JPS63276908A - Variable group delay time equalizer - Google Patents

Abstract

PURPOSE:To easily equalize a desired group delay time characteristic by connecting a midpoint of a secondary side of a hybrid transformer to ground through a variable resistor, providing a resistor circuit and a reactance circuit to both terminals so as to synthesize the signals and varying the variable components. CONSTITUTION:With an input signal given to an input terminal 1, the signal is inputted to the hybrid transformer 4 via a buffer amplifier 2 and a fixed resistor 3. The input signal is distributed into two signals whose phases are inverted to each other and outputted to a secondary winding of the transformer. One of the two signals is given to a resistance circuit and the other signal is given to a reactance circuit. Then the signal from the resistance circuit and the signal from the reactance circuit are synthesized and the result is given to an output terminal 13 via a fixed resistor 11 and a buffer amplifier 12. In adjusting a variable coil 8, a variable capacitor 9 and variable resistors 5, 6, a desired group delay time is equalized and the deviation in the frequency amplitude characteristic is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a group delay time equalizer, and particularly to flattening of variable group d delay time characteristics and frequency amplitude characteristics.

(Prior art) Conventionally, this type of group delay time equalizer was developed on October 2, 1971.
0th Institute of Electronics and Communication Engineers Mitsuyuki's "Transmission circuit network and filter"
Figure 5 (as described on pages 378-382)
A bridge T-type fixed 2-stroke delay time equalizer as shown in a) was used. FIG. 5(b) shows the basic circuit of the bridge T-type fixed two-way extension time equalizer shown in FIG. 5(a).

By the way, the operation transmission (e0) of the circuit shown in FIG. 5(a) or FIG. 5(b) is expressed as... (1).

Here, S is a complex angular frequency (=jω), a is a motion attenuation amount, and b is a motion phase field.

Figure 6 shows the arrangement of zero points and poles, and from the values a and b, Figure 5 <
If a>'t or in FIG. 5(b), the values of each element of the reception circuit are determined as 2 2 2 (3) ωo=a +b L2=C1Ro (6).

Here, R8 indicates characteristic impedance.

Furthermore, based on this Fig. 6, Fig. 5(a) or Fig. 5(
Determining the delay characteristics of the circuit shown in b), the total delay time □τ is determined by (12). The delay characteristics are shown in FIG.

Here, the characteristics shown in FIG. 7 change depending on the values of a and b in equation (1).

(Problems to be Solved by the Invention) As described above, in the conventional circuit, in order to obtain the desired secondary group rolling time characteristics, L, C1,
L2. Since the value of C,2 is uniquely determined, if a plurality of desired quadratic group delay interpolation characteristics, each different from each other, are required, the same number as the desired characteristics are required as shown in Figure 5 (a). It is necessary to provide a bridge T-type group redundant time equalizer as shown in FIG. Also, the center frequency f of the group delay time characteristic of the equalizer. Alternatively, if you try to tune the Chiken time to m as necessary, the input/output mismatch attenuation m and the frequency amplitude characteristics will change, so a bridge T-type group as shown in Fig. 5 (a) (b) may be used. Since the delay time equalizer cannot be adjusted once the design is completed and the manufacturing adjustment is completed, for example, an equalizer for the group delay time that occurs in a micro wireless line system requires a large number of equalizers. There was a big problem in that the group delay time characteristic, which changes in multiple ways, was required to be flattened to the maximum.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate this problem and provide a variable group delay time equalizer that can easily equalize desired group delay time characteristics that differ from each other.

[Structure of the invention]

(Means for Solving the Problems) The variable group delay time equalizer of the present invention has a first buffering means for inputting an input signal, and two buffering means whose phases are inverted from each other for the output j signal of the MW means. a hybrid transformer that divides the signal into two; a first variable element connected between the middle point of the secondary side of the hybrid 1-lance and ground; and a second variable resistor connected to one output of the hybrid transformer. a resistor circuit consisting of a series circuit of an element and a fixed resistance element, a reactance circuit connected to the other output of the hybrid transformer and having another variable capacitor connected in parallel to a series circuit of a variable coil and a variable capacitor, and the resistor. Features (Functions) The variable group D delay time equalizer of the present invention is characterized by comprising a second buffering means into which the output of the circuit and the output of the reactance are combined and input. Of the two signals outputted from the secondary side of the circuit and having mutually inverted phases, one signal is input to the resistance circuit, and the other signal is input to the reactance circuit. A signal obtained by combining the output signal from the resistance circuit and the output signal from the reactance circuit is input to the second Mlfi circuit.

By varying the reactance value of the reactance circuit, a signal equalized to the desired group length characteristic is output from the second buffer circuit. By varying one or both of them, the second buffer circuit outputs a signal whose frequency amplitude characteristic deviation has been corrected.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of the variable group delay time equalizer of the present invention. In the figure, the middle point of the secondary side of the hybrid transformer 4 and the ground are connected via a variable resistor 5. A resistance circuit in which a variable resistor 6 and a fixed resistor 7 are connected in series is connected to one output end on the secondary side of the hybrid transformer 4. Moreover, at the other output end on the secondary side of the hybrid transformer 4,
A reactance circuit in which a variable capacitor 10 is connected in parallel is connected to a series circuit of a variable coil 8 and a variable capacitor 9.

Then, the resistance circuit and the reactance circuit are combined, and the combination point is connected to the M impulse amplifier 1 via the fixed resistance 11.
Connected to 2.

In the configuration as described above, when an input signal is input to input terminal 1, the input signal is M-force j! The signal is input to a hybrid transformer 4 via a 4QFA unit 2 and a fixed resistor 3.

The signal input to the hybrid transformer 4 is divided into two signals whose phases are mutually inverted and output to the secondary side of the hybrid transformer.

One of the two signals is input to the resistance circuit, and the other signal is input to the reactance circuit. Then, the signal output from the resistance circuit and the signal output from the reactance circuit are combined and sent to the output terminal 13 via the fixed resistor 11 and the amplifier 12.

Here, by varying the inductance IL3 of the variable coil 8, the capacitance value C4 of the variable capacitor 9, and the capacitance value C3 of the variable capacitor 10 in the reactance circuit, the group delay time characteristics can be equalized to a desired one. .

Further, by varying the resistance value of one or both of the resistance values R5 and R6 of the variable resistors 5 and 6, the frequency amplitude characteristic deviation that occurs when the group delay time characteristic is varied is corrected.

By the way, the delay time of the circuit network in FIG. 1 is as follows: (13) where 20 = R2 + R10, 81 = ωC3 (susceptance). Here ω is the angular frequency.

Also, the delay time τ' at the series bar swing point is expressed by equation (13)
Substituting ω” 13C4=1 into τ′=413/Z
...(14).

FIG. 2 shows the input frequency versus phase characteristics of the embodiment shown in FIG.

In FIG. 1, the inductance value L3 of the variable coil 8
and the capacitance value C4 of the variable capacitor 9.
The capacitance value C3 of is varied. In this case, the values of the inductance ti L 3 and the capacitance value C4 are fixed to respective values at the series resonance frequency f.

As a result, the song shown in Figure 2? ! The phase characteristic becomes 20.21°22. The larger the capacitance value C3 of the variable capacitor 0 is, the steeper the phase characteristic 20 becomes.

FIGS. 3 and 4 show input frequency versus group delay time characteristics in the example.

In Fig. 1, the inductance fiiL of the variable coil 8
3 and the capacitance 1+i C4 of the variable capacitor 9 are fixed to 6 values at the frequency of the series resonance frequency fs.

Subsequently, by varying the capacitance DC3 of the variable capacitor 10, group delay time characteristics such as curves 30, 31, and 32 shown in FIG. 3 are obtained.

The larger the capacitance 11C3 of the variable capacitor 10 is, the steeper the group delay time characteristic 30 becomes.

Further, by fixing the capacitance value C3 and varying either the inductance value C3 or the capacitance value C4, the curves 40, 41, and 42 shown in FIG. 4 are obtained.
A group like ``becomes a time-long characteristic.

The frequency amplitude characteristic deviation that occurs when the group delay time characteristic is varied is determined by the resistance values R5 and R of the variable resistors 5 and 6.
The correction is made by varying the resistance value of one or both of the resistance values.

〔Effect of the invention〕

As explained above, the present invention can easily equalize the desired group delay time characteristic and at the same time correct the frequency amplitude characteristic deviation. Another advantage is that it can be applied to group delay time correction for microwave multiplexed radio line systems that require good performance and high quality.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the variable group delay time equalizer of the present invention, and FIG. 2 is a graph showing the phase characteristics of this embodiment.
3 and 4 are graphs showing the group delay time characteristics of this embodiment, FIG. 5 is a circuit diagram showing a conventional group delay time equalizer, and FIG. 6 shows the zero points and poles in FIG. FIG. 7 is a graph showing the conventional group delay time characteristics. 1... Input terminal, 2, 12... Buffer amplifier, 3, 7
゜11...Fixed resistance, 4...Hybrid transformer, 5゜6...Variable resistance, 8...Variable coil, 9,1
0...Variable capacitor, 13...Output terminal. s Figure 2 Figure 3 τ1 Figure 4 Lf (a) (b) Figure 5 Figure 7

Claims (1)

[Scope of Claims] A first buffer circuit that receives an input signal; a hybrid transformer that divides the output signal of the buffer into two signals whose phases are mutually inverted; and a secondary side of the hybrid transformer. a first variable resistance element connected between a point and ground; a resistance circuit connected to one output of the hybrid transformer and consisting of a series circuit of a second variable resistance element and a fixed resistance element; and the hybrid transformer. A reactance circuit is connected to the other output of the resistor circuit and has a second variable capacitor connected in parallel to a series circuit of the variable coil and the first variable capacitor, and the output of the resistor circuit and the output of the reactance are combined. A variable group delay time equalizer comprising: a second buffer circuit input to the variable group delay time equalizer.