JPS6056012B2 - Frequency characteristic adjustment circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a frequency characteristic adjustment circuit.

The transfer function T(s) of the frequency characteristic adjustment circuit having the frequency characteristic (quadratic type) as shown in Fig. 1 is 52+l+A)
ΔwS+wo2T(S)■52+(1+B)ΔwS+
It is shown as wo2゜'゛゜゜' (1).

W here. is the angular velocity of the resonant frequency of the filter, and Δw
indicates the bandwidth of the resonance characteristic of the filter. Also, let the angular velocity of the input signal be w and 5=iw.

Furthermore, A and B are constants that determine the filter characteristics, and at least one of them is zero, and T(s) has a band elimination characteristic with a dip corresponding to the value of B if A=0 as shown in Figure 1. It is well known that if B=0, a band pass filter characteristic having a peak corresponding to the value of A is exhibited.

Conventionally, a circuit like the one shown in FIG. 2 has been used as a method for realizing equation (1). In the figure, 1 and 2 are amplifiers,
3 is a bandpass filter. However, the bandpass filter used here is a double integral type circuit as shown in FIG. 3, and therefore has a very complicated configuration. In Fig. 3, 4 is an adder, 5 and 6 are integrators, and 7 and 8 are
is a feedback circuit. The present invention provides a frequency characteristic adjustment circuit with a simple configuration free from the above-mentioned drawbacks, and will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention.

In the figure, input terminal 17 is connected to one input terminal of first adder 11 . The output 21 of the adder 11 is branched into two branches, one of which is grounded through a series circuit consisting of a variable resistor 12 and a capacitor 13 and a parallel circuit consisting of a variable resistor 14 and a capacitor 15. The connection point 20 of the series connection circuit branches into two branches, one of which is connected to the feed forward circuit 2.
2 is applied to one input terminal of the second adder 19, and the other is applied to the other input terminal of the adder 11 via the feedback circuit 16. Said output 21 is also applied to the other input terminal of an adder 19, the output of which is led to the output terminal 18. Variable resistor 1
2 and 14 are linked and variable so that they always have the same resistance value. In the above configuration, the voltage at the input terminal 17 is u(s), the voltage at the output 21 of the adder 11 is E(s), the voltage at the common connection point 20 is E1(s), and the feedback circuit 1
6, the transfer coefficient of the feedforward circuit 22 is α, and the transfer function from the output 21 to the common connection point 20 is T1(s). In FIG. Let the resistance value of 12, 14 be R, and the capacitance of capacitors 13 and 15 be C, and calculate T1(s).
If we substitute equation (2) for the above equation, we substitute equation (5) for the above equation, we compare equations (1) and (6), and find the conditions under which both equations are equal. If the transfer coefficients β and α of the feedback and feedforward circuits 16 and 22 in FIG. 4 are set to β and α determined by equations (9) and (8), respectively, the transfer function T( s) can be realized.

Also, from equation (7), if the product of the values of the variable resistor 12 and the capacitor 13 and the product of the values of the variable resistor 14 and the capacitor 15 are both the same value CR, and this product CR is changed, the resonant frequency ω . can be changed. Figure 5 is the 4th
The transmission coefficients β and α of the feedback and feed forward circuits 16 and 22 in the figure are arranged to give Q (=WO/Δw), which indicates the quality of the resonant circuit, and the degree of amplification (or degree of attenuation) at the resonance point. The related A (or B) can be made variable independently, and the parts having the same functions as those in FIG. 4 are given the same reference numerals and the explanation thereof will be omitted.

In the figure, the adder 38 has input terminals 30, 31, 32, and 33, and the addition coefficient at each input terminal is 1.
, -1, -1 and 3. The adder 39 has input terminals 34, 35, 36 and 37, and the addition coefficients at each input terminal are set to 1, -3, 1 and 1, respectively. A common connection point 20 is connected to the input terminals 33 and 35 and to an amplifier 40. amplifier 40
The output is branched into four branches and connected to the input terminals 32 and 36, and via amplifiers 41 and 42 to the input terminals 31 and 37, respectively. In the above configuration, the amplifiers 40, 41 and Δw and 42
Let the amplification degrees of be 1, B, and A, respectively.
If WO, the circuit of FIG. 5 becomes equivalent to the circuit of FIG. 4.

Of course, in this case, it is assumed that the circuit shown in FIG. 4 satisfies equations (7), (8), and (9). In FIG. 6, the amplifier 40 in FIG. 5 is replaced by a variable resistor 47, and the amplifiers 41 and 42 are replaced by a variable resistor 48 whose midpoint is grounded and a fixed resistor 49, which corresponds to the amplification degree of the above amplifier. This allows the value to be easily set using each variable resistor. Buffer amplifiers 45 and 46 are inserted here to prevent the resistance values of the variable resistors from influencing each other. Note that the amplification degree of the buffer amplifier 45 is set to 1. Also, the amplification degree of the buffer amplifier 46 is determined by the resistor 49 and the variable resistor 48.
The attenuation at the maximum setting position of the voltage divider is compensated for, and the total amplification degree with the buffer amplifier 46 is set to be 1. Also, the addition coefficients for input terminals 31, 32, 36, and 37 are different from those in FIG. 5, and are applied to 11 -BO, -, 1, and AO, respectively. 9Q09Q0! 0 Therefore, if the variable resistor 48 is set on the adder 38 side, the resonant frequency W is determined by the above coefficient -8.

Is the degree of attenuation maximum at point 1? You can get dip 1+8 characteristics like that,
Also, if set on the adder 39 side, the center frequency W is determined by the addition coefficient .

A peak characteristic with a maximum amplification of 1+ can be obtained. Also, depending on the addition coefficient, the minimum value of Q becomes α. The maximum value of the amplification degree (attenuation degree) or the minimum value of Q mentioned above can be obtained by setting the variable resistors 47 and 48 on the side farther from the ground point, and by arbitrarily varying each variable resistor. Arbitrary amplification (attenuation), Q
You can get the value of

In the above description, it is assumed that the adders 38 and 39 are configured to multiply the signals applied to each input terminal by the respective addition coefficients and then add the signals.

Such an adder can be easily obtained by using, for example, an operational amplifier and various input resistors and feedback resistors corresponding to each addition coefficient, and a detailed description of the invention will be omitted.

As described above, according to the present invention, a quadratic frequency characteristic adjustment circuit can be realized with an extremely simple configuration using a feedback circuit and a feedforward circuit, and the transfer coefficients of the feedback circuit and the feedforward circuit can be set in a specific relationship. By doing this, it is possible to easily separate the coefficients related to the tuning frequency, peak, dip, and Q characteristics in a circuit, so each of these characteristics can be adjusted independently without being influenced by the other. It produces an excellent effect of being able to make it possible.

[Brief explanation of the drawing]

Figure 1 is a frequency characteristic diagram of a frequency characteristic adjustment circuit, Figure 2 is a block diagram of a conventional frequency characteristic adjustment circuit, and Figure 3 is a diagram of a conventional frequency characteristic adjustment circuit.
FIG. 4, FIG. J5, and FIG. 6 are block diagrams each showing an embodiment of the present invention. 11 and 19 are first and second adders, respectively, 16 is a feedback circuit, 22 is a feed forward circuit,
17 is an input terminal, and 18 is an output terminal/child.

Claims (1)

[Claims] 1. A first adder that adds an input signal and a feedback signal, a second adder that adds the output of the first adder and the feedforward signal, and an output of the first adder. means for serially connecting a series circuit comprising a first resistor and a capacitor and a parallel circuit comprising a second resistor and capacitor between a terminal and ground, the product of the first resistor and capacitor of the series circuit and the parallel circuit; a tuning frequency adjusting means that makes the product of the second resistor and the capacitor the same value and variable in conjunction with each other; and two constants, at least one of which is zero, are A and B, the bandwidth is Δω, and the tuning frequency is ω_0.
, the transfer coefficient is the addition coefficient of the second adder to the output of the first adder {(1+A)Δω/ω_0
-3} times the transmission coefficient circuit, which obtains the feedforward signal from the series connection point of the series circuit and the parallel circuit; The addition coefficient of the adder of 1 is {3-(1+
B) A frequency characteristic adjustment circuit comprising a second transfer coefficient circuit whose transfer coefficient is set to Δω/ω_0} times and which obtains the feedback signal from a series connection point between the series circuit and the parallel circuit.