JPS63276339A - Data transmission system - Google Patents

Abstract

PURPOSE:To contrive the miniaturization of an equipment by using a microcomputer so as to realize the establishment of bit synchronization by means of the software. CONSTITUTION:An arithmetic circuit 7 in the initial state makes a counted value latched by the initial edge detection signal 11 into an ideal bit synchronizing pattern to form a reference point of an edge data. Then the arithmetic circuit 7, in response to an edge detection signal 11, obtains an error between the actual input edge data and the ideal bit synchronizing pattern edge data and checks whether or not the obtained error is within the permissible range of the error of phase synchronization at the same time. When the error is within the permissible range, the arithmetic circuit 7 counts the number of input edges and obtains the error by a prescribed counted value and corrects the ideal edge data by taking the mean value as the difference between the reference edge and the actual input edge to form the reference edge.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data transmission systems requiring bit synchronization circuits.

Conventional technology In recent years, data transmission systems have been actively developed.

Hereinafter, with reference to the drawings, the PLL that controls the establishment of bit synchronization used in the conventional data transmission system described above will be explained.
An example of a (phase-locked loop) circuit will be described. FIG. 3 shows a block diagram of a conventional PLL circuit. In the figure, 21 is a phase comparator, 22 is a low-pass filter, 23 is a voltage controlled oscillator, 24 is an input signal, and 25 is an output signal.

The operation of the conventional PLL circuit configured as described above will be described below.

The phase comparator 21 has an input signal 24 and a voltage controlled oscillator 23.
The phase difference between the output signals 25 from the two is constantly compared. The voltage of the phase comparator 21 caused by this phase difference is smoothed by the low-pass filter 22 and acts as a control voltage for the voltage controlled oscillator 230, temporarily varying the frequency of the voltage controlled oscillator 23 and inputting the phase of the output signal 25. This serves to match the signal 24, that is, to perform automatic phase control.

Problems to be Solved by the Invention However, when the system is constructed using hardware as described above, the scale of the system becomes large and there is a problem that it is inconvenient to apply it to a portable device.

In view of the above problems, the present invention provides miniaturization of terminal equipment by realizing the function of the PLL circuit, that is, establishment of bit synchronization, using software using a microcomputer.

Means for Solving the Problems In order to solve the above problems, the bit synchronization circuit of the present invention includes a clock circuit that generates the same frequency for transmission and reception, a counter circuit that counts time using a clock signal,
An edge detection circuit detects the edges of the input waveform and generates an edge detection signal, a latch circuit uses the edge detection signal to latch the counter value of the counter circuit, and generates an ideal bit synchronization pattern to achieve ideal bit synchronization. Find the error in the counter value between the pattern and the edge of the input waveform,
An arithmetic circuit that calculates the average error with a certain specified number of edges, corrects the ideal bit synchronization pattern using the average error, and calculates the data sampling point, and the data sampling point (counter value) determined by the arithmetic circuit and the counter value of the counter circuit. The device is equipped with a comparator circuit that compares the input signals and generates a sampling signal for sampling the input signal when they match.

Operation The present invention has the above-described configuration, and the PLL circuit '111
Since G can be realized using microcomputer software, it is possible to downsize the device.

Embodiment Hereinafter, a bit synchronization circuit for a data transmission system which is an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a bit synchronization circuit in one embodiment of the present invention. FIG. 2 shows a calculation method for bit synchronization. In FIG. 1, 1 is an edge detection circuit, 2 is a clock circuit, 3 is a counter circuit, 4 is a launch circuit, 7 is an arithmetic circuit, 9 is a comparison circuit, 10 is an input signal, 1
1 is an edge detection signal, and 12 is a sampling signal.

The operation of the bit synchronization circuit configured as described above will be explained below with reference to FIGS. 1 and 2.

First, in this embodiment, it is assumed that the transmitting device sends out a bit synchronization pattern with a predetermined pulse width before transmitting data. However, due to the influence of various noises in the transmission system, jitter appears (input waveform a in Figure 2).

The clock circuit 2 generates the same frequency for transmission and reception, and the counter circuit performs counting using this signal.

When an edge detection circuit 1 detects an edge in an input signal 10, it generates an edge detection signal 11. Upon receiving this edge detection signal 11, the launch circuit 4 latches the counter circuit 3 as edge data.

In the initial state, the arithmetic circuit 7 uses the counter value latched by the first edge detection signal as the ideal bit synchronization pattern as the reference point of the edge data.

t'　O-t.

However, t'. : Reference point to of the edge data of the ideal bit synchronization pattern : Actual input edge data (counter value) After that, the arithmetic circuit 7 uses the edge data of the ideal bit synchronization pattern (Fig. 2, reference before correction) according to the edge detection signal. Find the error between waveform b) and the actual input edge data (input waveform a in Figure 2).

Δt10t″ ・−t・ However, t′,=t′, +T 1−I P i=l ~a t゛,: Edge data t of ideal bit synchronization pattern (: Actual input edge data (counter value) T2: Bit Check the synchronization pulse width and at the same time check whether the determined error is within the allowable phase synchronization error range.

-g<Δt, <g where i-1 to a g: Tolerable value of error of each edge (tolerable value of error of phase synchronization) If the error of each edge is not within the tolerance of error of phase synchronization, the calculation The circuit 7 returns to its initial state and re-establishes bit synchronization from the beginning.

If the error of each edge is within the permissible phase synchronization error range, the number of input edges is counted and the next input edge is waited for.

The above calculations are performed at a specified value (here, a) with the number of human edges.
When the number of input edges reaches a certain predetermined value, the above calculation is completed and the average error of each edge is calculated.

T-T+Δt1 Δt-T/(a-1) where i-1~a T: Total error of each edge (initially 0) This average error Δ
Since t is the difference between this reference edge and the actual human-powered edge, the arithmetic circuit 7 moves the latest ideal edge data t' by the average error Δt and sets it as the reference edge (Fig. 2 Reference waveform after correction) c) The arithmetic circuit 7 determines data sampling points based on this internal reference edge t'.

Hereinafter, the arithmetic circuit 7 calculates the counter value of the next sampling point and writes that value to the comparison circuit 9.
Now, compare this counter value with the counter value from the counter circuit 3, and if they match, the sampling signal 12 (second
Fig. Generate sampling signal d).

As described above, in this embodiment, P
Like the LL circuit, it only generates a sampling signal, but by taking input data into an arithmetic circuit using the sampling signal, it can perform error detection and correction on the data, and also performs other communication control. By integrating it with a microcontroller, further downsizing and cost reduction can be achieved.

Note that the configuration in this embodiment can be realized with a single chip using a single-chip microcomputer.

Effects of the Invention As described above, according to this embodiment, there is an internal counter circuit that generates the same frequency for transmission and reception, a counter circuit that counts time based on a clock signal, and an edge detection signal that is generated by detecting edges of an input waveform. an edge detection circuit that causes
A latch circuit that latches the counter value of the counter circuit using an edge detection signal, generates an ideal bit synchronization pattern, calculates the error in the counter value between the ideal bit synchronization pattern and the edges of the input waveform, and calculates the error of the counter value between the ideal bit synchronization pattern and the edges of the input waveform. An arithmetic circuit calculates the average error, corrects the ideal bit synchronization pattern using the average error, and calculates the data sampling point.The data sampling point (counter value) obtained by the arithmetic circuit is compared with the counter value of the counter circuit. By providing a comparison circuit that generates a sampling signal to sample the input signal when there is a match, the bit synchronization function can be realized using microcontroller software.
By integrating with other communication control microcontrollers, devices can be made smaller and lower in price.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bit synchronization circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram illustrating a calculation method for establishing bit synchronization, and FIG. 3 is a block diagram of a conventional PLL circuit. 1... Edge detection circuit, 2... Clock circuit, 3... Counter circuit, 4...
Latch circuit, 7... Arithmetic circuit, 9...
Comparison circuit, 10... Input signal, 11...
・Edge detection signal, 12...Sampling signal. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 3

Claims (1)

[Claims] a clock circuit that generates the same frequency in the transmitter/receiver; a counter circuit that counts time using the clock signal; an edge detection circuit that detects edges of an input waveform and generates an edge detection signal; A latch circuit that latches the counter value of the circuit, generates an ideal bit synchronization pattern, calculates the error in the counter value between the ideal bit synchronization pattern and the edge of the input waveform, and calculates the average error with a certain specified number of edges. an arithmetic circuit that calculates sampling points by correcting the ideal bit synchronization pattern using the average error; and a data sampling point (counter value) obtained by the arithmetic circuit.
and a comparison circuit that compares the counter values of the counter circuit and generates a sampling signal for sampling an input signal when they match.