JPS63275147A - Manufacture of hermetically sealed type semiconductor device - Google Patents
Manufacture of hermetically sealed type semiconductor deviceInfo
- Publication number
- JPS63275147A JPS63275147A JP62111822A JP11182287A JPS63275147A JP S63275147 A JPS63275147 A JP S63275147A JP 62111822 A JP62111822 A JP 62111822A JP 11182287 A JP11182287 A JP 11182287A JP S63275147 A JPS63275147 A JP S63275147A
- Authority
- JP
- Japan
- Prior art keywords
- sealing material
- ceramic
- ceramic base
- glass sealing
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000919 ceramic Substances 0.000 claims abstract description 53
- 239000011521 glass Substances 0.000 claims abstract description 40
- 239000003566 sealing material Substances 0.000 claims abstract description 34
- 238000007789 sealing Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims 1
- 230000003068 static effect Effects 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 239000000565 sealant Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000005394 sealing glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は気密封止形半導体装置の製造方法に関し、特に
ガラス封止材を用いる気密封止形半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hermetically sealed semiconductor device, and more particularly to a method for manufacturing a hermetically sealed semiconductor device using a glass sealing material.
従来、この種の半導体装置の製造方法は、まづ第３図に
示すように半導体素子１を銀ペーストなどにより固定し
且つ半導体素子１の電極（図示せず）と各リード３とを
金属細線４・にて電気的に接続したセラミックベース２
と、第４図に示すように、被着面にガラス封止材７を塗
布しその一部に切欠部を形成したセラミックキャップ６
とを重ねて荷重をかけながら４００〜５００℃の温度で
ガラス封止材７を溶かして封止していた。Conventionally, in the manufacturing method of this type of semiconductor device, as shown in FIG. Ceramic base 2 electrically connected at 4.
As shown in FIG. 4, a ceramic cap 6 has a glass sealing material 7 applied to the adhered surface and a notch formed in a part of the glass sealing material 7.
The glass sealing material 7 was melted and sealed at a temperature of 400 to 500° C. while applying a load.
しかしなから、上述した従来の気密封止による半導体装
置の製造方法は、第４図に示すように、セラミックキャ
ップ６とセラミックベース２との封止部において、キャ
ップに被着させたガラス封止材の切欠部が完全に埋まら
ないで流れ不足部９が発生し、封止不良の原因となると
いう欠点がある。すなわち、従来はセラミックベース２
側にはガラス封止材を塗布しないためにかかる流れ不足
が発生していた。However, as shown in FIG. 4, in the conventional method of manufacturing a semiconductor device using hermetic sealing described above, in the sealing portion between the ceramic cap 6 and the ceramic base 2, a glass seal is applied to the cap. There is a drawback that the notch in the material is not completely filled, resulting in insufficient flow 9, which causes sealing failure. In other words, conventionally ceramic base 2
This lack of flow occurred because the glass sealing material was not applied to the sides.
本発明の目的は、かかるガラス封止材の流れ不足部およ
びはみ出し部を生じないような気密封止形半導体装置の
製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a hermetically sealed semiconductor device that does not cause such insufficient flow areas and protrusion areas of the glass sealing material.
本発明は中央部に半導体素子を搭載したセラミックベー
スと、セラミックキャップとをガラス封止材を介して接
着する気密封止形半導体装置の製造方法において、前記
セラミックベースと前記セラミックキャップとの両被着
面にガラス封止材を塗布し、少なくとも一方のガラス封
止材の一部に切欠部を形成した後、前記セラミックベー
スと前記セラミックキャップとを加熱および圧着して封
着するように構成される。The present invention provides a method for manufacturing a hermetically sealed semiconductor device in which a ceramic base having a semiconductor element mounted in the center and a ceramic cap are bonded together via a glass sealing material. After applying a glass sealing material to the mounting surface and forming a notch in a part of at least one of the glass sealing materials, the ceramic base and the ceramic cap are sealed by heating and pressure bonding. Ru.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）はそれぞれ本発明の第一の実施例
を説明するための半導体装置におけるセラミックベース
の斜視図およびセラミ・ソクキャ・ンプの斜視図である
。FIGS. 1(a) and 1(b) are a perspective view of a ceramic base and a ceramic base in a semiconductor device, respectively, for explaining a first embodiment of the present invention.
第１図（ａ）に示すように、セラミックベース２はその
上部の周囲に、すなわち後述するセラミックキャップと
の被着面にガラス封止材５を切れ目なく塗布する。次に
、半導体素子１をアイランド上に銀ペーストなどにより
固定した後、金属細線４により半導体素子１の電極（図
示省略）とのボンディング接続を行い、各リード３との
間を電気的に接続する。As shown in FIG. 1(a), a glass sealing material 5 is seamlessly applied around the upper part of the ceramic base 2, that is, on the surface to which a ceramic cap, which will be described later, is adhered. Next, after fixing the semiconductor element 1 on the island with silver paste or the like, bonding is performed with the electrodes (not shown) of the semiconductor element 1 using thin metal wires 4 to electrically connect each lead 3. .
一方、第１図（ｂ）に示すよう呻、セラミックキャップ
６は前述したセラミックベース２との被着面にガラス封
止材７を塗布され且つ各辺のほぼ中央に計４ケ所の切欠
部９が形成される。尚、このカラス封止材７もあらかし
め半導体素子１−をセラミックベース２に固定する前に
セラミックベース２と同様に塗布しておく。On the other hand, as shown in FIG. 1(b), the ceramic cap 6 is coated with a glass sealing material 7 on the surface to which it is attached to the ceramic base 2, and has a total of four notches 9 approximately in the center of each side. is formed. Incidentally, this glass sealing material 7 is also applied in the same manner as the ceramic base 2 before fixing the semiconductor element 1- to the ceramic base 2.
かかるカラス封止材が塗布されたセラミックベース２と
セラミックキャップ６とに対し、荷重をかけなから４０
０〜５００ ’Ｃに加熱し封止カラスを融かすことによ
り封止を行なう。この方法により、従来ガラス封止有の
絶対量の不足により完全に埋まらなかった切欠部８が容
易に埋まるようになり、また封止不良をも無くすことが
できる。Do not apply any load to the ceramic base 2 and ceramic cap 6 coated with such glass sealing material.
Sealing is performed by heating to 0-500'C to melt the sealing glass. By this method, the notch 8, which was not completely filled due to the lack of absolute amount of glass sealing in the past, can be easily filled, and it is also possible to eliminate sealing defects.
第２図（ａ）、（ｂ）はそれぞれ本発明の第二の実施例
を説明するための半導体装置におけるセラミックベース
の斜視図および半導体装置の側面図である。前述の第一
の実施例においては、セラミックベースとセラミックキ
ャップとの両方にガラス封止材があるため、封止時にガ
ラス封止材のはみだしによる不良が発生する可能性もあ
る。その点を考慮したのが第二の実施例である。FIGS. 2(a) and 2(b) are a perspective view of a ceramic base in a semiconductor device and a side view of the semiconductor device, respectively, for explaining a second embodiment of the present invention. In the first embodiment described above, since there is a glass sealing material in both the ceramic base and the ceramic cap, there is a possibility that defects may occur due to the glass sealing material protruding during sealing. The second embodiment takes this point into consideration.
第２図（ａ）に示すように、まづセラミックベース２の
各辺中央にカラス封止材５を塗布する。As shown in FIG. 2(a), first, a glass sealing material 5 is applied to the center of each side of the ceramic base 2.
しかる後、半導体素子１を固定し金属細線１によりリー
ド３との電気的接続を完成させる。尚、前記ガラス封止
材５の塗布寸法はセラミックキャップのガラス封止材の
切欠部寸法よりも小さくする。Thereafter, the semiconductor element 1 is fixed and the electrical connection with the leads 3 is completed using the thin metal wires 1. Incidentally, the coating size of the glass sealing material 5 is made smaller than the size of the notch of the glass sealing material of the ceramic cap.
次に、第２図（ｂ）に示すように、前述の切欠−５＝
部寸法とすれば、セラミックベース２とセラミックシャ
ツプロを重ねた場合にも、それぞれセラミックベース２
とセラミックキャップ６のガラス封止材５および７を重
ならないようにすることによりガラス封止材５および７
によって形成される切欠部８を実質的に小さくすること
ができる。通常、かかるガラス封止材の塗布は印刷技術
により形成する。また、切欠部は０，６關が最小値であ
るが、本実施例を適用すれば切欠部を０．１關まで小さ
くすることができるため、流れ不足を除去てきる。更に
、被着部にガラス封止材の重なる部分がないため、封止
時のカラス封止材のはみだしによる不良も除去すること
ができる。Next, as shown in Fig. 2(b), if the above-mentioned notch -5 = part dimension, even when Ceramic Base 2 and Ceramic Shirt Pro are stacked, each Ceramic Base 2
By making sure that the glass sealing materials 5 and 7 of the ceramic cap 6 do not overlap, the glass sealing materials 5 and 7 of the ceramic cap 6 are
The notch 8 formed by this can be made substantially smaller. Typically, such glass encapsulant coatings are formed by printing techniques. Further, the minimum value of the notch is 0.6 degrees, but if this embodiment is applied, the size of the notch can be reduced to 0.1 degrees, thereby eliminating insufficient flow. Furthermore, since there is no overlapping portion of the glass sealant in the adhered portion, defects caused by protrusion of the glass sealant during sealing can be eliminated.
尚、上述の実施例における切欠部は、カラス材に直接形
成してもよく、またセラミックベースとセラミツスペー
スとを合わせたときに両方のカラス封止林間で実質的に
同様な溝の如き切欠部を形成してもよい。Note that the notch in the above-mentioned embodiment may be formed directly in the glass material, and when the ceramic base and the ceramic space are combined, the groove-like notch is substantially the same in both the glass-sealed spaces. It may also form a section.
以上説明したように、本発明はセラミックキャ６一
ツブと、セラミックベースとの両方にガラス封止材を被
着し、少なくとも一方のカラス封止材に切欠部を形成し
た後、加熱および圧着して封着することにより、ガラス
封止材の流れ不足およびはみだしによる封止不良を除去
できるという効果がある。As explained above, the present invention applies glass sealing material to both the ceramic cap and the ceramic base, forms a notch in at least one of the glass sealants, and then heats and presses the glass sealant. This has the effect of eliminating sealing defects due to insufficient flow and protrusion of the glass sealing material.
第１図（ａ’）、（ｂ）はそれぞれ本発明の第一の実施
例を説明するための半導体装置におけるセラミックベー
スの斜視図およびセラミックキャップの斜視図、第２図
（ａ）、（ｂ）はそれぞれ本発明の第二の実施例を説明
するための半導体装置におけるセラミックベースの斜視
図および半導体装置の側面図、第３図は従来の一例を説
明するためのセラミックベースの斜視図、第４図は従来
の気密封止形半導体装置の一部切り欠き斜視図である。
１・・・半導体素子、２・・・セラミックベース、３・
・・リード、４・・・金属細線、５，７・・・ガラス封
止材、６・・・セラミックキャップ、８・・・切欠部。FIGS. 1(a') and (b) are a perspective view of a ceramic base and a ceramic cap in a semiconductor device for explaining the first embodiment of the present invention, and FIGS. 2(a) and (b), respectively. ) are respectively a perspective view of a ceramic base in a semiconductor device and a side view of the semiconductor device for explaining a second embodiment of the present invention, and FIG. 3 is a perspective view of a ceramic base for explaining a conventional example. FIG. 4 is a partially cutaway perspective view of a conventional hermetically sealed semiconductor device. 1... Semiconductor element, 2... Ceramic base, 3...
...Lead, 4...Metal thin wire, 5, 7...Glass sealing material, 6...Ceramic cap, 8...Notch.
Claims (1)
ラミックキャップとをガラス封止材を介して接着する気
密封止形半導体装置の製造方法において、前記セラミッ
クベースと前記セラミックキャップとの両被着面にガラ
ス封止材を塗布し、少なくとも一方のガラス封止材の一
部に切欠部を形成した後、前記セラミックベースと前記
セラミックキャップとを加熱および圧着して封着するこ
とを特徴とする気密封止形半導体装置の製造方法。In a method for manufacturing a hermetically sealed semiconductor device in which a ceramic base having a semiconductor element mounted in the center and a ceramic cap are bonded together via a glass sealing material, the bonding surfaces of both the ceramic base and the ceramic cap are bonded. Hermetic sealing characterized by applying a glass sealing material, forming a notch in a part of at least one glass sealing material, and then heating and pressing the ceramic base and the ceramic cap to seal them. A method for manufacturing a static semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111822A JPS63275147A (en) | 1987-05-07 | 1987-05-07 | Manufacture of hermetically sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111822A JPS63275147A (en) | 1987-05-07 | 1987-05-07 | Manufacture of hermetically sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63275147A true JPS63275147A (en) | 1988-11-11 |
Family
ID=14571028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111822A Pending JPS63275147A (en) | 1987-05-07 | 1987-05-07 | Manufacture of hermetically sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63275147A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0310542U (en) * | 1989-06-19 | 1991-01-31 | ||
| JPH0547948A (en) * | 1991-08-09 | 1993-02-26 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPH06151620A (en) * | 1992-11-10 | 1994-05-31 | Ngk Insulators Ltd | Method of sealing cap of package for enclosing semiconductor chip |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61256656A (en) * | 1985-05-08 | 1986-11-14 | Fujitsu Ltd | Semiconductor device |
-
1987
- 1987-05-07 JP JP62111822A patent/JPS63275147A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61256656A (en) * | 1985-05-08 | 1986-11-14 | Fujitsu Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0310542U (en) * | 1989-06-19 | 1991-01-31 | ||
| JPH0547948A (en) * | 1991-08-09 | 1993-02-26 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPH06151620A (en) * | 1992-11-10 | 1994-05-31 | Ngk Insulators Ltd | Method of sealing cap of package for enclosing semiconductor chip |
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