JPS63273959A - Serial communication system - Google Patents

Abstract

PURPOSE:To prevent the step-out due to the noises produced in a period when no communication is carried out by securing such a constitution where a microcomputer B received a synchronizing clock sends an answer signal to a microcomputer A in case a counter has an overflow. CONSTITUTION:The communication is started when a tuner controller A sets START at H and a synchronizing clock SCK is transmitted. A deck controller B delivers the data So at the fall of the clock SCK and fetches the data Si at the rise of the clock SCK. The controller A delivers the data Si at the fall of the clock SCK and fetches the data So at the rise respectively. When a serial shift counter has an overflow, READY is set at H. Hereafter the actual transmission/reception of data is started and the hitherto data are neglected. If 4 bits, for example, are set for the serial data of a single time, the START, and SCK are all set at L as soon as the transmission/reception of the serial data is through.

Description

[Detailed Description of the Invention] 1. Summary In communication between microcomputers using serial ports, synchronization clocks are counted multiple times to achieve synchronization, thereby preventing data shift due to noise during non-communication.

[Industrial application field]

The present invention relates to a serial communication system between microcomputers.

[Conventional technology]

In a system where one microcomputer (hereinafter abbreviated as microcomputer) performs serial communication while providing a synchronized clock to the other microcomputer, synchronization may occur if noise enters the clock line during non-communication times when no synchronized clock is sent.

[Problem that the invention seeks to solve]

The above-mentioned synchronization error invalidates the serial data during subsequent communication. Therefore, in the present invention, the noise resistance is improved by counting the synchronization error a plurality of times before starting communication.

(Means for solving the problem) Fig. 1 is a basic configuration diagram of the present invention, where A and B are microcomputers that perform serial communication.Microcomputer B has a synchronous clock S
There are ports for CK, response signals RIIA, DY, and serial data out 30% serial data in St.

[Effect]

(1) First, microcomputer A provides synchronization clock SCK several times to microcomputer B. (2) Upon receiving this synchronization clock SCK, microcomputer B counts with a serial shift counter, and when the counter overflows, it sends back a response signal READY to microcomputer A to notify that synchronization has been achieved. ■Microcomputer A°, which has received REA port Y, sends serial data Si to microcomputer B in synchronization with the synchronous clock SCK, and at the same time sends serial data S from microcomputer B.
Receive o.

In this way, even if noise enters the clock line before microcomputer A transmits the synchronization clock SCK, if the noise is less than the number that overflows the serial shift counter, READY will not occur, and malfunctions can be prevented.

〔Example〕

FIG. 2 is a block diagram showing one embodiment of the present invention, in which A is a tuner controller, B is a deck controller, C is a tuner, D is a cassette deck, E is a key input section, and F is a display section. The key power section E and the display section F are provided on the tuner C side, but they are also shared on the deck D side, so the key power required for deck control is transmitted from the tuner controller A to the deck controller B using serial data Si. In addition, the display data necessary for display control is transferred from the deck controller B to the tuner controller A using serial data So.
need to be sent to.

■~■ correspond to the procedure shown in Fig. 1, but in this example, the procedure ■ further involves transmitting the start signal 5TAIT from microcomputer A.
Added. This is due to long-term accumulated noise that causes the serial shift counter to overflow and incorrectly indicate READY.
This is to prevent this from occurring.

FIG. 3 is a time chart showing the operation. First, when the tuner controller A sets 5TART to "H", communication starts and the synchronous clock SCK is transmitted. The deck controller B outputs the data So at the falling edge of the clock SCK.
is output, and data Si is taken in at the rising edge. Tuner controller A outputs data St at the falling edge of clock SCK.
It outputs □ and takes in data S11 again at the rising edge. Then, if the serial shift counter overflows, R
Set EADV to “H”. From here, the actual data (hatched area) begins to be sent and received, and the data up to that point is ignored.

If one serial data is, for example, 4 bits, 5TART and READY will be sent at the end of the transmission/reception.

All SCKs become "L".

FIG. 4 shows the processing of the tuner controller A and the deck controller B. The tuner controller has the initiative to start and end communication, and it is controlled by the 5TART H"111.
'' to the deck controller. The deck controller performs synchronization and notifies the tuner controller of the synchronization using RE^mouth Y. Data is sent and received at the same time on both sides.

〔Effect of the invention〕

As described above, according to the present invention, in a serial communication system between microcomputers, there is an advantage that synchronization deviation due to noise during periods of non-communication can be prevented.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of the present invention, Figure 2 is a configuration diagram showing an embodiment of the invention, Figure 3 is a time chart showing the operation of Figure 2, and Figure 4 is the processing of the controller in Figure 2. It is a flowchart which shows. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi (α) Chu T Control O-1 side Figure 4

Claims (1)

[Claims] A synchronous clock (SCK) is sent from one microcomputer (A) to the other microcomputer (B), and the microcomputer (B) that receives the synchronous clock (SCK) counts with a serial shift counter, and the counter If the response signal (REA) overflows, the response signal (REA
DY) is returned to the microcomputer (A), and from the next synchronous clock (SCK) both microcomputers (
A serial communication method characterized by transmitting and receiving serial data (S_0, Si) in A and B).