JPS63272261A - Picture information reader - Google Patents

Abstract

PURPOSE:To attain the reproduction of pseudo intermediate tone by generating a clock signal reading a picture signal in the unit of dots from an image sensor and a threshold value signal whose value changes synchronously with the said detection signal as reference signals. CONSTITUTION:A picture signal OS outputted from a terminal No.1 of an image sensor 29 is fed to a noninverting input terminal of a comparator 42 through a resistor 41 from a transistor 40. A comparator 63 compares a rotation detection signal with a reference voltage to generate a step pulse ST and supplies it to a threshold value signal generating circuit 39. Thus, the reference signal is changed in the unit of dots of the picture signal OS in response to a data whose threshold value is changed such as, e.g., the organized dither method and since the voltage of the threshold value signal is 16-stage, the picture data VD expressing the intermediate tone of the pseudo 17-gradation is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image information reading device, and more particularly to a device that reads image information by manually scanning a document.

2. Prior Art The present applicant has disclosed in Japanese Patent Application No. 176300/1983 that images of the original are repeatedly read by a one-dimensional image sensor while the original is slidingly scanned, and serial image data is obtained. We proposed an image information reading device that generates and outputs a detection signal for each amount of displacement.

In the above device, the image sensor has the configuration shown in FIG. In the figure, the photodiode 10 has a multi-stage configuration, and photoelectric conversion is performed at the pixels in each stage. Photodiode 1
The charges obtained in the odd and even pixels of 0 are accumulated in each stage of the transfer gates 11 and 12, respectively, and are stored in each stage of the transfer gates 11 and 12 by the address reset signal AR input from the terminals 11a and 12a, respectively. The accumulated charges in the stages are transferred to CODs (charge coupled devices) 13 and 14, respectively. C0D13.14
clock signal φ coming from terminal 138, 14a, respectively.
1A, φ1B, clock signals φ2A, φ with opposite phase
The signals are transferred by each 2B and output serially. C
The signal output from 0D13.14 is supplied to output gate 15.

The output gate 15 alternately switches the signals coming from each of the CCDs 13 and 14 and outputs them from the terminal 16 when the address up signal AU coming to the terminal 15a is at L level. When the address up signal U is at H level, it is a period in which the signal charge of the output gate 15 is emptied. As a result, the image signal O8 is output from the terminal 16.

This image signal O8 is compared with a certain reference signal in a comparator, converted into digital image data, and outputted serially.

Problems to be Solved by the Invention Conventional image information reading bags generate binary image data by comparing the image signal O8 with a constant reference signal. For this reason, there is no problem when the original image is a document or a screen, but when a halftone image such as a photograph is read, the problem is that the pseudo halftone cannot be reproduced even using this image data. was there.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an image information reading device that obtains image data that can reproduce pseudo-halftones.

Means for Solving the Problems In the apparatus of the present invention, the threshold signal generation circuit generates a clock signal for reading out image signals in units of dots from the image sensor and a threshold signal whose value changes in synchronization with the detection signal. Generate as a reference signal.

Operation In the present invention, a threshold signal included in the reference signal changes in correspondence with the dots of the image signal, and this threshold signal is, for example, a threshold for systematic dithering. Since the image signal is compared with this reference signal to obtain image data, pseudo halftones can be reproduced using the obtained image data.

Example FIG. 1 shows a circuit diagram of an embodiment of the device of the present invention.

In the figure, 20 is a reset circuit, which is a power supply? When the 'fi pressure exceeds a predetermined level, the monostable multivibrator (
(hereinafter referred to as "mono multi") 21 is operated. The mono multi 21 constitutes an oscillation circuit 24 together with an inverter 22 and a mono multi 23, and the oscillation signal output from the Q terminal of the mono multi 23 is supplied to a NAND circuit 25, and σ
An inverted oscillation signal as shown in FIG. 2(B) outputted from the terminal is supplied to the load terminal LD of the counter 26. Further, an oscillation signal as shown in FIG. 2(A) outputted from the oscillation circuit 27 is supplied to the trigger pin of the counter 26.

The counter 26 counts the signals input to the terminal T when the terminal LD is at H level, and outputs the signals to the terminals QB and QC.

Figures 2 (C) and (D) from QD and RCO, respectively.

Signals as shown in (E) and (F) are output.

The NAND circuit 25 generates the address reset signal AR shown in FIG. 2 (CG) from the inverted signal of FIG. 2 (B) and the signal of FIG. 2 (E), and this signal is sent from the terminal 28 to the interface circuit. (not shown) and
The signal is supplied to the No. 10 terminal of the image sensor 29 via the inverter 34.

The NAND circuit 30 generates an address up signal AtJ shown in FIG. 2 (J) from the signals of FIG. The signal is supplied to the 16th terminal of the image sensor 29 via.

The NAND circuit 32 generates the write signal WG shown in FIG. 2(K) from the signals of FIGS. 2(C), (D), and (E), and supplies this signal to the interface circuit from the terminal 33.

Furthermore, the signals shown in FIG. 2(D) are inverted by the inverter 36, and the clock signals φ2A and φ2B shown in FIG. 2(1) are generated.
The clock signals φIA and φ1B are supplied to the 4th and 13th terminals of the image sensor 29 through the inverter 37 and 38 as shown in FIG.

Supplied to terminal 18.

These inverters 34 to 36, 38 each perform signal inversion and signal voltage conversion, and connect the NAND circuits 25, 30, 32 with a positive power supply voltage of +5V, the inverter 37, and the image sensor 29 with a positive power supply voltage of +12V. I have an interface.

Further, each of the address reset signal AR and address up signal AU is supplied to a threshold signal generation circuit 39.

The image sensor 29 is a one-dimensional C0D with 1024 dots.
(Charge Coupled Device) Sen.
For example, TCD107G is used, and its structure is as shown in FIG.
It has an output gate 15 which is supplied with a 3.14 output serial signal and outputs an image signal.

FIG. 2 (
In contrast to the clock signals φ2A and φ2B shown in I), the address up signal ALJ supplied to the output gate 15 of the image sensor 29 has the same period as the clock signal as shown in FIG. 2(J).

Therefore, at the output gate 15, the signal of the odd pixel supplied from the CCD 13 and the signal of the even pixel supplied from the CDCl2 are added to obtain the image signal O8, which is output from the No. 1 terminal of the image sensor 29. .

The image signal O8 outputted from the No. 1 terminal of the image sensor +J29 is supplied from the transistor 40 through the resistor 41 to the non-inverting input terminal of the comparator 42. Further, the image signal O8 from the transistor 40 is supplied from a resistor 43 through a peak hold diode 44 to an integrating circuit composed of a capacitor 45 and a resistor 46. The integral value obtained here is supplied to the base of the transistor 47 as a shading correction signal.

Here, even if the image signal O8 reads an original of uniform whiteness, shading occurs, which is dark at both ends of the line and bright at the center of the line, as shown by the solid line in FIG. 3(A). This occurs due to the characteristics of the light source and lens.

However, in the above embodiment, by integrating the image signal O8, the shading correction signal changes to follow the shading as shown by the broken line in FIG. 3(A), so that shading correction is performed.

By the way, the light emitting diode 60 and the phototransistor 61
A rotary encoder is installed between the two. This rotary encoder is a disk having radial slits at equal angular intervals, and rotates as the image information reading device slides and scans. The phototransistor 61 becomes conductive when light from the light emitting diode 60 enters through the slit, and becomes conductive, for example, eight times for one original sliding scan of the reading device.

The rotation detection signal of the approximately sinusoidal pulsating current output from the phototransistor 61 is supplied to the non-inverting input terminal of the comparator 63 via the resistor 62, and from the resistor 64, passes through the diode 65 to the capacitor 66, the resistor 67, etc. The integral value obtained here is supplied to the inverting input terminal of the comparator 63 as a reference voltage.

The comparator 63 compares the rotation detection signal with the reference voltage to generate a step pulse ST, and this step pulse ST is supplied to the threshold signal generation circuit 39, and
The signal is supplied from the terminal 68 to the interface circuit.

The three threshold signal generation circuits have the configuration shown in FIG.

In FIG. 4, an address up signal AU, an address reset signal AR, and a step pulse ST are input to terminals 70a, 70b, and 70c, respectively.

The column counter 71 is a 2-bit counter, and is shown in FIG.
After being reset by the falling edge of the address reset signal AR shown in A), the count is incremented at the rising timing of the address up signal AU shown in FIG. 5(B). Bit count value △
1. AO is supplied to the ROM 73 as a column address.

The row counter 72 is a 2-bit counter, and is shown in FIG.
It is counted up at the rising timing of the step pulse ST shown in A), and its internal state is shown in FIGS.
It changes as shown in D).

The row counter 72 latches the internal state at the falling timing of the address reset signal AR shown in FIG. 6(B),
2-bit count value A3 shown in FIGS. 6(E) and (F)
．． A2 is supplied to the ROM 73 as a row address. In this way, the count value A3 is changed in synchronization with the fall of the address reset signal AR immediately after the rise of the step pulse ST.
．． The reason for outputting A2 is that the count value A3.A2 is not synchronized with the address reset signal AR. This is because if A2 changes, the arrangement of the threshold values of the systematic dither method will shift, and the pseudo halftones will become unnatural.

ROM 73 is accessed by a total of 4 bits of column and row addresses to read the 4-bit threshold value. As shown in FIG. 7(A), the ROM 73 stores in advance threshold data of values 0 to 15 in hexadecimal notation corresponding to column address values 0 to 3 and row address values 0 to 3. There is. The threshold data in FIG. 7(A) is arranged using the Bayer method, which is one of the systematic dither methods.

In addition, instead of the Bayer method, the threshold arrangement of the halftone method as shown in FIG. 7(B), the spiral method as shown in FIG. 7(C), or the threshold of the systematic dither method as shown in FIG. 7(C) may be used. Value placement may also be performed.

The column counter 71 is counted up in synchronization with the address up signal AU, and the row counter 72 is counted up in synchronization with the address reset signal AR by the step pulse ST. Therefore, the threshold data read from the ROM 73 is counted up by the image sensor. Image signal O output from 29
It changes according to the number 8 dot.

The 4-bit threshold value read from ROM73 is D/A
The converter 74 converts the signal into an analog threshold signal as shown in FIG. 3(B), and outputs the signal from a terminal 75. This threshold signal is provided to transistor 48 shown in FIG.

Transistors 47 and 48 constitute a mixing circuit together with resistors 49a and 49b, and in this mixing circuit, the threshold signal is added to the shading correction signal to generate a reference signal. This reference signal is supplied to the inverting input terminal of comparator 42 via resistors 50a and 50b. By the way, the capacitor 51 is for noise removal.

The comparator 42 compares the image signal O8 with a reference signal to generate digital image data VD, which is sent to the terminal 52.
to an interface circuit (not shown).

As described above, in the above embodiment, the reference signal changes in units of dots of the image signal O8 in accordance with data whose threshold value changes, such as the systematic dither method, and the voltage of the threshold signal is 1.
Since there are six levels, it is possible to obtain image data VD that can express halftones of pseudo 17 gradations.

By the way, 80 is a three-terminal regulator, and the voltage is +5 from the power supply voltage Vc c (=+12V) from the terminal 81.
Generate v, monomulti 21.23, counter 26,
The light is supplied to the light emitting diode 60 and the like.

Note that image data VD that reproduces pseudo halftones can be obtained without adding the shading correction signal to the threshold signal. Therefore, the threshold signal itself output from the threshold signal generation circuit 39 may be supplied to the comparator 42 as a reference signal, and the present invention is not limited to the above embodiment.

Effects of the Invention As described above, according to the apparatus of the present invention, it is possible to obtain image data capable of reproducing pseudo halftones, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the device of the present invention, FIG. 2 is a waveform diagram of a timing signal generated by the device of FIG. 1, and FIG. 3 is a signal waveform of a shading correction signal and a threshold signal. Figure 4 is a block system diagram of one embodiment of the threshold signal generation circuit, Figures 5 and 6 are signal waveform diagrams of each part of the circuit in Figure 4, and Figure 7 is the threshold data of the ROM. FIG. 8 is a block system diagram of an embodiment of the image sensor. 29... Image sensor, 39... Reference signal generation circuit, 42.63... Comparator, 71... Column counter, 72... Row counter, 73... ROM, 74
...D/A converter. Patent applicant Mitsumi Electric Co., Ltd. Figure 3 Figure 4 Figure 5 Figure 6 fFrfl-1 Figure 7

Claims (1)

[Claims] A one-dimensional image sensor reads the image of the original by sliding the original, and compares the image signal serially output by the image sensor dot by dot with a reference signal to generate digital image data. In an image information reading device that obtains a detection signal every predetermined displacement amount of the sliding scan, a clock signal for reading out an image signal in units of dots from the image sensor and a threshold whose value changes in synchronization with the detection signal. An image information reading device comprising a threshold signal generation circuit that generates a value signal as the reference signal.