JPS63272210A - Agc circuit - Google Patents

Abstract

PURPOSE:To attain the small sized device, to improve the reliability and to reduce the manufacture cost and man-hour by using a multiplier multiplying an input signal with an amplitude control signal represented in a digital value, a comparator comparing an output signal amplitude of the multiplier with a preset comparison value and a digital filter circuit. CONSTITUTION:A comparator 2 compares whether or not the amplitude of an ARF signal being an output signal of a multiplier 1 is larger or smaller than a reference amplitude. In the case of the amplitude of the ARF signal larger than the reference amplitude, since the comparator outputs a down-pulse, the count of an up-down counter 3 is being decremented. The multiplier 1 decreases the amplitude of an input RF signal according to the count. Moreover, when the amplitude of the ARF signal is smaller than the reference amplitude conversely to above, the multiplier 1 increases the amplitude of the input RF signal. Thus, the amplitude of the ARF signal being an output signal of the multiplier 1 is controlled to be always a constant amplitude. Thus, it is not required tg mount a comparatively large capacitance separately externally to decrease the size of the device and to attain high reliability and to reduce the manufacturing man-hour and cost.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal reproduction technique in a reproduction apparatus for reproducing digital information, such as a digital audio disc player.

2. Description of the Related Art In recent years, as digital information recording media have progressed, the performance of playback devices has been improved.

The conventional technology will be described below with reference to the drawings, taking a digital audio disc as an example.

FIG. 4 is a block diagram showing a part of the digital audio disc playback device. 2o is a disk, 21 is a motor, 22 is a pickup, 23 is an AGC circuit, and 24 is a signal processing circuit.

The input RF signal read by the pickup 22 from the disk 2o being rotated by the motor 21 is converted by the AGC circuit 23 into an ARP signal in which the amplitude of the reproduction signal is standardized in order to obtain stable reproduction characteristics. Thereafter, it is demodulated by the signal processing circuit 24 to become an audio signal.

The amplitude of the input RF signal fluctuates due to reasons such as changes in reflectance caused by manufacturing variations in the disk, and decreases in reflectance due to dirt or scratches attached to the disk. Particularly in the case of a system including a circuit such as a data slicing circuit whose performance is affected by the RF amplitude in the next stage signal processing circuit, fluctuations in the RF amplitude directly affect the performance of the system.

FIG. 3 shows a block diagram of a conventional AGC circuit, in which 1o is a multiplier, 11 is an ARP amplitude extractor, and 12 is an AR
A comparator 13 compares the ARP amplitude extracted by the P amplitude extractor 11 with a reference amplitude, and a filter circuit 13 smoothes the output of the comparator.

The multiplier 1o controls the waveform amplitude of the input RF signal and performs ARP.
Input the signal to the signal processing circuit. The amplitude of the ARP signal, which is the output signal of the multiplier 1o, is extracted by the ARP amplitude extractor 11. AR extracted by ARP amplitude extractor 11
The P amplitude information is compared in magnitude with a predetermined reference amplitude by a comparator 12.

The comparison result output from the comparator 12 is sent to the filter circuit 13.
It is smoothed by The multiplier 1o controls the input RF signal amplitude according to the output signal of the filter circuit 13.

As the multiplier 1o, a current distribution circuit using a differential amplifier circuit or the like is used. Further, as the ARP amplitude extractor 11, an analog peak hold circuit or the like can be used. Further, as the comparator 12, an analog comparator or the like is used. Further, as the filter circuit 13, an analog type integrating circuit using a relatively large capacitor is used.

As described above, the amplitude of the input RF signal is extracted and the amplitude of the input RF signal is controlled to be constant.

゛Problems to be solved by the invention However, as mentioned above, when using an analog type integrating circuit as the filter circuit 13, it is difficult to integrate a relatively large capacitor into an integrated circuit, so it is necessary to prepare a separate external component. There is a need to.

For this reason, there have been problems such as hindering miniaturization of the device, decreasing reliability, increasing the number of structural steps, and increasing costs.

In view of the above-mentioned problems, the present invention provides an AGC circuit that eliminates the need for an external capacitor, thereby realizing miniaturization of the device, high reliability, reduction in manufacturing man-hours, and cost reduction.

Means for Solving the Problems In order to solve the above problems, the AGC circuit of the present invention includes a multiplier that multiplies an input signal by an amplitude control signal expressed as a digital value, and an output of the multiplier. By using a comparator that compares the signal amplitude with a preset comparison value and a digital filter circuit, the filter circuit 13
It has a configuration that realizes this using digital circuits.

Function The present invention, with the above-described configuration, eliminates the need to separately attach a relatively large capacitance capacitor when integrating the circuit, thereby making it possible to downsize the device, improve reliability, and reduce manufacturing man-hours and costs. This realizes an AGC circuit that looks like this.

Embodiment An AGC circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an ACiC circuit in one embodiment of the present invention. 1 is a multiplier that multiplies an input signal and an amplitude control signal; 2 is a comparator that compares the output signal amplitude of the multiplier with a preset comparison value; 3
is an up-down counter.

The input RF signal is connected to the signal input of multiplier 1.

A count value of an up/down counter 3 is connected to a control signal input of the multiplier 1. The amplitude of the input RF signal is controlled by the multiplier 1 in accordance with the control signal input, and becomes an ARP signal.

The ARP signal is compared by a comparator 2 to determine whether its amplitude is larger or smaller than a reference amplitude.

When the ARP amplitude is larger than the reference amplitude, a down pulse is output to the up/down counter 3, and when the ARP amplitude is smaller than the reference amplitude, an up pulse is output to the up/down counter 3. The count value of the up/down counter 30 changes depending on the comparison result of the comparator 2.

If the ARP amplitude is larger than the reference amplitude, comparator 2
outputs a down pulse, so the counter value of the up/down counter 3 decreases. Multiplier 1 reduces the amplitude of the input RF signal according to the count value. Also ARP
Since the comparator 2 outputs an up pulse when the amplitude is smaller than the reference amplitude, the counter f value of the up/down counter 3 increases. Multiplier 1 increases the amplitude of the input RF signal according to the count value. As mentioned above, the ARP amplitude, which is the output signal of multiplier 1, is controlled to always have a constant amplitude by operating the AGC circuit composed of multiplier 1, comparator 2, and up/down counter 3. be done.

Note that the multiplier can be easily realized by using a combination of a conventionally used analog multiplier that handles analog signals and a D/A converter.

As described above, according to this embodiment, there is a multiplier 1 that multiplies an input signal and an amplitude control signal, and a comparator 2 that compares the output signal amplitude of the multiplier with a preset comparison value.
By providing the and up/down counter 3,
It is possible to realize an AGC circuit that eliminates the need to separately attach a relatively large-capacity capacitor, thereby making it possible to reduce the size of the device, increase reliability, and reduce manufacturing man-hours and costs.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of a digital filter circuit in a second embodiment of the invention.

In FIG. 2, 1 is a multiplier, 2 is a comparator, 4 is a reference clock generation circuit, 6 is a latch circuit, 6 is a coefficient unit, and 7 is an adder circuit. Multiplier 1 and comparator 2 have the same structure as that shown in FIG.

The operation of the AGC circuit configured as described above will be explained below. □ The input RF signal is connected to the signal input of multiplier 1.

A count value of an up/down counter 3 is connected to a control signal input of the multiplier 1. The amplitude of the input RF signal is controlled by the multiplier 1 in accordance with the control signal input, and becomes an ARP signal.

The ARP signal is compared by a comparator 2 to determine whether its amplitude is larger or smaller than a reference amplitude. 'If the ARF amplitude is larger than the reference amplitude, a value of -1 is added, and if the ARP amplitude is smaller than the reference amplitude, a value of +1 is added to the addition circuit 7.
is output to. The output value of the adder circuit 7 changes depending on the comparison result of the comparator 2.

Since the comparator 2 outputs -1 when the ARP amplitude is larger than the reference amplitude, the output value of the adder circuit 7 decreases. Multiplier 1 reduces the amplitude of the input RF signal according to the output value of addition circuit 7. Further, if the ARP amplitude is smaller than the reference amplitude, +1 is output, so the output value of the adder circuit 7 increases. The multiplier 1 increases the amplitude of the input RF signal according to the output value of the adder circuit 7. Since the operation of the digital filter constituted by the reference clock generation circuit 4, latch circuit 5, coefficient unit 6, and addition circuit 7 is well known, the explanation thereof will be omitted here.

As described above, the AGC circuit composed of the multiplier 1, the comparator 2, the reference cross-circuit generation circuit 4, the circuit 5, the coefficient multiplier 6, and the adder circuit 7 operates. The ARP signal, which is the output signal of the multiplier 1, is controlled to always have a constant amplitude.

As described above, according to this embodiment, there is a multiplier 1 that multiplies an input signal and an amplitude control signal, and a comparator 2 that compares the output signal amplitude of the multiplier with a preset comparison value.
By providing a reference clock generation circuit 4, a latch circuit 6, a coefficient unit 6, and an adder circuit 7, the need for a separate external capacitor of relatively large capacity is eliminated, making the device more compact and highly reliable. In addition to making it possible to reduce performance, manufacturing man-hours, and costs, it is also possible to realize an AGC circuit with more complicated loop gain characteristics than in the first embodiment.

Effects of the Invention As described above, the present invention includes a multiplier that multiplies an input signal by an amplitude control signal expressed as a digital value, and a comparison value that is set in advance and the output signal amplitude of the multiplier. By providing a digital filter circuit consisting of a comparator that compares the values of A method that can achieve the effect of reducing productivity, manufacturing man-hours, and costs.
This can be realized by a GC circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an AGC circuit according to a first embodiment of the present invention, and FIG. 2 is a block diagram of an AGC circuit according to a second embodiment of the present invention.
FIG. 3 is a block diagram of a conventional AGC circuit, and FIG. 4 is a block diagram showing a part of a digital audio disc playback device. 1... Multiplier, 2... Comparator, 3...
...Up/down counter, 4...Reference clock generation circuit, 6...Latch circuit, 6...
... Coefficient unit, 7... Addition circuit, 10...
... Multiplier, 11 ... ARFi width extractor, 12
...Comparator, 13...Filter circuit,
2Q...disc, 21...motor,
22...Pickup, 23...AG
C circuit, 24...signal processing circuit.

Claims (5)

[Claims] (1) A multiplier that multiplies an input signal by an amplitude control signal expressed as a digital value, a comparator that compares the output signal amplitude of the multiplier with a preset reference value, and a digital A characterized by being equipped with a filter circuit.
GC circuit. (2) The AG according to claim 1, wherein the digital filter circuit is an up/down counter.
C circuit. (3) The AGC circuit according to claim 1, wherein the digital filter circuit includes a reference clock generation circuit, a latch circuit, a coefficient multiplier, and an addition circuit. (4) The multiplier is an analog/digital multiplier that digitally controls the amplitude of the input signal expressed as an analog quantity, and the comparator is an analog comparator that compares the multiplier output expressed as an analog quantity with a comparison value. The AGC circuit according to claim 1, characterized in that: (5) The multiplier is a digital-digital multiplier that controls the amplitude of the input signal expressed as a digital quantity using a digital value, and the comparator is a digital-digital multiplier that controls the amplitude of the input signal expressed as a digital quantity with a comparison value. The AGC circuit according to claim 1, wherein the AGC circuit is a comparator.