JPS6327130A - Local oscillation circuit for tuner - Google Patents

Local oscillation circuit for tuner

Info

Publication number
JPS6327130A
JPS6327130A JP17057586A JP17057586A JPS6327130A JP S6327130 A JPS6327130 A JP S6327130A JP 17057586 A JP17057586 A JP 17057586A JP 17057586 A JP17057586 A JP 17057586A JP S6327130 A JPS6327130 A JP S6327130A
Authority
JP
Japan
Prior art keywords
frequency
signal
local oscillation
circuit
vco
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17057586A
Other languages
Japanese (ja)
Inventor
Kazuya Kawabata
一也 川端
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP17057586A priority Critical patent/JPS6327130A/en
Publication of JPS6327130A publication Critical patent/JPS6327130A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To remarkably reduce cost by providing a VCO, a PLL circuit controlling it and a frequency multiplier multiplying the oscillated frequency from the VCO so as to eliminate the need for an expensive frequency divider. CONSTITUTION:The titled circuit is constituted by providing the VCO 26, a frequency divider 30 frequency-dividing its oscillated signal OS, a programmable divider 32, the PLL circuit 24 controlling the VCO 26 while using the signal subjected to frequency-division and the frequency muitiplier 28 multiplying the frequency of the signal OS and giving an output of the local oscillation signal. Thus, in giving an output of a 1st local oscillation signal LO1 having a frequency of 2.05-2.85GHz from the multiplier 28 having a multiplication number, e.g. 2, the frequency of the signal OS from the VCO 26 is 1.025-1.425GHz. Then part of the signal OS is inputted to the circuit 24 for the control purpose. Thus, a general-purpose frequency synthesizer IC or the like is used for the circuit 24. Then no expensive frequency divider for the high frequency operation is required.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、例えばダブルス−パ一方式のテレビチュー
ナの第1局部発振回路等に用いられるチューナ用局部発
振回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a local oscillation circuit for a tuner, which is used, for example, as a first local oscillation circuit of a double-super one-type television tuner.

〔従来の技術〕[Conventional technology]

第2図は、ダブルス−パ一方式のテレビチューナの一例
を示すブロック図である。アンテナ等から人力されたテ
レビ放送の高周波信号RFを高周波増幅器2で増幅して
第1混合器6に供給し、そこにおいて第1局部発振回路
4からの第2局部発振信号Lo+に基づいて周波数変換
することによって第1中間周波信号IFIを得る。そし
て当該第1中間周波信号T F Iを第1中間周波数増
幅器兼フィルタ8を経由して第2混合器12に供給し、
そこにおいて第2局部発振回路10からの第1局部発振
信号LO,に基づいて再び周波数変換することによって
第2中間周波信号IF2を得て、これを第2中間周波増
幅器14を経由して次段へ供給するようにしている。
FIG. 2 is a block diagram showing an example of a double super one type television tuner. The high frequency signal RF of the television broadcast manually input from an antenna etc. is amplified by the high frequency amplifier 2 and supplied to the first mixer 6, where the frequency is converted based on the second local oscillation signal Lo+ from the first local oscillation circuit 4. By doing so, the first intermediate frequency signal IFI is obtained. Then, the first intermediate frequency signal T F I is supplied to the second mixer 12 via the first intermediate frequency amplifier/filter 8,
There, the frequency is again converted based on the first local oscillation signal LO from the second local oscillation circuit 10 to obtain a second intermediate frequency signal IF2, which is then passed through the second intermediate frequency amplifier 14 to the next stage. We are trying to supply it to

このようなテレビチューナにおいては、例えばオールバ
ンドチューナのような広範囲(例えば50〜850MH
z)の高周波信号RFを一括して、しかも歪み、イメー
ジ妨害等をできるだけ少なくして処理するため、第1中
間周波信号IF、の周波数は例えば2GH2帯辺りが選
ばれる。
In such a TV tuner, for example, an all-band tuner has a wide range (for example, 50 to 850 MHz).
In order to process the high frequency signal RF of z) all at once and with as little distortion, image disturbance, etc. as possible, the frequency of the first intermediate frequency signal IF is selected to be around the 2GH2 band, for example.

そして2GHz帯に第1中間周波信号IF+を持ってく
る場合、従来の周波数シンセサイザ方式の第1局部発振
回路4は、図示のように、電圧制御発振器(VCO)で
2GHz帯の第1局部発振信号LO,を発振させると共
に、その一部を分周器(プリスケーラ−)20で基準信
号と比較できる周波数まで分周してPLL回路18に帰
還信号として供給するよう構成している。この場合、受
信する高周波信号RFの帯域を前述のような50〜85
0MHzとし、第1中間周波信号IF、を2GHzとす
ると、電圧制御発振器16は2.05〜2.85GHz
牢での可変幅が必要となる。
When the first intermediate frequency signal IF+ is brought to the 2 GHz band, the first local oscillation circuit 4 of the conventional frequency synthesizer type generates the first local oscillation signal of the 2 GHz band using a voltage controlled oscillator (VCO) as shown in the figure. LO, is oscillated, and a part of it is divided by a frequency divider (prescaler) 20 to a frequency that can be compared with a reference signal and is supplied to the PLL circuit 18 as a feedback signal. In this case, the band of the high frequency signal RF to be received is set to 50 to 85 as described above.
0 MHz, and the first intermediate frequency signal IF is 2 GHz, the voltage controlled oscillator 16 has a frequency of 2.05 to 2.85 GHz.
A variable width in the cell is required.

今、位相比較用の基準信号を数KHzとし、汎用の周波
数シンセサイザ用IC(数百MH2の入力に対する分周
器とPLL回路とプログラマブルディバイダを含む)を
使用する場合には、上記2゜05〜2.85GHzの信
号LO,を数百MHzに落とすための分周器がもう一つ
必要である。
Now, if the reference signal for phase comparison is several KHz and a general-purpose frequency synthesizer IC (including a frequency divider, PLL circuit, and programmable divider for several hundred MH2 input) is used, the above 2°05~ Another frequency divider is required to reduce the 2.85 GHz signal LO to several hundred MHz.

尚、プログラマプルディバイダ21は、例えば、マイク
ロコンピュータ22からデータをシフトする基準信号C
K、チャンネル選択用の周波数設定信号DAおよびシフ
トレジスタにより直列から並列に変換されたデータを数
bitのデータ・ラッチに転送するための信号LDが供
給され、そして当該PLL回路18はこれらに基づいて
電圧制1III発振器16に制御用のチューニング電圧
■を供給するためのものである。
Note that the programmable divider 21 receives, for example, a reference signal C for shifting data from the microcomputer 22.
K, a frequency setting signal DA for channel selection and a signal LD for transferring data converted from serial to parallel by a shift register to a several-bit data latch are supplied, and the PLL circuit 18 operates based on these signals. This is for supplying the voltage controlled IIII oscillator 16 with a tuning voltage (2) for control.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の第1局部発振回路4においては、電
圧制御発振器16の周波数が例えば2゜05〜2.85
GHzというように高く、しかも可変幅が広いため、当
該発振器16の製作が難しく、しかも十分なC/Nが取
りにくい等といった問題がある。
In the conventional first local oscillation circuit 4 as described above, the frequency of the voltage controlled oscillator 16 is, for example, 2°05 to 2.85.
Since the frequency is as high as GHz and has a wide variable range, it is difficult to manufacture the oscillator 16, and it is difficult to obtain a sufficient C/N.

また2GHz〜3GHz帯という高、周波帯で動作する
高価な分周器20が必要であるという問題もある。
Another problem is that an expensive frequency divider 20 that operates in a high frequency band of 2 GHz to 3 GHz is required.

そこでこの発明は、例えば上記のような第1局部発振回
路に使用することができ、しかも従来のような問題のな
いチューナ用局部発振回路を提供することを目的とする
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a local oscillation circuit for a tuner that can be used, for example, in the first local oscillation circuit as described above, and does not have the problems of the conventional ones.

C問題点を解決するための手段〕 この発明のチューナ用局部発振回路は、電圧制御発振器
と、電圧制御発振器からの発振信号を用いて当該電圧制
御発振器を制御するPLL回路と、電圧制御発振器から
の発振信号の周波数を逓倍して局部発振信号として出力
する周波数逓倍器とを備えることを特徴とする。
Means for Solving Problem C] The tuner local oscillation circuit of the present invention includes a voltage controlled oscillator, a PLL circuit that controls the voltage controlled oscillator using an oscillation signal from the voltage controlled oscillator, and a A frequency multiplier that multiplies the frequency of the oscillation signal and outputs it as a local oscillation signal.

〔作用〕[Effect]

電圧制御発振器からの発振信号が周波数逓倍器で逓倍さ
れて所定周波数の局部発振信号が作られる。PLL回路
には、電圧制御発振器からの逓倍前の発振信号が帰還さ
れて制御に供される。従って、高周波で動作する分周器
が不要となり、しかも電圧制御発振器の発振周波数が低
く、かつその絶対的な可変幅が狭くて済むようになる。
The oscillation signal from the voltage controlled oscillator is multiplied by a frequency multiplier to create a local oscillation signal of a predetermined frequency. The oscillation signal before multiplication from the voltage controlled oscillator is fed back to the PLL circuit and used for control. Therefore, there is no need for a frequency divider that operates at a high frequency, and moreover, the oscillation frequency of the voltage controlled oscillator is low and its absolute variable range is narrow.

〔実施例〕〔Example〕

第1図は、この発明の一実施例に係る局部発振回路を示
すブロック図である。この局部発振回路40は、電圧制
御発振器(VCO)26と、電圧制御発振器26からの
発振信号OSを分周するための分周器30およびプログ
ラマブルディバイダ32と、そして分周された信号を用
いて電圧制御発振器26を制御するPLL回路24と、
電圧制御発振器26からの発振信号O8の周波数を逓倍
して局部発振信号として出力する周波数逓倍器28とを
備える。なお、プログラマプルディハイダ32は、上記
第2図の場合と同様に、マイクロコンピュータ34で制
御されている。また、■は上記の場合と同様に電圧制御
発振器26制御用のチューニング電圧である。
FIG. 1 is a block diagram showing a local oscillation circuit according to an embodiment of the present invention. This local oscillation circuit 40 includes a voltage controlled oscillator (VCO) 26, a frequency divider 30 and a programmable divider 32 for dividing the frequency of the oscillation signal OS from the voltage controlled oscillator 26, and a frequency-divided signal. a PLL circuit 24 that controls the voltage controlled oscillator 26;
It includes a frequency multiplier 28 that multiplies the frequency of the oscillation signal O8 from the voltage controlled oscillator 26 and outputs it as a local oscillation signal. Note that the programmable delayer 32 is controlled by a microcomputer 34 as in the case of FIG. 2 above. Further, (2) is a tuning voltage for controlling the voltage controlled oscillator 26 as in the above case.

上記局部発振回路40のより具体例を、例えば第2図に
示したようなチューナの第1局部発振回路4の代わりに
用いる場合を例に説明する。周波数逓倍器28は例えば
ダイオードダブラ−で構成することができ、この周波数
逓倍器28から例えば前述したような2.05〜2.8
5GHzの第1局部発振信号LO,を出力させる場合、
電圧制御発振器26からの発振信号OSの周波数は1゜
025〜1.425GHzで良くなる。
A more specific example of the local oscillation circuit 40 will be described using a case where it is used instead of the first local oscillation circuit 4 of a tuner as shown in FIG. 2, for example. The frequency multiplier 28 can be composed of, for example, a diode doubler, and from this frequency multiplier 28, for example, 2.05 to 2.8 as described above
When outputting the first local oscillation signal LO of 5 GHz,
The frequency of the oscillation signal OS from the voltage controlled oscillator 26 is preferably 1°025 to 1.425 GHz.

そしてPLL回路24には、基本波である(即ち逓倍前
の)上記発振信号OSの一部が入力され制御に供される
。従って、PLL回路24としては、上記PLL回路1
8の場合と同様に、汎用の周波数シンセサイザ用IC等
(プログラマブルディハイダとPLL回路内蔵)を使用
することができる。
A part of the oscillation signal OS, which is a fundamental wave (that is, before multiplication), is input to the PLL circuit 24 and used for control. Therefore, as the PLL circuit 24, the PLL circuit 1
As in the case of No. 8, a general-purpose frequency synthesizer IC or the like (with a built-in programmable delayer and PLL circuit) can be used.

従って上記のような局部発振回路40によれば、従来の
ような高周波で動作する高価な分周器20が不要となる
ため、大幅なコスト低減が可能となる。これは、周波数
逓倍器28の方が分周器20よりも遥かに簡単にかつ安
価に製作できるからである。
Therefore, according to the above-described local oscillation circuit 40, the expensive frequency divider 20 that operates at a high frequency as in the conventional circuit is not required, so that a significant cost reduction is possible. This is because frequency multiplier 28 is much easier and cheaper to manufacture than frequency divider 20.

しかも、電圧制御発振器26の発振周波数が低く、かつ
そのその可変幅が狭くて済むようになるので、当該電圧
制御発振器26の設計・製作が容易になると共に、その
出力レベルも全帯域に亘って十分に取れるようになり、
またC/Nも良くなることが期待できる。
Moreover, since the oscillation frequency of the voltage controlled oscillator 26 is low and its variable range is narrow, it becomes easy to design and manufacture the voltage controlled oscillator 26, and its output level can also be maintained over the entire band. Now you can get enough
Furthermore, it can be expected that the C/N will also improve.

尚、周波数逓倍器28における逓倍数は、必ずしも上記
2倍に限定されるものではなく、所望とする局部発振信
号の周波数や利用する電圧制御発振器26、PLL回路
24等に応じて種々のものを選定することができる。
Note that the multiplication number in the frequency multiplier 28 is not necessarily limited to the above-mentioned double, and various values may be used depending on the frequency of the desired local oscillation signal, the voltage controlled oscillator 26, the PLL circuit 24, etc. to be used. can be selected.

また1、上記では局部発振回路4oをダブルス−パ一方
式のテレビチューナの第1局部発振回路に使用する例を
説明したけれども、当該局部発振回路40はそれ以外の
局部発振回路にも使用することができるのは勿論である
In addition, 1. Although the example in which the local oscillation circuit 4o is used as the first local oscillation circuit of a double super one-way TV tuner has been described above, the local oscillation circuit 40 can also be used for other local oscillation circuits. Of course, it is possible to do so.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、高価な高周波用の分周
器が不要となるためコスト低減が可能となる。また電圧
制御発振器の発振周波数が低く、かつその可変幅が狭く
て済むようになるので、当該発振器の設計・製作等が容
易になると共に、C/Nも良くなることが期待できる。
As described above, according to the present invention, an expensive frequency divider for high frequencies is not required, so that costs can be reduced. Furthermore, since the oscillation frequency of the voltage controlled oscillator is low and its variable range is narrow, it is expected that the design and manufacture of the oscillator will become easier and the C/N will be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明の一実施例に係る局部発振回路を示
すブロック図である。第2図は、ダブルス−パ一方式の
テレビチューナの一例を示すブロック図である。 4・・・第1局部発振回路、16.26・・・電圧制御
発振器、18.24・・・PLL回路、20.・・分周
器、28・・・周波数逓倍器、40・・・実施例に係る
局部発振回路、IF、・・・第1中間周波信号、LO,
、・、第1局部発振信号。
FIG. 1 is a block diagram showing a local oscillation circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing an example of a double super one type television tuner. 4... First local oscillation circuit, 16.26... Voltage controlled oscillator, 18.24... PLL circuit, 20. ... Frequency divider, 28 ... Frequency multiplier, 40 ... Local oscillation circuit according to the embodiment, IF, ... First intermediate frequency signal, LO,
, ., first local oscillation signal.

Claims (1)

【特許請求の範囲】[Claims] (1)電圧制御発振器と、電圧制御発振器からの発振信
号を用いて当該電圧制御発振器を制御するPLL回路と
、電圧制御発振器からの発振信号の周波数を逓倍して局
部発振信号として出力する周波数逓倍器とを備えること
を特徴とするチューナ用局部発振回路。
(1) A voltage controlled oscillator, a PLL circuit that controls the voltage controlled oscillator using an oscillation signal from the voltage controlled oscillator, and a frequency multiplier that multiplies the frequency of the oscillation signal from the voltage controlled oscillator and outputs it as a local oscillation signal. A local oscillation circuit for a tuner, characterized by comprising:
JP17057586A 1986-07-19 1986-07-19 Local oscillation circuit for tuner Pending JPS6327130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17057586A JPS6327130A (en) 1986-07-19 1986-07-19 Local oscillation circuit for tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17057586A JPS6327130A (en) 1986-07-19 1986-07-19 Local oscillation circuit for tuner

Publications (1)

Publication Number Publication Date
JPS6327130A true JPS6327130A (en) 1988-02-04

Family

ID=15907378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17057586A Pending JPS6327130A (en) 1986-07-19 1986-07-19 Local oscillation circuit for tuner

Country Status (1)

Country Link
JP (1) JPS6327130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854872A (en) * 1996-10-08 1998-12-29 Clio Technologies, Inc. Divergent angle rotator system and method for collimating light beams

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854872A (en) * 1996-10-08 1998-12-29 Clio Technologies, Inc. Divergent angle rotator system and method for collimating light beams

Similar Documents

Publication Publication Date Title
US5973570A (en) Band centering frequency multiplier
US4451930A (en) Phase-locked receiver with derived reference frequency
JP2710528B2 (en) Low noise fine frequency step synthesizer
JPH11501471A (en) Wide frequency range television tuner with single local oscillator
JPS60134633A (en) Controller for double conversion tuner
US5712602A (en) Phase-locked oscillator for microwave/millimeter-wave ranges
US7551906B2 (en) AM/FM radio receiver and local oscillator circuit used therein
JP2001144545A (en) Frequency synthesizer
JPH0715371A (en) Superheterodyne system transmission/reception method and transmitter/receiver
JPH02188027A (en) Frequency synthesizer
US4249138A (en) Citizens band transceiver frequency synthesizer with single offset and reference oscillator
US6385266B1 (en) Sampling PLL for high resolution radar systems
US6493410B1 (en) Wide band high resolution synthesizer
JPS6327130A (en) Local oscillation circuit for tuner
JPS6221418B2 (en)
JP3053838B2 (en) Video intermediate frequency circuit
KR920009010B1 (en) Syncronizing circuit and method for composing frequency in television tuner
JPS6338329A (en) Microwave synthesizer
JP2000299646A (en) Double conversion tuner
JPH06224957A (en) Radio transmitter
JP2563256B2 (en) Microwave frequency synthesizer
US20040027205A1 (en) Local oscillator apparatus for low-noise generation of arbitrary frequencies
JPH05284023A (en) Frequency synthesizer
JPH07235893A (en) Formation of intermediate frequency signal for wireless telephone and its device
JPS6028330A (en) Double superheterodyne tuner