JPS6028330A - Double superheterodyne tuner - Google Patents

Double superheterodyne tuner

Info

Publication number
JPS6028330A
JPS6028330A JP13584383A JP13584383A JPS6028330A JP S6028330 A JPS6028330 A JP S6028330A JP 13584383 A JP13584383 A JP 13584383A JP 13584383 A JP13584383 A JP 13584383A JP S6028330 A JPS6028330 A JP S6028330A
Authority
JP
Japan
Prior art keywords
frequency
signal
circuit
local
local oscillation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13584383A
Other languages
Japanese (ja)
Inventor
Takeshi Saito
武志 斎藤
Toshio Nagashima
敏夫 長嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13584383A priority Critical patent/JPS6028330A/en
Publication of JPS6028330A publication Critical patent/JPS6028330A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16Multiple-frequency-changing

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To obtain the 2nd IF output signal which is highly stable by detecting the difference of a fundamental oscillating frequency of the 2nd local oscillating circuit and an oscillating frequency of the 1st local oscillating circuit to control the 1st local oscillating frequency by a PLL circuit. CONSTITUTION:A multiplier 9 doubles a frequency of an oscillator 10. In receiving a CATV signal of 50-450MHz, when the 1st IF signal frequency is 600MHz, the 1st local oscillating frequency is 650-1,050MHz and when the 2nd IF signal frequency is 62MHz, the oscillating frequency of the local oscillator 10 is 331MHz. The difference between the 1st local oscillating frequency and the oscillating frequency of the oscillator 10 is 319-719MHz by a mixer 11, which attains the frequency division by a fixed frequency divider 12 and the control of the oscillating frequency of the 1st local oscillating circuit 3 via the PLL circuit 13.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、テレビ信号を受信するチェーナに係υ、特に
cAry儂号全受信するのに好適なダブルス−パーヘテ
ロダインチューナに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a tuner for receiving television signals, and particularly to a double superheterodyne tuner suitable for receiving all cAry signals.

〔発明の背景〕[Background of the invention]

CATV信号を受信し、空きチャネルのRF倍信号変換
するダブルス−パーヘテロダイン方式のチューナについ
て、第1図を用いて説明する。
A double superheterodyne tuner that receives a CATV signal and converts it into an RF signal of an idle channel will be described with reference to FIG.

第1図は一般的なダブルスーパーヘテロダインチ瓢−す
全説明するためのブロック図である。
FIG. 1 is a block diagram for explaining the entire structure of a general double superheterodyne inch.

第1図において、1はRF倍信号入力端子、2は第1混
合器、3け第1局部発振回路、4はバンドパスフィルタ
、5は第11F信号増幅器、6は第2混合器、7は第2
局部発振回路、8は第2IF信号出力端子である。
In FIG. 1, 1 is an RF multiplied signal input terminal, 2 is a first mixer, 3-digit first local oscillation circuit, 4 is a band pass filter, 5 is an 11F signal amplifier, 6 is a second mixer, and 7 is a Second
In the local oscillation circuit, 8 is a second IF signal output terminal.

RF信号入力端子1に入力されたRF倍信号第1局部発
振回路3によシ第1混合器2で第11F信号に変換され
、バンドパスフィルタ4およU1g1 IF信号増幅器
5で選択増幅された後、第2局部発振回路7の発振信号
により第2混合器6で第21F信号に変換され、出力端
子8よシ出力される。
The RF multiplied signal input to the RF signal input terminal 1 is converted into an 11F signal by the first mixer 2 by the first local oscillation circuit 3, and selectively amplified by the bandpass filter 4 and U1g1 IF signal amplifier 5. Thereafter, the signal is converted into a 21F signal by the second mixer 6 using the oscillation signal of the second local oscillation circuit 7, and is outputted from the output terminal 8.

希望するRF信号の選択は第1局部発振回路6の発振周
波数を選択することで行なわれ、第11F信号周波数は
通常、受信するRF信号周波数よりも高す周波数に設定
される。第2IF信号周波数は通常、米国のCATV受
信においては、2チヤネルある込は3チヤネルに設定さ
れる。
The desired RF signal is selected by selecting the oscillation frequency of the first local oscillation circuit 6, and the 11th F signal frequency is normally set to a higher frequency than the RF signal frequency to be received. The second IF signal frequency is normally set to 3 channels (including 2 channels) in CATV reception in the United States.

ダブルスーパーペテロダイン方式のチューナでは、安定
した第21F信号を得るためには第1局部発振回路3の
発振周波数、第2局部発掘回路7の発振周波数およびバ
ンドパスフィルタ4の通過帯域中心周波数がそれぞれ安
定であるか、さもなくばそれぞれ同等に変動することが
必要である。
In a double superpeterodyne tuner, in order to obtain a stable 21st F signal, the oscillation frequency of the first local oscillation circuit 3, the oscillation frequency of the second local excavation circuit 7, and the passband center frequency of the bandpass filter 4 must be set respectively. They need to be stable or otherwise vary equally.

そこで、安定した第21F信号を得るために、第1局部
発振回路6をPLL回路等によシ正確に制御した場合、
バンドパスフィルタ4及び第2局部発振回路7の周波数
も高安定にしなければならない。例えば、第1局部発振
周波数が最高10H,程度であれば第2局部発振回路7
およびバンドパスフィルタ4の安定化を図ることで、第
1局部発振周波数を直接検知しPLL回路で制御するこ
とが可能である。
Therefore, in order to obtain a stable 21st F signal, if the first local oscillation circuit 6 is accurately controlled by a PLL circuit or the like,
The frequencies of the bandpass filter 4 and the second local oscillation circuit 7 must also be made highly stable. For example, if the first local oscillation frequency is about 10H at maximum, the second local oscillation circuit 7
By stabilizing the bandpass filter 4, the first local oscillation frequency can be directly detected and controlled by the PLL circuit.

ところがこの場合、例えば第1 IF信号周波数が2〜
5(Jzと高くなってくると、第1局部発振周波数も高
くなるため、直接分周することが困難となり、PLL制
御ができなくなってしまうという欠点があった。
However, in this case, for example, the first IF signal frequency is 2~
5 (Jz), the first local oscillation frequency also becomes high, which makes direct frequency division difficult and has the disadvantage that PLL control becomes impossible.

また、第1局部発振回路3と第2局部発振回路7の差の
周波数によりPLL回路で第1局部発振周波数を制御し
た場合はバンドパスフィルタ4と第2局部発振回路7の
周波数安定度を同程度にする必要があり、さらに、第1
局部発振回路3と第2局部発掘回路7の差の周波数がゼ
ロとなること、および第21F信号周波数を3チヤネル
に設定すると2チヤネルと4チヤネルの区別ができない
等の問題があり、PLL制御が困難となってしまうとい
う欠点があった。
In addition, when the first local oscillation frequency is controlled by the PLL circuit using the difference frequency between the first local oscillation circuit 3 and the second local oscillation circuit 7, the frequency stability of the bandpass filter 4 and the second local oscillation circuit 7 is the same. In addition, the first
There are problems such as the frequency difference between the local oscillator circuit 3 and the second local excavation circuit 7 being zero, and if the 21st F signal frequency is set to 3 channels, it is not possible to distinguish between 2 channels and 4 channels. The drawback was that it was difficult.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した従来技術の欠点を除去し、第
1局部発振周波数f PLL回路で安定して制御でき、
高安定な第21F信号出力を得ることができるダブルス
ーパーヘテロダインチェーナを提供することにある。
The object of the present invention is to eliminate the drawbacks of the above-mentioned conventional technology, to enable stable control of the first local oscillation frequency f by a PLL circuit, and to
An object of the present invention is to provide a double superheterodyne chainer capable of obtaining a highly stable 21st F signal output.

〔発明の概要〕[Summary of the invention]

上記の目的は、本発明によれば、第2局部発振回路を発
振器とその発振周波数を逓倍して発振出力とする逓倍器
で構成すると共に、該発振器の基本発振周波数と第1局
部発振回路の発振周波数との周波数差を検出してPLL
回路により第1局部発振周波数を制御することによって
達成される。
According to the present invention, the above object is to configure the second local oscillation circuit with an oscillator and a multiplier that multiplies the oscillation frequency to produce an oscillation output, and to combine the basic oscillation frequency of the oscillator with the first local oscillation circuit. PLL by detecting the frequency difference with the oscillation frequency
This is achieved by controlling the first local oscillation frequency by a circuit.

〔発明の実施例〕[Embodiments of the invention]

第2図は本発明の一実施例を示すブロック図である。 FIG. 2 is a block diagram showing one embodiment of the present invention.

第2図において、第1図と同一の作用の要素については
同一番号を付L1説明は省略する。
In FIG. 2, elements having the same functions as those in FIG. 1 are designated by the same numbers, and explanation thereof will be omitted.

また、同図において、9は逓倍器、10は発振器、11
は第3の混合器、12は固定分局器、16はPLL回路
である。
Also, in the same figure, 9 is a multiplier, 10 is an oscillator, and 11 is a multiplier.
1 is a third mixer, 12 is a fixed divider, and 16 is a PLL circuit.

第2図では、逓倍器9としては発振器10の発振周波数
全2逓倍する逓倍器を用いた。
In FIG. 2, a multiplier that doubles the oscillation frequency of the oscillator 10 is used as the multiplier 9.

50〜450 )dHzのCATV信号全受信する場合
、第11F信号周波数f 600 MHzとすると、第
1局部発振周波数は650〜105105Oとなり、第
21F信号周波数f 62 MHzとすると局部発振器
10の発振周波数は331MH2となる。そこで第5の
混合器11によシ、第1局部発振周波数と発振器10の
発振周波数の差をめると、319〜719MH2となり
、固定分局器12による分局が可能でPLL回路13を
介して第1局部発振回路3の発振周波数の制御が可能と
なる。
When receiving all CATV signals of 50 to 450 dHz, if the 11th F signal frequency f is 600 MHz, the first local oscillation frequency is 650 to 105105 O, and if the 21st F signal frequency is f 62 MHz, the oscillation frequency of the local oscillator 10 is It becomes 331MH2. Therefore, if we calculate the difference between the first local oscillation frequency and the oscillation frequency of the oscillator 10 in the fifth mixer 11, we get 319 to 719 MH2. The oscillation frequency of the first local oscillation circuit 3 can be controlled.

本発明の他の実施例を第3図により説明する。Another embodiment of the present invention will be described with reference to FIG.

第3図は本発明の他の実施例を示すブロック図である。FIG. 3 is a block diagram showing another embodiment of the present invention.

第3図において、第2図と同一作用の要素については同
一番号を付し、説明は省略する。同図において、14は
分波器である。
In FIG. 3, elements having the same functions as those in FIG. 2 are given the same numbers, and explanations thereof will be omitted. In the figure, 14 is a duplexer.

第6図に示したダブルス−パーヘテロダイン方式のチー
−すでは第1局部発振回路6の発振信号が第1混合器2
、バンドパスフィルタ4、第i IF増幅器5を介して
第2混合器6に入力され、この第2局部発振信号と発振
器10の信号との周波数差の信号を分波器14により第
2 rp倍信号区別して取り出し、該信号の信号レベル
が低い場合には増幅する等して固定分局器12で分周し
、PLL回路13ヲ介して第1局部発振回路3の発振周
波数を制御する。
In the double superheterodyne system shown in FIG.
, the bandpass filter 4 and the i-th IF amplifier 5 are input to the second mixer 6, and the signal having the frequency difference between the second local oscillation signal and the signal from the oscillator 10 is multiplied by a second rp by the splitter 14. The signals are differentiated and extracted, and if the signal level of the signal is low, it is amplified or frequency-divided by a fixed divider 12, and the oscillation frequency of the first local oscillation circuit 3 is controlled via a PLL circuit 13.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、テレビ信号fRF信号に変換するダブ
ルス−パーヘテロダイン方式のCATV受信チューナに
おいて、特に、第11F信号周波数を高く取シ第1局部
発振周波数の直接分周が困難な場合でも、第1局部発振
周波数’(i−PLL回路で安定して制御できるので、
高安定外第21F信号出力を得ることができる。
According to the present invention, in a double superheterodyne CATV reception tuner that converts a television signal into an fRF signal, the 11th F signal frequency can be raised to a high frequency, and even when it is difficult to directly divide the first local oscillation frequency. 1 local oscillation frequency' (can be stably controlled by the i-PLL circuit,
A highly stable external 21st F signal output can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一般的なダブルス−パーヘテロダイン方式のチ
ューナを説明するためのブロック図、第2図、第3図は
それぞれ本発明の実施例を示すブロック図である。 1・・・RF信号入力端子 2・・・第1混合器3・・
・第1局部発振回路 4・・・バンドパスフィルタ5・
・・第j IF信号増幅器 6・・・第2混合器7′・
・・第2局部発振回路 8・・・第21F信号出力端子
9・・・逓倍器 10・・・発振器 11・・・第6混合器 12・・・固定分周器13・・
・PLL回路 14・・・分波密事2図 第 3 図
FIG. 1 is a block diagram for explaining a general double superheterodyne tuner, and FIGS. 2 and 3 are block diagrams showing embodiments of the present invention. 1... RF signal input terminal 2... First mixer 3...
・First local oscillation circuit 4...Band pass filter 5・
・Jth IF signal amplifier 6 ・Second mixer 7'・
... Second local oscillation circuit 8 ... 21st F signal output terminal 9 ... Multiplier 10 ... Oscillator 11 ... Sixth mixer 12 ... Fixed frequency divider 13 ...
・PLL circuit 14...Branch secrets Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1) RF入力信号を第1の局部発振回路からの発振出
力によシ周波数変換して出力する第1の混合器と、該第
1の混合器からの出力を第2の局部発振回路からの発振
出力によシ周波数変換して出力する第2の混合器とを含
んで成るfプルスーパーヘテロダインチューナにおいて
、前記第2の局部発振回路を発振器とその発振周波数を
逓倍して発振出力とする逓倍器で構成すると共に、該発
振器の基本発振周波数と前記第1の局部発振回路の発振
周波数との周波数差を検出し出力する検出手段と、該検
出手段からの出力によシ前記第1の局部発振回路の発振
周波数を制御するPLL (フェーズロックループ)回
路を具備したことを特徴とするダブルス−パーヘテロダ
インチューナ。
1) A first mixer that converts the frequency of an RF input signal into an oscillation output from a first local oscillation circuit and outputs the resultant signal; In an f-pull superheterodyne tuner that includes a second mixer that converts the frequency of an oscillation output and outputs the same, the second local oscillation circuit is a multiplier that multiplies the oscillation frequency and outputs the oscillation output. a detection means for detecting and outputting a frequency difference between the fundamental oscillation frequency of the oscillator and the oscillation frequency of the first local oscillation circuit; A double superheterodyne tuner comprising a PLL (phase locked loop) circuit that controls the oscillation frequency of an oscillation circuit.
JP13584383A 1983-07-27 1983-07-27 Double superheterodyne tuner Pending JPS6028330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13584383A JPS6028330A (en) 1983-07-27 1983-07-27 Double superheterodyne tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13584383A JPS6028330A (en) 1983-07-27 1983-07-27 Double superheterodyne tuner

Publications (1)

Publication Number Publication Date
JPS6028330A true JPS6028330A (en) 1985-02-13

Family

ID=15161057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13584383A Pending JPS6028330A (en) 1983-07-27 1983-07-27 Double superheterodyne tuner

Country Status (1)

Country Link
JP (1) JPS6028330A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6519305B1 (en) 1998-04-28 2003-02-11 Rohde & Scwarz Gmbh & Co. Kg Frequency converter arrangement
JP2006153322A (en) * 2004-11-26 2006-06-15 Fujitsu General Ltd Duct cover

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6519305B1 (en) 1998-04-28 2003-02-11 Rohde & Scwarz Gmbh & Co. Kg Frequency converter arrangement
JP2006153322A (en) * 2004-11-26 2006-06-15 Fujitsu General Ltd Duct cover

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