JPS63269513A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63269513A JPS63269513A JP62103290A JP10329087A JPS63269513A JP S63269513 A JPS63269513 A JP S63269513A JP 62103290 A JP62103290 A JP 62103290A JP 10329087 A JP10329087 A JP 10329087A JP S63269513 A JPS63269513 A JP S63269513A
- Authority
- JP
- Japan
- Prior art keywords
- film
- film formation
- inert gas
- supplied
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000011261 inert gas Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 abstract description 49
- 239000007789 gas Substances 0.000 abstract description 19
- 230000015572 biosynthetic process Effects 0.000 abstract description 14
- 239000001307 helium Substances 0.000 abstract description 12
- 229910052734 helium Inorganic materials 0.000 abstract description 12
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 12
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000002994 raw material Substances 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 abstract description 3
- 229910004012 SiCx Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- -1 etc. are used Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は半導体装置の製法に関し、とくに異種半導体を
積層して形成される接合界面を少なくとも有する半導体
装置の製法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having at least a bonding interface formed by stacking different types of semiconductors.
［従来技術およびその問題点］
半導体装置の製法として、各種のＣＶＤ法が採用されて
いる０例えば、プラズマＣＶＤ法、光ＣＶＤ法、マイク
ロ波ＣＶＤ法、ＥＣＲＣＶＤ法、ＭＯＣＶＤ法などによ
って半導体装置が形成されている。これらのＣＶＤ法に
おいては、大半が真空装置を利用するものであるから、
異種半導体を積層するに際しては、真空に排気した後、
異種半導体を積層することが実施されている。しかしな
がら、良好の半導体装置を得るためには、極めて大きい
排気能力を必要とするうえ、装置の真空度により、得ら
れる半導体装置の性能や安定性が太き（左右されると云
う問題点があった。これは、恐らく、半導体接合界面（
異種界面）形成時の真空度が装置の特性と大きな相関を
有するためと推定される。とりわけ、非晶質半導体にお
いて、この異種界面の性能が問題にされており、解決の
ための努力が払われている。[Prior art and its problems] Various CVD methods are used to manufacture semiconductor devices. For example, semiconductor devices are formed by plasma CVD, photoCVD, microwave CVD, ECRCCVD, MOCVD, etc. has been done. Since most of these CVD methods utilize vacuum equipment,
When stacking different types of semiconductors, after evacuation,
Stacking different types of semiconductors has been practiced. However, in order to obtain a good semiconductor device, an extremely large exhaust capacity is required, and there is the problem that the performance and stability of the resulting semiconductor device are greatly affected by the degree of vacuum in the device. This is probably due to the semiconductor junction interface (
This is presumed to be because the degree of vacuum at the time of forming the heterogeneous interface has a strong correlation with the characteristics of the device. Particularly in amorphous semiconductors, the performance of this heterogeneous interface is a problem, and efforts are being made to solve it.
［基本的着想］
本発明者は特願昭５７−１８２９７８号 において、界
面の形成にさいして、水素放電を実施して水素プラズマ
にさらすことによる非晶質光電変換素子の製法を提案し
た０本発明者等は界面形成時に一旦、成膜装置へのガス
導入を止めて真空に排気しなければ、水素放電は必ずし
も必要とされず不活性ガスで原料ガスを置換し不活性ガ
ス雰囲気とすれば上記問題点を解決することが出来るこ
とを見出した０本発明はかかる知見にもとすいてなされ
るに到ったものである。[Basic Idea] In Japanese Patent Application No. 57-182978, the present inventor proposed a method for manufacturing an amorphous photoelectric conversion element by performing hydrogen discharge and exposing to hydrogen plasma to form an interface. The inventors believe that hydrogen discharge is not necessarily necessary unless the gas introduction into the film forming apparatus is stopped and evacuated to a vacuum when forming the interface, and if the source gas is replaced with an inert gas to create an inert gas atmosphere. The present invention, which has found that the above problems can be solved, has been made based on this knowledge.
［発明の目的］
すなわち、本発明の目的は、積層により製造される半導
体装置の界面形成法を改善することにより、半導体装置
の特性を改善することにある。[Object of the Invention] That is, an object of the present invention is to improve the characteristics of a semiconductor device by improving a method for forming an interface in a semiconductor device manufactured by lamination.
［発明の開示］
本発明の上記目的は、性質の異なる半導体層を積層して
形成される接合界面を少な（とも有する半導体装置を形
成するにあたり、該接合界面の形成を不活性ガス雰囲気
下に行うことを特徴とする半導体装置の製法であり、特
に、一つの半導体層を形成し、引き続いて不活性ガス置
換した後、これと異なる異種半導体を積層する製法、に
ょうて達成することが出来る。[Disclosure of the Invention] The above object of the present invention is to form a semiconductor device having a small number of bonding interfaces formed by stacking semiconductor layers having different properties, and to form the bonding interface under an inert gas atmosphere. In particular, it is a manufacturing method of semiconductor devices characterized by forming one semiconductor layer, replacing it with an inert gas, and then laminating different types of semiconductors. .
本発明の最も特徴とするところは、要するに、該接合界
面の形成を不活性ガス雰囲気下に行うことであり、具体
的には、一つの半導体層を形成し、引き続いて不活性ガ
ス置換した後、これと異なる異種半導体を積層すること
である。The most characteristic feature of the present invention is that the bonding interface is formed in an inert gas atmosphere. Specifically, after forming one semiconductor layer and subsequently replacing the inert gas with , by stacking different types of semiconductors.
該不活性ガス置換は、反応性ガスを不活性ガスによりガ
ス置換する方法により容易に実施され、また不活性ガス
を反応性ガスの希釈ガスとして使用している場合には、
該反応性ガスの供給を停止することにより系内を不活性
ガス雰囲気にすることが出来、本発明の目的を達成でき
るのである。The inert gas replacement is easily carried out by replacing the reactive gas with an inert gas, and when the inert gas is used as a diluent gas for the reactive gas,
By stopping the supply of the reactive gas, an inert gas atmosphere can be created in the system, and the object of the present invention can be achieved.
なお、不活性ガス置換時の条件は、成膜装置内の圧力が
１ｍＴｏｒｒ以上、好ましくは１０ｍＴｏｒｒ以上、特
に好ましくは１００ｍＴｏｒｒ以上になるように不活性
ガスを供給すること以外には、とくに限定されない。Note that the conditions for replacing the inert gas are not particularly limited, except that the inert gas is supplied so that the pressure inside the film forming apparatus is 1 mTorr or more, preferably 10 mTorr or more, particularly preferably 100 mTorr or more.
不活性ガスとしては、ヘリウム、アルゴン、ネオン、ク
リプトン、キセノン等が用いられるが、純度および本発
明の効果の点において、ヘリウムが特に好ましい。As the inert gas, helium, argon, neon, krypton, xenon, etc. are used, and helium is particularly preferred in terms of purity and the effects of the present invention.
また、温度について一言すれば、成膜温度は半導体装置
の性能に大きい影響を与えることが知られている。一方
、不活性ガス置換の効果は成膜温度に大きく影響されな
いが、一層の効果をあげるために、通常、４５０°Ｃ以
下の成膜温度で不活性ガス置換を実施することが好まし
い。具体的には、目的とする半導体装置に応じて、４５
０°Ｃ以下の成膜温度が適宜選択されるものである。Regarding temperature, it is known that film formation temperature has a large effect on the performance of semiconductor devices. On the other hand, although the effect of inert gas replacement is not greatly affected by the film formation temperature, it is usually preferable to carry out inert gas replacement at a film formation temperature of 450° C. or lower in order to obtain further effects. Specifically, depending on the target semiconductor device, 45
A film forming temperature of 0° C. or lower is appropriately selected.
異種半導体を積層して形成される接合界面を少な（とも
有する半導体装置は各種存在し、本発明はその何れにつ
いても基本的に好適に適用出来ることは云うまでもない
ものであるが、以下、具体的示例として、ｐｉｎ型アモ
ルファス太陽電池の場合について、本発明を実施するう
えで好ましい形態を説明する。There are various types of semiconductor devices that have a small number of bonding interfaces formed by stacking different types of semiconductors, and it goes without saying that the present invention can basically be suitably applied to any of them. As a specific example, a preferred embodiment of the present invention will be described in the case of a pin type amorphous solar cell.
［発明を実施するための好ましい形態］透明電極が形成
されたガラス基板を成膜装置に導入し成膜温度に加熱す
る。ｐ型アモルファス半導体の原料ガスを、必要に応じ
て希釈して、成膜装置に供給する。該ガス圧力を１０−
４〜１０Ｔｏｒｒに調整し、高周波、マイクロ波あるい
は直流電力による放電を実施して原料を分解し該基板上
にｐ型アモルファス半導体を形成する。[Preferred form for carrying out the invention] A glass substrate on which a transparent electrode is formed is introduced into a film forming apparatus and heated to a film forming temperature. A raw material gas for a p-type amorphous semiconductor is diluted as necessary and supplied to a film forming apparatus. The gas pressure is 10-
The temperature is adjusted to 4 to 10 Torr, and discharge is performed using high frequency, microwave, or DC power to decompose the raw material and form a p-type amorphous semiconductor on the substrate.
必要膜厚のＰ型アモルファス半導体層が形成されたとこ
ろで、原料ガスを不活性ガスで置換し、該半導体の形成
を終了する。この際不活性ガスの圧力は１０−３〜１０
Ｔｏｒｒ程度になるようにする。かくして、接合界面形
成時に不活性ガス雰囲気下とするのである。圧力の安定
後、同一の成膜室でそのままｉ型アモルファス半導体の
原料ガスを導入し、ｉ型アモルファス半導体層を、該ｐ
型アモルファス半導体層の上に積層して形成するか、よ
り好ましくは、減圧状態を維持したままで、別室の成膜
室に該基板を移送して、ｉ型アモルファス半導体層の形
成を行う。なお、一般に好ましい方法として、不活性ガ
ス、特にヘリウムで原料ガスを希釈する方法があるが、
かかる方法を採用する場合は、接合界面形成時に原料ガ
スを停止するだけで、容易に界面を不活性ガス雰囲気と
することが出来る。When a P-type amorphous semiconductor layer with a required thickness is formed, the source gas is replaced with an inert gas, and the formation of the semiconductor is completed. At this time, the pressure of the inert gas is 10-3 to 10
It should be about Torr. In this way, an inert gas atmosphere is used when forming the bonding interface. After the pressure has stabilized, raw material gas for the i-type amorphous semiconductor is directly introduced into the same film-forming chamber, and the i-type amorphous semiconductor layer is formed using the p-type amorphous semiconductor layer.
The i-type amorphous semiconductor layer is formed by stacking the substrate on top of the i-type amorphous semiconductor layer, or more preferably, the substrate is transferred to a separate film forming chamber while maintaining a reduced pressure state to form the i-type amorphous semiconductor layer. Note that a generally preferred method is to dilute the raw material gas with an inert gas, especially helium.
When such a method is adopted, the interface can be easily brought into an inert gas atmosphere by simply stopping the source gas when forming the bonding interface.
ｐ型アモルファス半導体と同様にして、必要膜厚のｉ型
アモルファス半導体層が形成されたところで、原料ガス
を不活性ガスで置換し、該ｉ型アモルファス半導体の形
成を終了し、ｎ型アモルファス半導体の形成に移る。こ
の場合も、減圧状態を維持したままで、別室の成膜室に
該基板を移送して、ｎ型アモルファス半導体を形成を行
うことが好ましい、このように、一つの半導体の形成か
ら次の半導体の形成に移るときに、すなわち接合界面を
形成するとき、不活性ガスの圧力が１０４〜１０τｏｒ
ｒのなるように不活性ガス置換し、不活性ガス雰囲気と
することが本発明の特徴である。In the same manner as for the p-type amorphous semiconductor, when the i-type amorphous semiconductor layer of the required thickness is formed, the source gas is replaced with an inert gas, the formation of the i-type amorphous semiconductor is completed, and the n-type amorphous semiconductor layer is formed. Move on to formation. In this case as well, it is preferable to transfer the substrate to a separate deposition chamber while maintaining a reduced pressure state and form an n-type amorphous semiconductor. In other words, when forming the bonding interface, the pressure of the inert gas is 104 to 10τor.
A feature of the present invention is that the atmosphere is replaced with an inert gas so that r is satisfied.
［発明の効果］
未発明の実施により、得られる半導体装置の特性は大幅
に向上するが、これは、接合界面の形成を不活性ガス雰
囲気に行うことにより、従来半導体装置の積層界面に蓄
積されていた、酸素、窒素、炭素を始めとする各種の不
純物濃度が低減されたためと推定される。[Effects of the invention] By carrying out the invention, the characteristics of the resulting semiconductor device are greatly improved, but this is due to the fact that the bonding interface is formed in an inert gas atmosphere, which eliminates the effects that have accumulated at the laminated interface of the conventional semiconductor device. This is presumed to be due to a reduction in the concentration of various impurities, including oxygen, nitrogen, and carbon.
［実施例］および［比較例］
第１図に模式的に表わした、平行平板電極を有するプラ
ズマＣＶＤ装置において、透明電極が形成されたガラス
基板上に、ｐ型ａ−ＳｉＣｘ：Ｈ（ｘ＝０．０５）膜を
形成した。原料ガスの流量比はジボラン／ジシラン＝
１／１０００〜１／１０ 、ジメチルシラン／ジシラン
−１／１〜２／１、ジシラン／水素−１７２０〜１１５
の範囲で適宜選択した。形成温度２５０℃、圧力０．２
Ｔｏｒｒの条件で１００〜１５０Ａの膜厚になるように
成膜室ｌにおいて形成された。[Example] and [Comparative Example] In a plasma CVD apparatus having parallel plate electrodes schematically shown in FIG. 1, p-type a-SiCx:H (x= 0.05) A film was formed. The flow rate ratio of raw material gas is diborane/disilane =
1/1000 to 1/10, dimethylsilane/disilane-1/1 to 2/1, disilane/hydrogen-1720 to 115
Appropriate selection was made within the range. Forming temperature 250℃, pressure 0.2
The film was formed in a film forming chamber 1 to have a film thickness of 100 to 150 Å under Torr conditions.
ｐ型ａ−５ｉＣｘ：Ｆｌ膜形成後、ジボラン、ジシラン
、ジメチルシラン、水素の供給を停止し、ヘリウムを供
給して、成膜室１の圧力を０．１Ｔｏｒｒとした。After forming the p-type a-5iCx:Fl film, the supply of diborane, disilane, dimethylsilane, and hydrogen was stopped, and helium was supplied to set the pressure in the film forming chamber 1 to 0.1 Torr.
また、成膜室２にも、ヘリウムを供給して、圧力をＱ、
１Ｔｏｒｒにした。ついでゲート弁１９を開きｐ型ａ−
５ｉＣｘ：Ｈ（ｘ＝０．０５） Ｉｆｉが形成された基
板を成膜室２に移送した。ゲート弁１９を閉じ、成膜室
２にジシランを供給し、成膜圧力０．１５Ｔｏｒｒ、成
膜温度３００°Ｃにおいて、ｉ型ａ−５ｉ：Ｈ膜を形成
した。なお、成膜室２においては、ヘリウムを停止する
ことなくジシランを供給することによって、成膜圧力を
調整することが好ましい。In addition, helium is also supplied to the film forming chamber 2, and the pressure is set to Q,
I set it to 1 Torr. Then, open the gate valve 19 and open the p-type a-
5iCx:H (x=0.05) The substrate on which Ifi was formed was transferred to the film forming chamber 2. The gate valve 19 was closed, disilane was supplied to the film forming chamber 2, and an i-type a-5i:H film was formed at a film forming pressure of 0.15 Torr and a film forming temperature of 300°C. Note that in the film forming chamber 2, it is preferable to adjust the film forming pressure by supplying disilane without stopping the supply of helium.
必要膜厚のｉ型ａ−５ｉ：Ｈ膜を形成した後、ジシラン
の供給を停止して、ヘリウムのみを供給する。After forming the i-type a-5i:H film of the required thickness, the supply of disilane is stopped and only helium is supplied.
成膜室３にもヘリウムを供給して、成膜室２と同圧にす
る。同圧になった後、ゲート弁２０を開きｉ型ａ−５ｉ
：Ｈ膜が形成された基板を成膜室３に移送する。ゲート
弁２０を閉じ、原料ガスを供給して、ｎ型半導体薄膜を
形成する。原料ガスの流量比は、ホスフィン／モノシラ
ン＝ １／１００〜５／１００．モノシラン／水素＝１
／２０〜１１５０の範囲から、適宜選択された。こうし
て、形成されたｎ型半導体薄膜は微結晶化されたもので
あった。ついで、金属電極を形成して、ｐｉｎ構造を有
するアモルファス光電変換装置を得た。この装置の光電
変換特性を第１表に示した。Helium is also supplied to the film forming chamber 3 to make it the same pressure as the film forming chamber 2. After the pressure becomes the same, open the gate valve 20 and
:The substrate on which the H film is formed is transferred to the film forming chamber 3. The gate valve 20 is closed, source gas is supplied, and an n-type semiconductor thin film is formed. The flow rate ratio of the raw material gas is phosphine/monosilane = 1/100 to 5/100. Monosilane/hydrogen = 1
/20 to 1150 as appropriate. The n-type semiconductor thin film thus formed was microcrystalline. Then, metal electrodes were formed to obtain an amorphous photoelectric conversion device having a pin structure. The photoelectric conversion characteristics of this device are shown in Table 1.
比較のために透明電極が形成されたガラス基板上に、ｐ
型ａ−５ｉＣｘ：Ｈ（ｘ＝０．０５）膜を実施例と同じ
条件で同じ膜厚だけ形成した後、原料ガスの供給をすべ
て停止し、成膜室の圧力が５ｘｌＯ−’〜５ｘｌＯ−”
Ｔｏｒｒになるまで、排気した。また、成膜室２も５ｘ
１０−’〜５ｘｌＯ−’Ｔｏｒｒに排気し、成膜室１と
の圧力差がほとんどな（なったところで、ゲート弁１９
を開きｐ型ａ−５ｉＣに：Ｈ（に・０．０５）膜が形成
された基板を成膜室２に移送した。ゲート弁１９を閉じ
、以下実施例に従ってｐｉｎ構造を有するアモルファス
光電変換装置を得た。For comparison, p was placed on a glass substrate on which a transparent electrode was formed.
After forming a type a-5iCx:H (x=0.05) film with the same thickness under the same conditions as in the example, all supply of source gas was stopped and the pressure in the film forming chamber was set to 5xlO-' to 5xlO- ”
The exhaust was pumped until it reached Torr. In addition, the film forming chamber 2 is also 5x
10-' to 5xlO-' Torr, and when there is almost no pressure difference with the film forming chamber 1, close the gate valve 19.
The chamber was opened, and the substrate on which the p-type a-5iC:H (ni.0.05) film was formed was transferred to the film-forming chamber 2. The gate valve 19 was closed, and an amorphous photoelectric conversion device having a pin structure was obtained according to the following examples.
実施例、比較例を纏めた第１表から明らかなごとく、本
発明の半導体装置の光電変換効率はＡＭＩ 。As is clear from Table 1, which summarizes Examples and Comparative Examples, the photoelectric conversion efficiency of the semiconductor device of the present invention is AMI.
１００ｓ＋Ｗ／ｃｍ”において１１％を越える高いもの
であることが示される。この効率を基準として、さらに
実施例および比較例と同一の実験例をそれぞれ１０回実
施した結果の平均値をも第１表に示した。この平均値に
着目すれば、比較例においても、最高の効率は１０．５
％を得ることができるものの、実施例に比較して、効率
の変動がはるかに大きいことがわかる。かかる効率の大
きな変動についてはｐｎ接合界面の形成時に不活性ガス
置換操作を行わないため、恐らくｐ型膜とｉ型膜の界面
付近の不純物濃度の制御ができていないためと考えられ
るが、その詳細については、現在のところ勿論明らかに
されてはいない。100s+W/cm" is shown to be high, exceeding 11%. Based on this efficiency, Table 1 also shows the average value of the results of carrying out the same experiment 10 times as the Example and Comparative Example. If we focus on this average value, even in the comparative example, the highest efficiency is 10.5.
%, but it can be seen that the variation in efficiency is much larger than in the example. This large variation in efficiency is probably due to the fact that the impurity concentration near the interface between the p-type film and the i-type film cannot be controlled because the inert gas replacement operation is not performed when forming the p-n junction interface. Of course, details have not been disclosed at this time.
第１表
〔産業上の利用可能性〕
本発明はこのように異種の半導体を真空装置内で積層す
るにさいして、積層界面の不純物濃度の低減を可能にす
るので、先に説明した太陽電池以外の半導体装置におい
ても、その実用的な製造方法として有効である。当然の
ことながら、本発明は、半導体−半導体の界面のみでは
なく、半導体−導電体、半導体−絶縁体、導電体−絶縁
体の界面の不純物低減にも効果を発揮する。Table 1 [Industrial Applicability] The present invention makes it possible to reduce the impurity concentration at the lamination interface when different types of semiconductors are laminated in a vacuum apparatus, so that it is possible to reduce the impurity concentration at the lamination interface. It is also effective as a practical manufacturing method for other semiconductor devices. Naturally, the present invention is effective in reducing impurities not only at the semiconductor-semiconductor interface, but also at the semiconductor-conductor, semiconductor-insulator, and conductor-insulator interfaces.
すなわち、本発明は、従来、超高真空対応の成膜装置で
しか対応できなかった高性能太陽電池等の半導体装置の
安定製造を従来から用いられている通常性能の成膜装置
においても可能にするものであり、実用上きわめてすぐ
れた発明であると云わざるを得ないのである。In other words, the present invention makes it possible to stably manufacture semiconductor devices such as high-performance solar cells, which was conventionally possible only with ultra-high vacuum compatible film-forming equipment, using conventional film-forming equipment with normal performance. Therefore, it must be said that it is an extremely excellent invention in practical terms.
第１図は本発明を実施することのできる成膜装置の一例
を示す模式図である０図中１．２．３・−成膜室、４一
基板導入室、５・−電極形成室、６・一基板、？、８．
９・−高周波導入電極、１０，１１．１２・−−−−一
一一接地電極、１３．１４．１５．１６・・−・−・加
熱手段、１７．１８，１９，２０．２１．２２・・−・
ゲート弁、２３．２４，２５，２６．２７．２８−−−
−−−・−真空排気手段、２６．２７．２８・−・−原
料ガス導入手段。FIG. 1 is a schematic diagram showing an example of a film forming apparatus in which the present invention can be carried out. 6. One board? , 8.
9.-High frequency introduction electrode, 10, 11.12.----11.1 Ground electrode, 13.14.15.16...Heating means, 17.18, 19, 20.21.22・・・－・
Gate valve, 23.24, 25, 26.27.28---
---.- Vacuum exhaust means, 26.27.28.-- Raw material gas introduction means.
Claims (2)
界面を少なくとも有する半導体装置を形成するにあたり
、該接合界面の形成を不活性ガス雰囲気下に行うことを
特徴とする半導体装置の製法。(1) A method for manufacturing a semiconductor device, which comprises forming a semiconductor device having at least a bonding interface formed by laminating semiconductor layers having different properties, and forming the bonding interface in an inert gas atmosphere.
置換した後、これと異なる異種半導体を積層する特許請
求の範囲第１項記載の製法。(2) The manufacturing method according to claim 1, in which one semiconductor layer is formed, and then a different type of semiconductor is laminated after inert gas replacement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62103290A JPS63269513A (en) | 1987-04-28 | 1987-04-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62103290A JPS63269513A (en) | 1987-04-28 | 1987-04-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63269513A true JPS63269513A (en) | 1988-11-07 |
Family
ID=14350165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62103290A Pending JPS63269513A (en) | 1987-04-28 | 1987-04-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63269513A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60111418A (en) * | 1983-10-26 | 1985-06-17 | ア−ルシ−エ− コ−ポレ−ション | Coating method and device |
| JPS61296710A (en) * | 1985-06-25 | 1986-12-27 | Kanegafuchi Chem Ind Co Ltd | Manufacture of amorphous silicon system semiconductor |
-
1987
- 1987-04-28 JP JP62103290A patent/JPS63269513A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60111418A (en) * | 1983-10-26 | 1985-06-17 | ア−ルシ−エ− コ−ポレ−ション | Coating method and device |
| JPS61296710A (en) * | 1985-06-25 | 1986-12-27 | Kanegafuchi Chem Ind Co Ltd | Manufacture of amorphous silicon system semiconductor |
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