JPS63268197A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To obtain a nonvolatile memory capable of writing without disconnecting the circuit by making a circuit which is composed of source/drain of an enhancement type MOS transistor TR and a diode connected in parallel with the source/drain a writing status. CONSTITUTION:The n-channel enhancement type MOSTR 101 consists of the drain electrode 111, the source electrode 112, and a gate electrode 113, and the diode 102 is connected so as to obtain forward direction from the drain to the source. When a positive voltage is impressed to the electrode 111 with respect to the electrode 112, the diode 102 comes in the forward direction, the electrodes 111 and 112 come conductive irrespective of the potential of the electrode 113. If the diode 102 is not connected, the electrodes 111 and 112 does not come conductive unless a voltage higher than the threshold is impressed to the electrode 113, therefore, this can be discriminated from the case shown in the figure where the diode is connected in parallel with the enhancement type MOSTR. Hence, the circuit can be used as a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only or one-time writable read-only semiconductor nonvolatile memory, and particularly to a memory element with no special restrictions on use.

[Conventional technology]

Among the applications of semiconductor nonvolatile memory, there are many applications in which information once written does not need to be rewritten again, and read-only memories are used for such applications.

Some read-only memories allow users to write information to them, while others do not.

An example of a ROM in which a user can write information is a fused ROM using polysilicon, and an example of a ROM in which a user cannot write information is a mask ROM. Since mask ROM is used to write information at the manufacturing stage, it is manufactured to order, and there are drawbacks for manufacturers, such as the inability to mass-produce, and for users, such as long delivery times and high prices if the number of orders is small. Writable memory is more demanding because of its drawbacks.

[Problem that the invention seeks to solve]

However, since information is written in a fused ROM by permanently cutting off the circuit, there are restrictions on how it can be used, such as not being able to use it as a means of transmitting signals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor nonvolatile memory that can be written by the user without interrupting the circuit and can also be used as a mask ROM.

[Means for solving problems]

The first feature of the present invention is that in order to provide memory characteristics without interrupting the circuit, one diode is connected in parallel to the source and drain of an enhanced type MOS transistor, and the enhanced type MoS transistor is set to a write state. This means that it is in a writing state.

A second feature of the present invention is to electrically short-circuit either the source or the drain of the enhanced MOS transistor with the substrate serving as the channel region, in order to easily realize the configuration described in the first feature. As a result, it is possible to equivalently connect the enhanced type MOS transistor and the poor diode in parallel.

A third feature of the present invention is that, in order to enable writing by the user, a metallic bond is created in a part of the p-n junction of either the source or the drain of the enhanced MOS transistor. , to create an electrical short circuit between either the source or the drain and the substrate.

A fourth feature of the present invention is that when the enhanced MOS transistor is an n-channel transistor, its substrate is connected to a different signal line than the source/drain and gate.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, how each feature solves the problems.

FIG. 1 shows an embodiment of the parallel connection of an enhanced MOS transistor and a diode according to the present invention.

In Figure 1, an n-channel Enno-nce type MO8I
- The transistor 101 is composed of a drain electrode 111, a source electrode 112, and a gate electrode 113, and the diode 10 is arranged in a forward direction from the drain to the source.
2 are connected.

In FIG. 1, if a positive voltage is applied to the drain electrode 111 with respect to the source electrode 112, the diode 102 becomes in the forward direction.
2 becomes conductive regardless of the potential of the gate electrode 113.

If the diode 102 is not connected, the drain electrode 111 and the source electrode 112 are in a non-conducting state unless a voltage higher than the threshold voltage is applied to the gate electrode 116. Therefore, the enhanced type MOS transistor and diode shown in FIG. can be distinguished from the parallel connection state. Therefore, it can be used as memory. It is clear that an n-channel enhanced MOS transistor can also be used as a memory in the same way.

FIG. 2 shows an embodiment of an n-channel enhanced type MOS transistor according to the present invention, which was devised to equivalently and simply realize the structure shown in FIG. 1, and shows a cross section of the basic part.

The n-channel enhanced type MOS transistor in FIG. 2 has a p-type diffusion region 202 on a p-type substrate 201 to facilitate connection with the substrate 201, an n-type drain 203 and an n-type source 2. , 04, a drain electrode 211 connected to the p-type diffusion region 202 and the drain 203 at the same time, a source electrode 212, and a gate electrode 213 on the gate insulating film 221.

In Fig. 2, instead of connecting a diode in parallel to an enhanced type MO8 transistor, the drain 203 is connected to a p-type substrate 20 through a drain electrode 211 and a p-type diffusion region 202.
1 to make it electrically equivalent to that shown in FIG.

A p-type substrate 20 corresponds to the diode in FIG.
1 and an n-type source 204 are also p-n junctions. If a positive voltage is applied to the drain electrode 211 with respect to the source electrode 212, the p-n junction diode consisting of the p-type substrate 201 and the n-type source 204 will be in the forward direction. Gate electrode 21
It becomes conductive regardless of the potential of 6.

Therefore, an n-channel enhanced type MOS transistor in which the drain 203 and the substrate are short-circuited as shown in FIG. 2 has a forward direction from the drain to the source as shown in FIG. It operates exactly the same as the enhanced type MOS transistor, and can be used as a memory if combined with a normal enhanced type MO8) transistor whose drain is not shorted to the substrate.

□ It is clear that a P-channel enhanced type MO8) transistor can also be used as a memory in the same way.

FIG. 3 shows an embodiment of an n-channel enhanced MOS transistor according to the present invention, which is designed so that a memory user can write information to obtain a configuration equivalent to that shown in FIG. This is what is shown.

The n-channel enhanced type MOS transistor in FIG. 3 has a p-type diffusion region 302 on a p-type substrate 301 to facilitate connection with the substrate 301, an n-type drain 306 and an n-type source. 604, has a substrate electrode 614 connected to the p-type diffusion region 602, has a drain electrode 611 and a source electrode 612, and has a gate insulating film 62.
1 has a gate electrode 313 on top.

In addition, each time a user writes information, the covalent bond is destroyed and the p-n junction changes to a metallic bond.
This is a region 361 indicated by a dotted line where metallic bonding occurs.

In Fig. 3, if the user does not write information, it is a normal enhanced type MOS transistor, and if the user writes information, the drain 303 and the substrate 601 become electrically short-circuited, so it is the same as Fig. 2. It starts to work.

In FIG. 3, the mechanism for producing a metallic bond in the region 331 that produces a metallic bond is explained as follows.

Since the drain 606, the substrate 601, and the source 604 are n-type, p-type, and n-type, respectively, they have a structure similar to that of an NPN bipolar transistor, and operate as a bipolar transistor when each has an appropriate potential relationship.

Since a positive voltage is applied to the drain electrode 611, the p-n junction between the substrate 301 and the drain 303 is biased in the opposite direction, and the drain electrode 611 functions as a bipolar transistor.
03 is a collector.

Therefore, source 304 becomes an emitter and source 60
If the potential relationship between the transistor 4 and the substrate 301 is such that the p-n junction is in the forward direction, it will operate as a bipolar transistor. The forward potential relationship between the source 604 and the substrate 601 is as follows:
It can be easily obtained by applying a positive voltage to the substrate electrode 614, and if it is an n-channel MO8) transistor,
It can also be obtained by operating in a potential state where impact ionization is likely to occur.

Now, it is well known that when the potential of the gate electrode 316 is lower than that of the drain 603, the drain electric field is strengthened in the region 661 directly under the gate where metallic bonding occurs, and in such a state it operates as a bipolar transistor. Then, the carriers are accelerated by the strong electric field and become in a high energy state, so the covalent bonds are broken and the bond changes to a metallic bond.

By the way, n-channel MO3) transistors are prone to impact ionization, so they can be operated as bipolar without externally manipulating the substrate potential, but p
Since a channel MOS transistor does not easily cause impact ionization, it cannot be operated as a bipolar transistor unless the substrate potential is controlled externally. Therefore p
Channel MO8) When using a transistor as a nonvolatile memory, the substrate must be connected to a signal line different from the source, drain, and gate.

This is the reason for the fourth feature.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to obtain a writable nonvolatile memory without interrupting the circuit, and the effect is very large.

Since the manufacturing process is exactly the same as that for a normal enhanced type MOS transistor, if it is applied to a semiconductor integrated circuit made of enhanced type MOS transistors, there will be no increase in manufacturing costs, and the effect will be even more significant.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a parallel connection of an enhanced type MOS transistor and a diode in an embodiment of the present invention, and FIGS.
FIG. 2 is a cross-sectional view showing an OS transistor. 101...Enhanced MOS transistor,
102...Diode.

Claims (4)

[Claims] (1) A semiconductor nonvolatile memory characterized in that a diode connected in parallel to the source and drain of an enhancement type MOS transistor is in a write state, and an enhancement type MOS transistor is in a non-write state. (2) Either the source or the drain of the enhanced MOS transistor is electrically short-circuited with the substrate that becomes the channel region, thereby equivalently establishing a parallel connection between the enhanced MOS transistor and the diode. A semiconductor nonvolatile memory according to claim 1. (3) Either the source or drain of an enhanced MOS transistor is electrically shorted to the substrate due to the presence of a metallic bond in a part of the p-n junction. A semiconductor nonvolatile memory according to claim 1, characterized in that: (4) The semiconductor nonvolatile memory according to claim 1, wherein the substrate of the enhanced p-channel MOS transistor is connected to a signal line different from that of the source/drain and gate.