JPS6326752A - Designating system for common bus address - Google Patents

Abstract

PURPOSE:To decrease the bus occupation frequency and to shorten the processing time in a system where the addresses of plural modules are designated, by securing a field on a common bus to designate plural modules simultaneously. CONSTITUTION:An offset field OF111 of (a) bits is secured on a common bus to designate 2<n> sets of module groups. Similarly, an m-bit address vector field 112 is secured on the common bus to select and designates simultaneously plural modules (at most m pieces) out of plural designated module groups. The high- order n-bit 31 of an address register 3 and the address of the OF111 are supplied to a comparator 4 and a coincidence signal is sent to a check circuit 6. While the low-order m-bit 32 of the register 3 opens a corresponding AND 62 out of (m) pieces of decoding signals 51 via a decoding circuit 5 to secure the input of the data set one the corresponding field 112. Then a selection signal 61 is outputted via the circuit 6.

Description

[Detailed Description of the Invention] [Summary] This is an addressing method on a common bus between multiple modules that transfers data, in which a module-specific address is sent onto an address field constituting the common bus. In order to solve the problem that the common bus was occupied many times and took a lot of time because only one address could be specified at the same time, we created a field that allows multiple modules to be specified at the same time on the common bus. It becomes possible to reduce the number of occupancies and shorten the processing time.

[Industrial application field]

The present invention relates to an addressing method on a common bus between multiple modules that performs data inheritance.

2. Description of the Related Art In the field of data processing, etc., a common bus is provided within a device, and a plurality of modules are connected to perform data transfer, thereby realizing a device with high connectivity.

In this case, the module that sends the data or information is
The address of the receiving module is sent on a common bus, but when sending the same information to multiple modules, it is necessary that the number of times the bus is occupied is small and the processing time is short.

[Conventional technology]

FIG. 4 shows a block diagram illustrating a conventional example.

Figure 4 shows a plurality of modules 1 that are replaceable functional units.
(0) to 1(n) and its modules 1(0) to 1(n)
) and a common bus (1) for transmitting information between modules 1(0) to 1(n).

Also, the common bus (1) connects each module 1(0) to 1(n).
address field Ql) carrying the unique address where
and a data field that carries the data to be left behind.

When a plurality of modules 1(0) to 1(n) are specified in the conventional method, one method is that if a predetermined value on the address field 0υ is sent, all related modules 1 (O) to 1(n) are the common bus (
1) The method for importing the above data has been implemented.

[Problem that the invention seeks to solve]

That is, in the conventional method described above, the sending module 1 (0)
Although it is possible to simultaneously specify modules 1(0) to 1(n) that are predefined in the system from ~1(n),
It has been impossible to simultaneously select and specify arbitrary modules within a specified module group.

Therefore, if it is necessary to select and specify any module from the specified module group as described above, the processing time will be longer, and the common bus (1
1 was to be occupied for a long time.

Measures to solve problem C] FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram shown in Fig. 1 shows the outline of the configuration within module 1(i) and the relationship with the common bus fl), and its configuration is such that 28 sets of information destination modules are specified in the address field αυ. n-bit offset field (11
1) An address field aυ consisting of an m-bit address vector field (112) that specifies m modules in the module group specified by the offset field (111) in bit correspondence, and data for transferring data. A common bus (1) having a field 0 and an address register 3 that generates an address of a predetermined bit, and a plurality of high-order bits (3) sent from the address register 3.
1) and the contents of the offset field (111), a comparison means (comparison circuit) 4, and an address register 3.
a decoding means (decoding circuit) 5 for converting the lower bins (32) sent from the plurality of lower bins and activating a predetermined decode signal (51) among the plurality of output signals; and the contents of the address vector field (112). The output (51) of the corresponding decoding means (decoding circuit) 5 is active, and the output (41) of the comparing means (comparing circuit) 4
) is active, the module 1(i) has a check means (check circuit) 6 that activates a select signal (61) indicating that the module has been addressed.

[Effect]

An offset field (111) for simultaneously specifying 2'' sets of module groups on the common bus (1), and an address vector for arbitrarily selecting and specifying multiple modules (up to m can be selected) from the specified multiple module group. field (112) and this offset field (11
1) A means for validating the addressing sent through the address vector field (112) is provided in each module, and it is possible to address a range of 21×m modules using (n+m) tree signal lines, and further address a maximum of m By allowing multiple modules to be specified simultaneously, the addressing processing time can be shortened, and the number of times and time that the common bus is occupied can be reduced.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating the module specification status in the embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

Check circuit 6 in module 1(i) of this embodiment
are set in number corresponding to the number of bit-corresponding addresses (m in this embodiment) specified in the address vector field (112), and
112) and the output signal (51) from the decoding circuit 5. AND62(1) ~AN
D62(m) and each AND62(1) ~AND62(
0R63 which takes the logical sum of the outputs of m), and AND64 which takes the logical product of the output signal (41) of the comparator circuit 4 and the output of 0R63.

The address register 3 is a (n+Logzm) bit register, and stores the unique address of each module 1(i).

The upper n bits (31) of this address are sent to the comparator circuit 4 and compared with the address contents of the offset field (111). If the conditions match, a conveyor signal (41) is sent.
becomes active and is sent to one input terminal of AND64 in check circuit 6.

Furthermore, the lower m bits (32) of the address register 3 are sent to the decode circuit 5, and one of the m decode signals (51) becomes active and the corresponding AND62 (1) to AND62 (m ) is sent to the input terminal. .

For example, the decode signal (5
1 (1)) becomes active, and the corresponding bit (112 (11)) of the address vector field (112) becomes active.
) is active and the conveyor signal (41) is active, the select signal (61) becomes active indicating that the module 1(i) in question has been addressed.

In addition, FIG. 3 is a diagram showing the specification/selection status of module 1(i). First, N of the offset field (111) is
By specifying the bit, a specified module group is selected from among the modules (shown in FIG. 3A) consisting of (2'Xm). (The selected situation is shown in FIG. 3(B)) Next, predetermined modules (maximum m) are simultaneously selected by the m bits of the address vector field (112). As shown above (shown in Figure 3(C)), (n+m
) signal lines can address a range of (2″Xm) modules, and furthermore, it is possible to simultaneously designate up to m arbitrary modules.

〔Effect of the invention〕

According to the present invention as described above, the addressing processing time can be shortened, and the time occupied by a common lot due to one addressing processing can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the module specification situation in the embodiment of the present invention, and FIG. Block diagrams illustrating conventional examples are shown, respectively. In the figure, ■(0) to 1(i) to 1(n) are modules, 3 is an address register, 4 is a comparison circuit, 5 is a decoding circuit,
6 is a check circuit, 62(1) to 62(m)
, 64 is AND, 63 is OR. are shown respectively.・Noto \gu Tazuki e-mail? f. mouth

Claims (1)

[Claims] A common bus ((11), (12) that connects multiple modules)
)) When exchanging information on a predetermined module (1(i)
), and each of the plurality of modules has a different unique address. an n-bit offset field ((111)) that specifies a group; and an m-bit address vector field that specifies m modules in the module group specified by the offset field ((111)) in bit correspondence. ((11
2)), and each module further includes an address register (3) that generates an address of a predetermined bit, a plurality of high-order bits ((31)) sent from the address register (3), and the offset Field ((1
11))), and a comparison means (4) for comparing the contents of the address register (3) with the contents of the address register (3).
(32)) to activate a predetermined decode signal ((51)) among the plurality of output signals; The output ((51)) of the decoding means (5) is active, and the output ((4)) of the comparing means (4) is active.
1)) is active, the corresponding module (1(i)
) is addressed, the select signal ((6
checking means (6) for activating the address field ((11)); The offset field ((111)) and the address vector field ((
112)) A common bus addressing method characterized by specifying multiple modules at the same time in combination with 112)).