JPS6326717A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the time delay of a signal by using a bus line of a precharging system and its discharging MOS transistor TR as well as a bus line of a discharging system and its pull-up MOSTR. CONSTITUTION:The 1st bus line 4 of a precharging system is set at a low level as long as input signals 102 and 103 are kept at high levels when a clock signal 101 is set at a high level. Then a P channel MOSTR 15 charges the 2nd bus line 5 of a discharging system and therefore the line 5 is set at a high level. While an N channel MOSTR 14 discharges the line 4 and therefore the line 4 is kept at a low level. Then output signals 201 and 202 are set at a high level and a low level respectively. A signal 104 is set at a low level when the signal 101 is kept at a high level with input signals 105 and 106 kept at low levels respectively. This state is equal to that set when signals 102 and 103 are kept at high levels.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor integrated circuit included entirely within a bus line.

[Conventional technology]

Generally, bus lines inside a semiconductor integrated circuit are used to transfer information between devices within a microcomputer, and the time required for the transfer is required to be short.

An example of conventional technology related to semiconductor integrated circuits? It is shown in Figure 3.

llnMOS inverter, Tri, Tr2 f'c
, N channel MOS, Tr3 n, P channel MOS
゜311 is the power NCL terminal. In FIG. 3, when the precharge signal 111 is at low level, the bus line 14
When the signal 111 is precharged and the signal 111 is at a high level, information is passed between each device, and at this time, each device outputs information, the information is placed on the bus line, and the information is not received. Information is transmitted to the MOS inverter 11 on the slave side.

Now, the case where the output of the device is connected to Tri and Tr2 will be explained.

When the precharge signal 111 is at high level, the signal 112,
If 113 reaches a high level, bus line 14
The precharged charge is discharged from the discharge line 14,
The output signal 211i of the inverter 11 becomes low level.
, reach a high level.

When the precharge signal 111 is at high level 0, the signal 112
．． If either or both of 113 are at low level, the bus line 14 will be pre-charged and its hole will remain, so the bus line 14 will be at high level? The output signal 211i' of the inverter 11 is held. , low level 1
It is 1.

[Problem that the invention seeks to solve]

Conventional semiconductor integrated circuits have a drawback in that the time delay of signals on the F-bus line is large due to loads such as load and resistance on the bus line. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks of the conventional bus line and to propose an entire semiconductor integrated circuit in which the time delay of signals is small.

The problem? Means for Solving] The bus line of the present invention includes a precharge type first bus line and a discharge MO for the first bus line.
S) It has a transistor, a discharge type second bus line, and an IOS transistor for pulling up the bus line of the skin 2, and an MO3 transistor for pulling up the second bus line on the first bus line. F structure 532.The second bus line is connected to the gate of a discharge MOS transistor of the first bus line. It will be reduced.

By using this method, it is possible to obtain a semiconductor integrated circuit in which the time delay of the signal is small. [Embodiment] The details of the present invention will be described below. Refer to and explain.

FIG. 1 is a circuit diagram of an embodiment of a semiconductor integrated circuit of the present invention.1. 2. 3 M O84 inverter, Tr1
3. Tr15. Tr16. Tr17t-zp channel h
iO8°Trll, '1'r12. Tr14. Tri8
tlN channel MOS +301 to 303 are power supply terminals. FIG. 2 is a timing chart of FIG. 1.

In FIGS. 1 and 2, the input signals 102 and 103 and the output signal 201 operate as positive logic, and the input signal 105
, 106 and the output signal 202, it operates with negative logic. Therefore, when the clock signal 101 is at a low level, a high level is output as the output signal of the HIOS inverter 3, and the first bus line 4 and second bus line 5 are precharged, discharged, and then When 101 is at high level, the VC signal is received and passed.

That is, when the signal 101 is at a high level, the input compensation signal 10
If both 2 and 103 are at high level, the first bus line 4 becomes low level, and in order to charge the second bus line 5 to Tr15, the second bus line 5 becomes high level and Tr14tl In order to completely discharge the first bus line 4, the first bus line 4 has a low level of 1, and the output signal 201.20:1X becomes a high level and a low level respectively. Further, when the signal 101 is at a high level and the signals 105 and 106 are both at a low level, the signal 104 is at a low level, and the signals 102 and 103 are at a low level.
The same operation is performed when both are at high level.

According to the present invention, since the bus line provided inside the semiconductor integrated circuit can be divided, the load can be completely reduced compared to the conventional bus line, and the time delay of the bus line can be reduced.

Embodiment 911 of the Invention For convenience, a semiconductor integrated circuit having a CMOS bus line has been described, but in reality,
For bus lines of other semiconductor integrated circuits as well, the time delay nt of the signal can be reduced by 1 to 0.

〔Effect of the invention〕

As is clear from the above explanation, is there a problem with the bus line in the semiconductor integrated circuit having the bus line of the present invention? The effect of reducing the load due to division and reducing the time delay of the signal? Obtainable.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a bus line according to an embodiment of the present invention, and FIG.
1, FIG. 3 is a circuit diagram of a conventional bus line, and FIG. 4 is a timing chart shown in FIG. 3. Try Tr13. Tr15. Tr16. Trl? −・
-P channel MOS%Tri, Tr2. Trll, Tr
12. Tr14゜Tr 18--・-N channel MO
S, 1, 2, 3, 11...MOS inverter, 4.14...Precharge system novus line, 5...discharge system bus line, 3
01, 302, 303, 311... Power terminal,
102,103,105,106゜112.113...
-... Input signal, 101, 111... Precharge signal, 201, 202, 211... Output signal % 104... Output signal of inverter 3.

Claims (1)

[Claims] In a bus line provided inside a semiconductor integrated circuit, a first bus line of a precharge type, a discharge MOS transistor of the first bus line, a second bus line of a discharge type, and the second bus line. a pull-up MOS transistor, the first bus line is connected to the gate of the pull-up MOS transistor of the second bus line, and the second bus line is connected to the gate of the pull-up MOS transistor of the second bus line.
A semiconductor integrated circuit, wherein the bus line is connected to a gate of a discharge MOS transistor of the first bus line.