JPS63266940A - Loop type data transmitter - Google Patents

Abstract

PURPOSE:To send data with fidelity by providing a means inserting dummy data to a data signal or eliminating part of data so as to use only one line in duplicated transmission line system using different clock signals. CONSTITUTION:If the data transmission in the duplicated system transmission lines is disabled because of a fault of a transmission line between communication stations 1 and 1B in the duplicated transmission line system, the communication stations at both ends of the transmission line having the fault are used as loopback terminal stations and the transmission lines of the duplicated system are connected as a single transmission line. In this case, the communication station 1 selects an output signal fB of a clock oscillator 21 as a clock and monitors a deviation of the frequencies of the received clock signal fA and the transmission clock signal fB. In case of fA>fB, the communication station 1 masks part of the clock signal fA and sends the data while part of the received data is eliminated. On the other hand, in case of fA<fB, the dummy data is inserted to the sent data and the result is transmitted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a loop-type data transmission device, and in particular, to a loop-type data transmission device that is connected to one of a group of communication stations inserted into two loop transmission paths. The present invention relates to a loop data transmission device suitable for use in a communication station of a communication system that performs staff synchronization communication with other communication networks.

[Conventional technology]

In data communication systems, a method is adopted in which multiple communication stations are connected in a loop through a first transmission path and a second transmission path, and data is sent and received through the duplicated loop transmission path. ing. In this loop data transmission system.

Although it is normally used as an open communication network, interconnection forms with other communication networks are also adopted.

As a connection form between the loop transmission system and other communication networks, as described in Japanese Patent Laid-Open No. 61-70832, the synchronization frequency of the loop transmission system is synchronized with the clock frequency of the other communication network. A system has been proposed in which data is transmitted between another communication network and a loop transmission system.

Regarding data transmission technology between devices that generally operate at different frequencies, staff synchronization technology is known as described in Japanese Patent Application Laid-Open No. 61-125241, and it is used for loop transmission systems and other devices. Data communication with the communication network can be performed using a staff synchronization method.

[Problem that the invention seeks to solve]

When synchronizing the synchronization frequency of a loop transmission system with the clock frequency of another communication network, a dependent synchronization method is used in which one variable frequency oscillator is provided in each communication station of the loop transmission system and the clock frequency of the other communication network is tracked. However, when each communication station reproduces a clock signal using the output signal of an oscillator, the slight frequency deviation of the clock signal reproduced by the oscillator is transmitted to downstream communication stations, and the frequency deviation increases as the number of oscillators increases. There is a problem in that transmission errors due to beat slips occur on the transmission path with other communication networks due to the frequency deviation after looping.

Therefore, it has been proposed to apply staff synchronization to data transmission between other communication networks and the loop transmission system. In the case of this system, as shown in FIG. 2, a communication station 51 including a monitoring device and a communication station 52 including a data transmission device
A to 52E are connected in a loop via transmission paths 53a and 53b, one communication station 52A is connected to a transmission device 54 of another communication network via communication line 56, and communication station 52D is connected to communication line 5.
It connects to a communication terminal 57 via 8. and communication station 52
A~52E1 The communication station 51 includes a transmitter 65A, a receiver 66A, a transmitter 65B, and a receiver 66 as shown in FIG.
Provide B. Further, one communication network 61 is provided, and a clock generator 62 is provided which generates a clock signal having a frequency lower than that of the clock signals of other communication networks. A clock signal 61a based on the output of the clock generator 61 is output to the transmission line 53A, and a clock signal 61a output from the clock generator 61 is output to the transmission line 53b.
A two-output clock signal 62a is output.

Each receiver 66A, 66B receives the communication signal from the transmission path 53a, 53b and converts it into a data signal and a clock signal, and the transmitter 65A, 65B converts the data signal and clock signal into a communication signal and transmits it respectively. The signals are output to paths 53a and 53b. and 1 communication station 51, 52
Any communication station among A to 52E is configured to exchange data with other communication networks through staff synchronization.

That is, by supplying the 211 class clock signal to each of the communication stations 51, 52A to 52E, each station can exchange data with other communication networks through staff synchronization.

By the way, as shown in FIG. 4, when a transmission failure 69 occurs between one communication station 52A and one communication station 52B, one communication station 52A and one communication station 52B are respectively used as loopback terminal stations, and the transmission line 53a is used.

If 53b is used as a single transmission line, transmission line failure 69
Even if this occurs, data can still be exchanged.

However, even if the communication stations 52A and 52B are used as loopback terminal stations, only the clock signal 61a is supplied to one communication station 52A, only the clock signal 62a is supplied to one communication station 52b, and the other communication networks There was a problem that data transmission by staff synchronization became impossible.

An object of the present invention is to provide a loop-type data transmission device that can perform data transmission using staff synchronization between each communication station and another communication network even when a duplicated transmission line is used as a single transmission line. It is about providing.

[Means for solving problems]

In order to achieve the above object, the present invention inserts a plurality of communication stations into a first loop transmission path and a second loop transmission path, and performs staff synchronization between each communication station and another communication network. In a communication system capable of communication using A first transmitter that is inserted into a loop transmission path and converts data signals and clock signals into communication signals and outputs them to the first loop transmission path; a second receiver that receives a communication signal from the station and converts it into a data signal and a clock signal;
a second transmitter that is inserted into the loop transmission path and converts the data signal and clock signal into communication signals and outputs them to the second loop transmission path; a second switching means that disconnects the output side of the first transmitter from the transmission path and connects it to the output side of the first receiver; and disconnects the output side of the first transmitter from the first loop transmission path and connects it to the output side of the second receiver. and second switching means for connecting.

A first clock generator that generates a clock signal with a higher frequency than the clock signal of the other communication network, and a second clock generator that generates a clock signal with a lower frequency than the clock signal of the other communication network. and.

The clock signal of the first receiver output is used in the steady state, and the clock signal of the first receiver output is used in the loopback terminal station. a first clock selection means for selecting one of the clock signals output from the second clock generator as a transmission clock signal; 1st place in the game. a second clock selection means for selecting one of the clock signals output from the second clock generator as a transmission clock signal; and a reception clock signal output from the first receiver and a first clock selection means. a first deviation detection means for detecting a frequency deviation between the output clock signal and the transmission clock signal; and a first deviation detection means for detecting a frequency deviation between the reception clock signal output from the second receiver and the transmission clock signal output from the second clock selection means. and dummy data in the data signal of the first transmitter when the frequency of the transmission clock signal is higher than the frequency of the reception clock signal by the first or second deviation detection means. a first dummy data insertion means for inserting data of the second transmitter when the first or second deviation detection means detects that the frequency of the transmission clock signal is higher than the frequency of the reception clock signal; a second dummy data insertion means for inserting dummy data into the signal;
Or is it determined by the second deviation detection means that the frequency of the transmission clock signal is lower than the frequency of the reception clock signal?

first dummy data removing means for removing dummy data from the data signal of the first receiver when detected;
or second dummy data removal means for removing dummy data from the data signal of the second receiver when the second deviation detection means detects that the frequency of the transmission clock signal is lower than the frequency of the reception clock signal; This constitutes a loop data transmission device including the following.

[Effect]

During normal operation, a communication signal received by the first receiver is converted into a data signal and a clock signal, and the data signal and clock signal are converted into communication signals and transmitted from the first transmitter to the first receiver.
output to the loop transmission line.

Furthermore, the communication signal received by the second receiver is converted into a data signal and a clock signal, and the data signal and clock signal are converted into communication signals and outputted from the second transmitter to the second loop transmission path. , data is transmitted through two transmission paths. Furthermore, data communication is performed between any communication station among the communication stations and the communication network of another system by staff synchronization.

On the other hand, if a failure occurs in one of the duplex transmission lines and data transmission on the duplex transmission line becomes impossible, the communication stations at both ends of the transmission line where the failure has occurred are connected to the loopback terminals. It is used as a station to connect dual system transmission lines as a single transmission line. When the communication station designated as each loopback terminal station outputs a communication signal, the communication station uses a clock generator that generates a clock signal with a frequency different from that of the received clock signal among the clock signals from the first or second clock generator. is selected, and the clock signal from the selected clock generator is output to the transmission path as a transmission clock signal. Further, when the frequency of the transmit clock signal is higher than the frequency of the receive clock signal, dummy data is inserted into the data signal, and conversely, when the frequency of the transmit clock signal is lower than the frequency of the receive clock signal, dummy data is removed from the data signal. . This makes it possible to faithfully transmit data even if the duplicated transmission paths have different clock signals and each transmission path is connected to a single transmission path. Furthermore, since two types of clock signals are supplied to each communication station, each communication station is able to perform data communication through staff synchronization with other communication networks.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, a communication station 1 is inserted into a first loop transmission line 2 and a second loop transmission line 3, and the communication station 1 includes receiving circuits 4 and 15, a demodulation circuit 5. Extraction circuit 6, 17, flag detector 9, 29, 18, 35, dummy data removal circuit 28, 191 frequency comparator 7, 20
, clock selection circuits 12, 22 . clock oscillator 11,
21, dummy data insertion circuit 8, 34, transmission circuit 14゜24, modulator 13, 23, communication LSI 26゜27,
Controller 25, MPU 30. Memory 31, communication L
Data transmission devices including SI32 and the like are used.

Note that the communication station 1 has a circuit for synchronizing staff with other communication networks and a circuit for performing data communication with other communication terminals.

These circuits are omitted.

Receiving circuit 4. Demodulation circuit 5. The clock extraction circuit 6 constitutes a first receiver, and is configured to convert the communication signal from the transmission line 2 into a data signal and a clock signal. That is, the data signal is output from the demodulation circuit 5, and the clock extraction circuit 6
A clock signal fA is output from the clock signal fA. The data signal is supplied to the LSI 26, and the clock signal fA is supplied to the LSI 26 via the dummy data removal circuit 28. And these signals are LSI2
6 and the MPU 30, and the data signal is output to the modulator 13 via the dummy data insertion circuit 8.

The clock signal fA is supplied to the modulator 13 via the clock selection circuit 12, and is output from the transmission circuit 14 to the transmission line 2 as a communication signal. That is, the transmitting circuit 14 and the modulator 13 constitute a first transmitter, which converts a clock signal and a data signal into a communication signal. The clock selection circuit 12 is configured as a first clock selection means, and is configured as a first clock selection means. Either the clock signal from the second clock generator 21 or the clock signal from the clock extraction circuit 6 is selected. That is, during steady state, the clock signal output from the clock extraction circuit 6 is selected as the transmission clock signal, and during the loopback terminal station, one of the clock signals output from the clock generator 11 or the clock generator 21 is selected as the transmission clock signal. You get to choose.

The frequency comparator 7 is configured as a first deviation detection means, and detects the frequency deviation between the reception clock signal output from the clock extraction circuit 6 and the transmission clock signal output from the clock selection circuit 12, and sends the detected output to the LSI 26. It is designed to output to.

The dummy data removal circuit 28 masks a part of the clock signal fA according to a command from the LSI 26, and removes dummy data from the data signal received by the LSI 26. That is, the dummy data removal circuit 28 and the LS
I26 constitutes a first dummy data removal means. The dummy data insertion circuit 8 is a communication LSI 2
Dummy data is inserted into the data signal according to a command from 6. That is, the dummy data insertion circuit 8 is configured as a first dummy data insertion means. Note that the timing for masking a part of the clock signal fA is detected by the output of the flag detector 29, and the timing for inserting dummy data is detected by the flag detector 9.

Receiving circuit 15. Demodulation circuit 16. The clock extraction circuit 17 connects the second receiver to the transmitter circuit 24 . The modulator 23 serves as a second transmitter, the clock selection circuit 22 serves as a second clock selection means, the frequency comparator 2o serves as a second deviation detection means, and the dummy data insertion circuit 34 serves as a second dummy data insertion means. , dummy data removal circuit 19. L5'I27 constitutes second dummy pig removing means.

Also, MPU30. The LSIs 26 and 27 constitute a first switching means that disconnects the input side of the second transmitter from the transmission line 3 and connects it to the output side of the first receiver at the time of loopback terminal station, and also connects the input side of the second transmitter to the output side of the first receiver. The input side of
A second switching means is configured to be separated from the receiver and connected to the output side of the second receiver.

In the above configuration, the communication signal transmitted through the transmission path 2 is transmitted to the receiving circuit 4. Demodulation circuit 5. LSI26. Dummy data insertion circuit 8. Modulator 13. It is transmitted to other communication stations via the transmitter 14. At this time, when the communication station 1 is used as a clock master, the clock signal fA of the clock generator 11 is selected by the clock selection circuit 12, and when the communication station 1 is used as a clock-dependent communication station, it is extracted by the clock extraction circuit 6. clock signal fA
are selected by the clock selection circuit 12, and a communication signal is outputted via the transmission path 2 in accordance with each selected clock signal fA. The communication signal at this time is generated according to the format shown in FIG. That is, it is composed of FLAGI indicating the presence or absence of dummy data, destination communication station address DA, source communication station address SA, area C for commands, etc., data area DA, and error check information storage area FC8. When dummy data is inserted into the data signal, as shown in FIG.
AG2. Dummy DUMMY is inserted.

When data is being transmitted and received via the transmission path 2, the frequency comparator 7 detects a deviation in frequency between the reception clock and the transmission clock.

When the frequencies of the receive clock signal and the transmit clock signal are equal, the signals shown in FIGS. 8(a) and 8(b) are received and outputted via the transmitter circuit 14.

On the other hand, when the received data includes dummy data as shown in FIG. 8(e), the frequency comparator 7 determines that the frequency of the received clock signal is higher than the frequency of the transmitted clock. Detected, the command from the LSI 26 is output to the dummy data removal circuit 28, a part of the clock signal fA output from the clock extraction circuit 6 is masked, and the received clock signal fA as shown in FIG. 8(f) is generated. Selected by the clock selection circuit 12.

As a result, the signals shown in (g) and (h) of FIG. 8 are supplied to the modulator 13. Further, when it is detected that the frequency of the transmitting clock signal is higher than the frequency of the receiving clock signal, dummy data is inserted into the data signal according to a command from the LSI 26. At this time, the modulator 13 includes a dummy data insertion circuit 8. The clock selection circuit 12 supplies signals as shown in (c) and (d) of FIG. Dummy data is inserted to prevent data underruns, and conversely, when the frequency of the transmitting clock signal is lower than the frequency of the receiving clock signal, dummy data is removed to prevent data overruns. , the effective data transmission rate, which is different from the clock rate, appears to be the same everywhere on the loop transmission path.

Note that similar data transmission is performed in the transmission line 3 system as well.

Here, as shown in FIG. 5, communication station 1 and communication station I
A failure occurred in the transmission path between communication station 5 and communication station IB.
When using each as a loopback terminal station, the transmission line 2 is connected to the receiving circuit 4. Demodulation circuit 5. LSI 26, 27, dummy data insertion circuit 34, modulator 23. It is connected to the transmission line 3 via the transmission circuit 24. and clock selection circuit 2
2 selects the clock signal fB from the clock oscillator 21, and the clock selection circuit 12 selects the clock signal fB output from the clock oscillator 21 selected by the clock selection circuit 22. Then, the frequency selector 7 monitors the frequency deviation between the reception clock signal and the transmission clock signal. At this time, since the frequency of the transmission clock signal fB is set to a lower value than the frequency of the transmission clock signal fA, a part of the clock signal fA is masked by a command from the LSI 26, and a part of the received data is removed. The removed data signal is transferred to the communication LSI 26, LSI
27. The signal is supplied to the modulator 33 via the dummy data insertion circuit 34. That is, in the first communication LSI 26, the data signal for the transmission line 2 is converted into a data signal for the transmission line 3, and the converted data signal is supplied to the communication LSI 27. Therefore, even if transmission lines with different clock signals are connected, the clock signal is converted into a clock signal suitable for the transmission line, so data transmission can be performed faithfully.

In one communication station IB, the transmission line 3 is connected to the receiving circuit 15.
Demodulation circuit 16. LSI27. LSI26° data insertion circuit 8. Modulator 13. Processing for connecting to the transmission line 2 via the transmission circuit 3 is performed, and the clock selection circuit 1
2, the clock signal fA of the clock generator 11 output
is selected.

Also, at this time, the clock selection circuit 22 is the clock selection circuit 1.
The clock signal fA selected by 2 is selected.

Then, in the frequency comparator 20, the received clock signal fB
The deviation between the frequency of the transmission clock signal fA and the frequency of the transmission clock signal fA is monitored.

In this case, since the frequency of the transmission clock signal fA is higher than the frequency of the reception clock signal fB, dummy data is inserted into the data signal supplied to the modulator 13 in response to a command from the LSI 27, 26. That is, by inserting dummy data into the transmission signal for transmission through transmission path 3,
Processing is performed to convert it into a data signal for use. For this reason,
Even if a transmission failure occurs between the communication station 1 and the communication station IB, the communication signal based on the clock signal fA is transmitted to the transmission path 2,
A communication signal according to the clock signal fB is transmitted to the transmission path 3.

Furthermore, each communication station 1. Since two types of clock signals fA and fB are supplied to IA and 1B, each communication station can perform data communication with other communication networks through staff synchronization.

In the case of the communication station IA, it acts as an intermediate station, and since the frequencies of the reception clock signal and the transmission clock signal usually match, the reception signal can be output as is as a transmission signal.

〔Effect of the invention〕

According to the present invention, even when two transmission lines are used as one transmission line, clock signals with different frequencies can be supplied to each communication station, so even during the loopback operation period, each communication station and other communication It becomes possible to transmit data between the network and the network using staff synchronization, and data can be transmitted continuously in real time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a communication station showing one embodiment of the present invention, and FIG.
3 is a diagram showing the main part of the conventional example, FIG. 4 is a diagram for explaining the loopback operation in the conventional example, and FIG. 5 is the loopback of the device according to the present invention. 6 is a diagram illustrating an example of the data format of the device according to the present invention; FIG. 6 is a diagram illustrating an example of the data format of the device according to the present invention with dummy data inserted. The figure shown in FIG. 8 is a waveform chart for explaining the operation of the device according to the present invention. 1, IA, IB...communication station, 2, 3...transmission line, 4
゜15...Reception circuit, 5.16...Demodulation circuit, 6,
17... Clock extraction circuit, 7.20... Frequency comparator, 8.34... Dummy data insertion circuit, 11,2
1... Clock oscillator, 12.22... Clock selection circuit. 13.23...Modulator, 14.24...Transmission circuit,
26.27...Communication LS1.28.19...Dummy data removal circuit.

Claims (1)

[Claims] 1. A plurality of communication stations are connected to a first loop transmission path and a second loop transmission path, respectively.
In a communication system that is inserted into the first loop transmission path and allows communication between each communication station and other communication networks by staff synchronization, it is inserted into the first loop transmission path and communicates from other communication stations. a first receiver that communicates signals and converts them into data signals and clock signals; and a first receiver that is inserted into the first loop transmission path and converts the data signals and clock signals into communication signals and sends the signals to the first loop transmission path. a first transmitter that outputs an output; a second receiver that is inserted into a second loop transmission path and receives a communication signal from another communication station and converts it into a data signal and a clock signal; A second transmitter that is inserted into the loop transmission path and converts the data signal and clock signal into communication signals and outputs them to the second loop transmission path; the input side of the first transmitter is separated from the first loop transmission line and connected to the output side of the second receiver; a first clock generator that generates a clock signal with a higher frequency than the clock signal of the other communication network; and a first clock generator that generates the clock signal with a lower frequency than the clock signal of the other communication network. A second clock generator generates a clock signal, and a clock signal of the first receiver output during normal operation is transmitted to the first and second clock generators during a loopback terminal station.
a first clock selection means for selecting one of the clock signals output from the clock generator as a transmission clock signal; 1. second clock selection means for selecting one of the clock signals output from the second clock generator as a transmission clock signal, and a reception clock signal output from the first receiver and the first clock; A first deviation detection means detects a frequency deviation between the transmission clock signal of the selection means and a reception clock signal output from the second receiver, and a frequency deviation between the reception clock signal output from the second receiver and the transmission clock signal output from the second clock selection means. a second deviation detection means, and when it is detected by the first or second deviation detection means that the frequency of the transmission clock signal is higher than the frequency of the reception clock signal, dummy data is stored in the data signal of the first transmitter; a first dummy data insertion means for inserting data of the second transmitter when the first or second deviation detection means detects that the frequency of the transmission clock signal is higher than the frequency of the reception clock signal; when it is detected by the second dummy data insertion means for inserting dummy data into the signal and the first or second deviation detection means that the frequency of the transmission clock signal is lower than the frequency of the reception clock signal; The first dummy data removal means removes dummy data from the data signal of the first receiver, and the first or second deviation detection means detects that the frequency of the transmission clock signal is lower than the frequency of the reception clock signal. a second dummy data removing means for removing dummy data from the data signal of the second receiver when the data signal of the second receiver is detected.