JPS63261790A - Hybrid integrated circuit board - Google Patents

Hybrid integrated circuit board

Info

Publication number
JPS63261790A
JPS63261790A JP9516387A JP9516387A JPS63261790A JP S63261790 A JPS63261790 A JP S63261790A JP 9516387 A JP9516387 A JP 9516387A JP 9516387 A JP9516387 A JP 9516387A JP S63261790 A JPS63261790 A JP S63261790A
Authority
JP
Japan
Prior art keywords
terminal
film
solder
integrated circuit
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9516387A
Other languages
Japanese (ja)
Inventor
伸次 鈴木
戸崎 博己
伊藤 光子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9516387A priority Critical patent/JPS63261790A/en
Publication of JPS63261790A publication Critical patent/JPS63261790A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、銀を主体とする厚膜導体で部品のはんだ接続
用端子を形成した混成集積回路基板に係り、特に接続強
度の向上ζこ好適な端子構造に関する0 〔従来の技術〕 混成集積回路では、IC,LSIを含ムパッケージ素子
、チップコンデンサ、抵抗チップ等の個別部品および外
部入出力用クリップリード等がPb −Sn系はんだの
り70−やディップによって基板上の端子に接続される
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a hybrid integrated circuit board in which terminals for solder connection of components are formed with a thick film conductor mainly composed of silver, and particularly relates to a hybrid integrated circuit board in which terminals for solder connection of components are formed with a thick film conductor mainly composed of silver. [Prior art] In hybrid integrated circuits, individual components such as ICs and LSIs, package elements such as chip capacitors, resistor chips, clip leads for external input/output, etc. are soldered with Pb-Sn solder paste 70 It is connected to the terminal on the board by - or dip.

次に、従来の端子構造を第5図、第4図を用いて説明す
る。同図において、端子2はアルミナ。
Next, a conventional terminal structure will be explained using FIGS. 5 and 4. In the figure, terminal 2 is alumina.

ガラスセラミックス等の絶縁性基板1上に回路配線5や
抵抗体(図示せず)とともに産膜印刷技術により形成さ
れ、通常この配意や抵抗体は機械的保護および耐環境性
向上のためガラス膜4で被覆される。一方、端子に関し
ては、多ピン素子用の端子列や入出力端子列の端子間が
はんだlこよりブリッジ短絡されることを防ぐため、図
示のようにガラス膜4が当該端子間に端子2と分離され
た状態で形成される。上記の端子や配線の導体材料とし
ては、多くの場合、銀を主体とするAg−Pd系。
It is formed by film printing technology on an insulating substrate 1 made of glass ceramic or the like along with circuit wiring 5 and a resistor (not shown), and usually the resistor is coated with a glass film for mechanical protection and to improve environmental resistance. 4. On the other hand, regarding the terminals, in order to prevent bridge short circuits between the terminals of the terminal row for multi-pin elements and the input/output terminal row due to solder, a glass film 4 is separated from the terminal 2 between the terminals as shown in the figure. It is formed in a state where In most cases, the conductive material for the terminals and wiring mentioned above is Ag-Pd based mainly on silver.

Ag−Pt系の材料が使用されている。これらに関連す
る文献としては、例えば「厚膜多層回路基板;電子材料
、1985年5月、 pp54〜59」がある。
Ag-Pt based materials are used. A related literature includes, for example, "Thick Film Multilayer Circuit Board; Electronic Materials, May 1985, pp. 54-59."

この混成集積回路基板における部品のはんだ接続強度の
向上に関しては、端子用導体材料、はんだ材料、はんだ
接続部形状等に種々の改良が加えられているが、特に接
続強度の経時低下は、基本的にはPb−8n系はんだ中
のSnがはんだ接合時およびその後の熱履歴により端子
膜中に拡散し、Ag s Sn合金を形成するためであ
り、Srl拡散が端子一基板界面まで達したときは、著
しく接続強度が低下すると言われている。これに関する
文献としては、例えばrAg/Ptメタライズの接着強
度劣化解析;第1回マイクロエレクトロニクスシンポジ
ウム予稿集、1985年7月、 pp61〜63」があ
る。
In order to improve the solder connection strength of components on hybrid integrated circuit boards, various improvements have been made to terminal conductor materials, solder materials, solder connection shapes, etc., but in particular, the decline in connection strength over time is basically This is because Sn in the Pb-8n solder diffuses into the terminal film during soldering and the subsequent thermal history, forming an Ag s Sn alloy. When Srl diffusion reaches the terminal-substrate interface, , it is said that the connection strength decreases significantly. A related literature includes, for example, "Analysis of adhesive strength deterioration of rAg/Pt metallization; Proceedings of the 1st Microelectronics Symposium, July 1985, pp. 61-63".

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術による混成乗積回路基板では、端子にはん
だ接続した部品の接続強度が、高温での放置や温度サイ
クルによって短時間に低下し、部品接続の信頼性が乏し
いという問題点があった。
The conventional hybrid multiplication circuit board described above has a problem in that the connection strength of the components soldered to the terminals decreases in a short period of time due to being left at high temperatures or through temperature cycling, resulting in poor reliability of component connections.

Ag系端子膜にPb−8n系はんだを用いて部品を接続
した場合、前記の理由により接続強度の経時低下は避は
碓いものであるが、著しい強度低下に至るまでの時間が
、端子膜厚方向lこSnが完全に拡散するまでの時間よ
りも短いことから、本発明者らは、接続強度低下の要因
の一つおして端子外周側面からのEn拡散があることを
見出した。これは、端子膜の構成に起因するものである
。すなわち、第3図、第4図に示した従来の端子構造で
は、はんだが端子の上表面だけでなく、その外周側面に
も付着する。このため、はんだ接合時に当該外周側面の
底部の端子一基板界面には既に91面から拡散するSn
によりAg5in合金が形成され、端子一基板界面に接
続強度の低い部分が生じる。そして、高温環境下でのS
nの拡散の加速や温就サイクルでの基板、端子膜、はん
だの熱膨張差による応力集中などのため、この接続強度
の低い部分から端子膜の剥がれが生じ、はんだ接続用端
子の接続強度を急速に低下させるものと考えられる9、
本発明の目的は、上記したA(系端子膜の外周側面から
のSn拡散を防止することにより、端子一基板界面の接
続強度を高め、部品接続の信頼性の高い端子構造を備え
た混成集積回路基板を提供することにある。
When parts are connected using Pb-8n solder to an Ag-based terminal film, it is inevitable that the connection strength will decrease over time due to the reasons mentioned above. Since the time taken for Sn to completely diffuse in the direction l is shorter, the present inventors have found that one of the causes of the decrease in connection strength is En diffusion from the outer peripheral side surface of the terminal. This is due to the structure of the terminal film. That is, in the conventional terminal structure shown in FIGS. 3 and 4, solder adheres not only to the upper surface of the terminal but also to the outer peripheral side surface thereof. Therefore, during soldering, Sn that has already diffused from the 91st surface is present at the terminal-substrate interface at the bottom of the outer peripheral side surface.
As a result, an Ag5in alloy is formed, and a portion with low connection strength is created at the terminal-substrate interface. And S under high temperature environment
Due to accelerated diffusion of n and stress concentration due to thermal expansion differences between the board, terminal film, and solder during the heating cycle, the terminal film peels off from the areas with low connection strength, reducing the connection strength of the solder connection terminal. 9, which is considered to cause a rapid decline.
The object of the present invention is to prevent the Sn diffusion from the outer peripheral side of the A (type terminal film) described above, thereby increasing the connection strength at the terminal-to-substrate interface, and providing a hybrid integrated circuit with a terminal structure that provides highly reliable component connection. Our goal is to provide circuit boards.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、銀を主体とする厚膜導体で部品のはんだ接
続用端子を形成した混成集積回路基板において、上記端
子の外周辺部をガラス膜で被覆することにより達成され
る。
The above object is achieved by covering the outer periphery of the terminal with a glass film in a hybrid integrated circuit board in which terminals for solder connection of components are formed with a thick film conductor mainly composed of silver.

〔作用〕[Effect]

上記のように構成された本発明の混成集積回路基板にお
いては、端子と部品を接続するためのはんだは、端子の
ガラス膜で行われていない上表面にのみ付着する。した
がって、はんだ中のSnは端子膜の上表面のみから拡散
するため、はんだ接合時(こ端子一基板界面の接続強度
を低下させる界面部でのAg3Sn合金の生成がない、
・また、この端子構造では、端子の外周辺部がカラス膜
と基板で挾み込まれ押えられた状態にあるため、端子膜
の引き剥がしに対する抗力も高まり、両々相まってはん
だ接続した端子の接続強Kを向上させることができる。
In the hybrid integrated circuit board of the present invention configured as described above, the solder for connecting the terminals and the components adheres only to the upper surface of the terminal, which is not covered by the glass film. Therefore, since Sn in the solder diffuses only from the upper surface of the terminal film, there is no formation of Ag3Sn alloy at the interface that reduces the connection strength of the terminal-substrate interface during solder bonding.
・In addition, with this terminal structure, the outer periphery of the terminal is sandwiched and pressed between the glass film and the board, which increases the resistance to peeling off the terminal film, and these combine to reduce the connection strength of the soldered terminal. K can be improved.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図および第2図を用いて
説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

第1囚、第2図において、アルミナ焼結基板1上に、A
g−Pd系導電ペーストを周知の厚膜印刷技術により塗
布し、120°Cで乾燥後、8500C−10分で焼成
することにより、膜淳10μm 、 1.5mx’の端
子2と当該端子に至る回路配線3を形成した。回路構成
に応じて厚膜クロスオーバ、厚膜抵抗体(図示せず)を
印刷、焼成により形成した後、550’C−10分の焼
成でガラス膜を形成するアルミノホウケイ酸塩系ガラス
ペーストを用い、厚膜配線3.厚膜抵抗体とともに端子
2の外牌辺部を覆って印刷、焼成し、ガラス膜4で厚膜
の被&を行なった。端子に関しては、はんだ接続のため
上衣面lこ1.5−、+G40の露田部を残し、外周辺
部がガラス膜4と基板1で挾み込まれた状態として、カ
ラス膜4をはんだ接続強度の向上と入出力端子列の端子
間のはんだブリッジ防止に兼用した。この端子21こ外
部入出力用クリップリードを装湿し、Ag2%含有Pb
−8n共晶はんだ浴中に250°C−5秒ディップして
接続した。
In the first case and FIG. 2, on the alumina sintered substrate 1, A
A g-Pd based conductive paste is applied using a well-known thick film printing technique, dried at 120°C, and then fired at 8500C for 10 minutes to form a terminal 2 with a film thickness of 10 μm and a size of 1.5 m x 1. Circuit wiring 3 was formed. After forming thick film crossovers and thick film resistors (not shown) according to the circuit configuration by printing and firing, an aluminoborosilicate glass paste that forms a glass film is fired at 550'C for 10 minutes. Thick film wiring 3. The outer edge of the terminal 2 was printed and fired together with the thick film resistor, and the thick film was covered with the glass film 4. Regarding the terminal, leave an exposed area of 1.5-, +G40 on the upper surface for solder connection, and assume that the outer periphery is sandwiched between the glass film 4 and the substrate 1. It also serves to improve the performance and prevent solder bridging between terminals in the input/output terminal row. This terminal 21 external input/output clip lead was humidified and Pb containing 2% Ag was used.
Connections were made by dipping in a -8N eutectic solder bath at 250°C for 5 seconds.

はんだ接続強度は、クリップリードのリード部分を基板
に対して垂直に折曲げ、これを引き剥がすビール法にて
測定した。才だ、接続強度の経時低下は、はんだ接続し
たクリップリードを150’C1000  時間放置後
、測定した。
The solder connection strength was measured by the Beer method, in which the lead portion of the clip lead was bent perpendicularly to the board and then peeled off. The decline in connection strength over time was measured after the soldered clip leads were left for 150'C1000 hours.

なお、比較としての従来例では、膜厚10μm。In addition, in the conventional example for comparison, the film thickness is 10 μm.

1.5m4に端子を形成し、ガラス膜は第3図および第
4図に示すように端子の配線部と端子間の基板面を被覆
する構成とした。はんだ接続、接続強度の測定は本発明
の実施例と同様に行なった。
A terminal was formed in an area of 1.5 m4, and the glass film was configured to cover the wiring part of the terminal and the substrate surface between the terminals as shown in FIGS. 3 and 4. Measurement of solder connection and connection strength was carried out in the same manner as in the examples of the present invention.

第1表に実施例と従来例の初期接続強度および1500
C−1000時間後の経時接続強度を比較して示す○ 第1表 衣から明らかなようζこ、本発明の実施例によれば、従
来例に比べてはんだ接続部の面積が小さい(従来例の0
.75倍)にも拘わらず、初期接続強度では1゜55倍
の強度が得られた。また、150°C−1000時間後
の経時接続強度でも167倍と、従来の端子構造lこ比
べてはんだ接続部Kを向上させることができた4、 なお、本発明は前記のような特定の材料および端子膜の
形成方法を用いた実施例に限定されるものではなく、基
板の材料としてはアルミナのほか、各種ガラスセラミッ
クス、ムライト・AlN、 SiC等の使用が可能であ
り、基板が焼結体でなくグリーンシートであってもよい
。また、端子膜がこれらの基板上に直接形成される場合
だけに限らず、基板と端子の層間にいわゆるガラス質等
の絶縁膜が介在する場合も本発明の実施の対象とするこ
とができる。
Table 1 shows the initial connection strength and 1500 of the embodiment and conventional example.
C- Comparison of connection strength over time after 1000 hours ○ As is clear from the first cover, ζ According to the embodiment of the present invention, the area of the solder joint is smaller than that of the conventional example 0 of
.. 75 times), the initial connection strength was 1°55 times as strong. Furthermore, the connection strength over time after 1000 hours at 150°C was 167 times higher than that of the conventional terminal structure. The material and the method for forming the terminal film are not limited to the embodiments, and the substrate material may be alumina, various glass ceramics, mullite/AlN, SiC, etc., and the substrate may be sintered. It may be a green sheet instead of a body. Furthermore, the present invention is not limited to cases in which the terminal film is directly formed on these substrates, but also in cases where an insulating film such as a so-called glass material is interposed between the layers of the substrate and the terminal.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、銀を主体とする厚膜導体で端子を形成
した混成集積回路基板において、部品のはんだ接続強度
に大きな影響を及ぼす端子膜の外周部の引き剥がしに対
する強度を増大させることができるので、部品接続の信
頼性を一層向上できる効果がある。しかも、本発明は基
板上の被覆ガラス膜を利用して端子膜の外周辺部を被覆
することで、特別な材料や工程の追加を喪せずに容易に
実施できるものである。
According to the present invention, in a hybrid integrated circuit board in which terminals are formed with a thick film conductor mainly composed of silver, it is possible to increase the strength against peeling off of the outer peripheral portion of the terminal film, which has a large effect on the solder connection strength of components. This has the effect of further improving the reliability of component connections. Moreover, the present invention can be easily implemented without adding any special materials or processes by covering the outer periphery of the terminal film using the covering glass film on the substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す端子部の平面図、第2
図は第1図のA −A’断面図、第3図は従来例を示す
端子部の平面図、第4図は第3図のB −B’断面図で
ある。 符号の説明 1・・・基板      2・・・端子6・・・回路配
線    4・・・被覆ガラス膜代理人 弁理士 小 
川 勝 男(6 (J  、”’
FIG. 1 is a plan view of a terminal section showing one embodiment of the present invention, and FIG.
The figures are a cross-sectional view taken along the line A-A' in FIG. 1, FIG. 3 is a plan view of a terminal portion showing a conventional example, and FIG. 4 is a cross-sectional view taken along the line B-B' in FIG. Explanation of symbols 1... Board 2... Terminal 6... Circuit wiring 4... Covered glass membrane agent Patent attorney Small
Katsuo Kawa (6 (J, "'

Claims (1)

【特許請求の範囲】[Claims] 1、銀を主体とする厚膜導体で部品のはんだ接続用端子
を形成した混成集積回路基板において、上記端子の外周
辺部をガラス膜で被覆したことを特徴とする混成集積回
路基板。
1. A hybrid integrated circuit board in which terminals for solder connection of components are formed with a thick film conductor mainly composed of silver, characterized in that the outer periphery of the terminal is covered with a glass film.
JP9516387A 1987-04-20 1987-04-20 Hybrid integrated circuit board Pending JPS63261790A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9516387A JPS63261790A (en) 1987-04-20 1987-04-20 Hybrid integrated circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9516387A JPS63261790A (en) 1987-04-20 1987-04-20 Hybrid integrated circuit board

Publications (1)

Publication Number Publication Date
JPS63261790A true JPS63261790A (en) 1988-10-28

Family

ID=14130105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9516387A Pending JPS63261790A (en) 1987-04-20 1987-04-20 Hybrid integrated circuit board

Country Status (1)

Country Link
JP (1) JPS63261790A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2017199712A1 (en) * 2016-05-16 2019-02-14 株式会社村田製作所 Ceramic electronic components

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2017199712A1 (en) * 2016-05-16 2019-02-14 株式会社村田製作所 Ceramic electronic components

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