JPS63260289A - Video scramble descramble device - Google Patents

Abstract

PURPOSE:To improve the security against illegal descrambling and to reduce the effect on a voice signal by applying AM modulation to a transmission voice signal independently of the period subject to scrambling and no scrambling. CONSTITUTION:A control circuit 20 generates a prescribed timing pulse during the period of a horizontal synchronizing signal to be scrambled and the horizontal synchronizing signal not to be scrambled. A voice IFAM modulation circuit 18 applies AM modulation to a transmission voice signal by using a pulse from the control circuit 20. The output is given to an RF modulator 16 and mixed with a video signal subject to scrambling processing and converted into an RF frequency.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a video scrambling/descrambling device that performs scrambling and descrambling using synchronization suppression for paid broadcasting in a subscriber broadcasting system.
In particular, since the decoder side descrambles the RF scrambled signal that is a composite of video and audio, it prevents the audio signal from being subjected to AM modulation and degrades the S/N ratio, and provides a high degree of secrecy against unauthorized descrambling. The present invention relates to a video scrambling/descrambling device that has the following characteristics.

(Prior Art) In subscriber broadcasting systems such as OATV broadcasting, in order to charge for paid broadcasting, transmitted information is scrambled so that only subscribers who are authorized to receive the broadcast can receive correct information. There is. The broadcasting station superimposes decoding data for unscrambling on the scrambled pay signal so that the subscriber can receive it, and encrypts and transmits the signal.

An example of a scrambling method is a synchronous suppress scrambling method in which the horizontal synchronizing signal of an RF frequency video signal is suppressed completely or randomly.

The scramble (encoder) side and descramble (decoder) side of a system that uses such a synchronization suppression method
The side configuration is shown in FIGS. 6 and 7.

FIG. 6 shows the encoder side, where the baseband video signal and audio signal are sent to separate IF modulators 101 and 1, respectively.
02 into a signal with a predetermined intermediate (IF>frequency).The video signal from the IF modulator 101 is supplied to the RF modulator 105 via a synchronization suppress circuit 103 that suppresses the signal in the horizontal synchronization signal period. A scramble control signal b (suppress pulse) from the scramble control circuit 104 is applied to the synchronization suppress circuit 103, and the video signal in the horizontal synchronization signal period is suppressed at the pulse timing of this signal. The audio signal from 102 is supplied to the audio IFAM modulator 106, AM-modulated by a signal d (scramble timing signal) whose timing is advanced by a predetermined amount of time from the scramble control signal, and then supplied to the RF modulator 105. RF
The modulator 105 converts the video signal and the audio signal into predetermined RF frequencies, and outputs the combined image transmission signal to the terminal 107. The signal from terminal 107 is transmitted to the decoder side via a transmission path.

FIG. 7 shows the configuration of the decoder side, where the scrambled video signal from the transmission path enters the converter tuner 108 and is received, becoming a received signal of a predetermined IF frequency. This I
The descrambled video signal a' is synchronously stretched by the F low signal and the descramble control signal C' (stretch pulse) from the descramble control circuit 110, and is led to the output terminal 111. Descramble control circuit 1
10 uses the signal d' from the audio AM detector 112 that performs AM detection of the IF low signal from the converter tuner 108 as a descrambling control signal C' (stretch pulse) to the synchronous stretch circuit 18. terminal 1
The signal from 11 is adapted to be supplied to the RF input of the TV receiver.

FIG. 8 is a time chart showing operations on the encoder side and the decoder side, in which (a) is a scrambled video signal that has been synchronously suppressed, (b) is a scramble control signal, and (C) is a scrambled video signal that has been synchronously suppressed.
is audio IFAMI! 1111106, (d) is a scramble timing signal superimposed on the transmission audio signal, (a)' is a descrambled video signal, and (b) is a received audio signal.

(C)' is a descrambling control signal, and (d) - is a scrambling timing signal.

As can be seen from this time chart, the video signal is suppressed during the pulse period TS of the scramble control signal corresponding to the horizontal synchronization signal period of the video signal. In order to stretch the signal in the suppressed horizontal synchronization signal period to its original level, a signal (d
) is sent superimposed on the audio signal. On the decoder side,
This superimposed signal is subjected to AM detection to obtain a descrambling timing signal (d)-, and a descrambling control signal (C)', which is the same as the scrambling control signal (b), is reproduced. This allows correct descrambling to be performed. In this case, on the encoder side, the timing at which the scramble timing signal d is superimposed on the audio signal is advanced by a predetermined time T with respect to the timing at which the video signal is scrambled. This takes into account the delay t due to audio AM detection in each decoder device. On the decoder side, the descrambling timing signal d' having various delay times t is delayed by T-t to become the descrambling control signal C'. As a result, a stretch pulse ps is generated during the synchronization suppression period TS- of the received video signal.

According to the above-described scrambling method, the audio signal stretched together with the video signal has irregularities Pi caused by the delay in AM detection, as shown in the waveform of FIG. 8(b).
, P2 are formed. If all synchronization suppression is performed, the period of the uneven portion becomes a horizontal period and does not extend to the audible range, but if scrambled at random timing to increase security, the uneven portion P1, There is a problem in that P2 spreads into the audible range and the SN is lowered due to buzz interference due to intercarrier detection, resulting in deterioration of sound quality.

Furthermore, this type of scrambling method has the disadvantage that the random timing of scrambling is superimposed on the audio signal, making it easy to perform illegal descrambling. Therefore, the scrambling timing is not superimposed on the audio signal,
There is also a method of superimposing it on the vertical retrace period as data for decoding the scramble that indicates the initial state of the random pattern, but in this case, the encoder does not suppress the audio signal, so the decoder uses the stretch pulse for descrambling. This has the disadvantage that the audio signal is stretched and the degree of audio signal deterioration increases.

(Problems to be Solved by the Invention) The scramble/descramble devices shown in FIGS. 6 and 7 have the problem of low security as a communication system because the descrambling timing is directly superimposed on the audio signal. be.

Therefore, if the vertical retrace interval is used instead of superimposing the audio signal, security will be increased, but on the decoder side, the RF multiplied signal that is a composite of video and audio will be descrambled, so the audio signal will be the stretch control pulse. A by
There was a problem in that it received M[l and was degraded.

In view of the above problems, the present invention aims to provide a video scrambling/descrambling device that has high security against unauthorized descrambling and has little effect on audio signals.

[Structure of the Invention] (Means for Solving the Problems) This invention scrambles the horizontal synchronizing signal of a video signal with a random number, and uses data for decoding the scramble as the initial value of the random number during the vertical blanking period of the video signal. , or video scramble/transmission using a data channel.
In the descrambling device, the encoder side includes means for generating pulses at predetermined timings within the periods of the scrambled horizontal synchronization signal and the unscrambled horizontal synchronization signal, and the transmission audio signal is generated using the pulses from the pulse generation means. AM modulation means and frequency conversion means for mixing the output of this means with a scrambled video signal and converting it into an RF frequency are provided, and the decoder side includes a descrambler that is reproduced based on the scramble decoding data. It is characterized in that the RF multiplied signal, which is a composite of video and audio signals, is descrambled using a timing pulse.

(Operation) According to the present invention, the transmitted audio signal is subjected to AM modulation regardless of whether scrambling is performed or not. Therefore, when these AM modulation sections undergo processing on the decoder side, they become horizontally periodic AM components and do not spread into the audible range. Furthermore, since the AM modulation during the scrambling period is performed after the horizontal synchronizing signal period, a person who stealth viewing cannot know the timing of scrambling until after the horizontal synchronizing signal period has elapsed. Therefore, unauthorized descrambling from the audio signal becomes impossible.

(Example) Hereinafter, the present invention will be explained with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of the encoder side of the video scrambling/descrambling apparatus according to the present invention.

In FIG. 1, the area within the dotted line is a scramble processing unit 12, which determines the channel frequency of the baseband video signal and audio signal using the transmission control signal 11b from the center CPU unit 11, and sends the baseband video signal and audio signal to the video channel as a pay broadcast signal. It is transmitting. Further, the center CPU section 11 transmits reception contract information, scramble inhibit information (a signal indicating pay broadcasting), etc. to the data channel via the interface circuit 23 and the FSK modulator 24.

A baseband video signal is supplied from, for example, a VTR, and this signal is supplied to a PIF video suppressor circuit 15 via a data superimposition circuit 13 and a modulator 14.Data The superimposition circuit 13 superimposes scramble decoding data on the vertical retrace period of the baseband video signal, and the PIF video suppression circuit 15
Outputs a scrambled video signal in which the horizontal synchronization signal is suppressed at random timing. The video signal with the decoding data superimposed and scrambled in this way is
The signal is guided to an RF modulator 16, the transmission frequency of which is controlled by a transmission control signal 11b from the center CPU 11, and is sent to a video channel as a scrambled transmission video signal.

The data superimposition circuit 13. PIF video suppression circuit 15
are supplied with scramble decoding data 220, a superimposed timing pulse 20b, and a scramble control signal 20a from the control circuit 20, respectively. The control circuit 2G is
Vertical and horizontal synchronization signals from the baseband video signal 19
It is operated by each open signal from the synchronization separation circuit 19 that separates H, 19V, and the system clock, and decode data 221, superimposition pulse 20b, and scramble control signal 2.
This is a timing signal generation circuit that generates an audio stretch signal 20c and an audio suppress signal 20d for audio signals, which will be described later. The control circuit 20 is controlled by a scramble inhibit signal 11a from the center CPU section 11 to determine whether or not to perform the scramble control operation.

Next, the baseband audio signal is input to the audio IFAM modulation circuit 18 via the IF modulator 17.

This audio IFAM modulation circuit 18 receives an audio stretch signal 20 from the control circuit 20 via a waveform shaping circuit 21.
A C1 audio suppression signal 20d is supplied. From the waveform shaping circuit 21 to the audio I FAM modulator 18
The signal 21a that is input to the
0d combined signal.

The control circuit 20, as shown in FIG.
Counter 5 that counts the system clock by 9H
1. A counter 52 that counts the system clock using a vertical synchronization signal of 19V. A timing signal generator 53. generates various timing signals from the outputs from these counters 51, 52. A circuit section (55, 56, 58) for generating the scramble control signal 20a.

A circuit section that forms signals for modulating and controlling audio signals (
49, 54), and a circuit section (51) for encrypting the scramble decoding data.

The circuit section for generating the scrambled 1i11tl signal 20a is generated by logically converting the output 56a of the random value generator 56, which generates a random number signal using the initial value generated by the initial value generator 58, using the Nant gate 55.

In addition to the random number output 56a, the Nant gate 55 receives a scramble inhibit signal 11a and a timing signal 53a for the horizontal synchronization signal period. On the other hand, the audio suppress signal 20d is formed by an AND gate 54, and the AND gate 54 receives, in addition to the random number output 56a, a scramble inhibit signal 11a and a timing signal 53b. Here, the signal @53b from the timing signal generator 53 is a signal that exhibits a pulse in the latter half of the horizontal synchronization signal period. The audio stretch signal 20c is also generated by a Nantes gate 49. This Nantes gate 49 has a random number output of 5
6a, a timing signal 53b, and a scramble inhibit signal 11a are input.

Note that the initial value generated from the initial value generator 58, ie.

The scramble decoding data is encrypted by an encoder 57 composed of a ROM or the like and superimposed on the video signal. Further, a signal 53c supplied from the timing signal generator 53 to the random value generator is a shift drive pulse of a random number signal.

Next, the configuration of the decoder device of this embodiment will be explained with reference to FIG. 3.

In FIG. 3, the reception contract information and scramble inhibit information from the data channel are sent to the FSK demodulator 26.
．． The information is input to the CPLJ section 28 via the interface circuit 27, and the 020 section 28 inputs the channel selection control signal 28b and scramble decoding data 28a to the descramble processing section 25 based on this information.

The descrambling processing unit 25 converts the scrambled transmission video signal transmitted through the video channel into a 020 part 28.
The converter tuner 29, which performs a tuning operation in response to the authorized tuning control signal 28b, receives the signal from the converter tuner 29, and inputs its output to the stretching circuit 30. stretch circuit 3
0 is the descrambling control signal 34 from the control circuit 34
a, a video signal in which the suppressed horizontal synchronization signal is stretched is output. The RF video signal thus descrambled is received and displayed by a TV receiver.

Further, the output of the converter tuner 29 is transmitted to the video detection circuit 3.
1, the video is detected, and the video detection output is sent to the sync separation circuit 32. and a data separation circuit 33.

The control circuit 34 generates a pulse (data separation pulse) 34b corresponding to the period in which the scramble decoding data is superimposed.
is supplied to the data separation circuit 33. As a result, the data separation circuit 33 extracts the scramble decoding data (encrypted initial value data) 33a superimposed on the vertical retrace period. The decoding data 33a outputted from the data separation circuit 33 is decoded by the 020 unit 28 and outputted as the same initial value data 28a as on the encoder side. Control circuit 34
creates a descrambling control signal 34a using this initial value data 28a, the horizontal synchronizing signal 322 from the synchronization separation circuit 32, and the vertical synchronizing signal 32V.

FIG. 4 shows details of the control circuit 34, and the portion surrounded by a dashed line is the control circuit. In this way, the control circuit 34 on the decoder side also controls the horizontal synchronization signal 32 in the same way as the encoder side.
Counter 5 that counts the system clock by H
9, a circuit 60 that counts the system clock at intervals of the vertical synchronization signal @ 32V, and a timing signal generator 61 that generates various timing signals from the outputs of these counters 59 and 60, regenerating the scramble control signal 34a. It consists of two parts.

The circuit section that reproduces the descrambling control signal 34a is C.
Consisting of a random value generator 63 to which initial value data 28a from the PLI unit 28 is supplied, and an AND gate 62 that outputs the AND of the output 63a of this random value generator 63 and the output of the timing signal generator 61. The logical product output of the AND gate 62 is the descramble control signal 34a.
The signal is supplied to the stretch circuit 30 as a signal. however,
The AND gate 62 also receives a scramble inhibit signal 28'a from the 020 unit 28. The signal 61a from the timing signal generator 61 is a signal that exhibits a pulse during the horizontal synchronization signal period. The signal 61 applied to value generator 63 is a random value shift output drive pulse.

The present embodiment is configured as described above, and the operations on the encoder side and decoder side will be explained first.

When the encoder side baseband video signal enters the data superimposition circuit 13, a data superimposition timing pulse 20b is generated during a predetermined horizontal scanning period in the vertical retrace period, and the decryption data 22 from the control circuit 20 is generated during the same period. superimposed on The video signal on which the scramble decoding data is superimposed is converted into an IF frequency and supplied to the PIF video suppressor circuit 15. Random value generator 5 in the υ1t11 circuit 20
The random number signal 56a generated from 6 is a signal whose pulse width changes randomly in units of -horizontal scanning period, and the AND gate 55 performs a scramble operation which is the NAND of this signal 56a and the horizontal synchronization signal period pulse 53a. The control signal 20a is supplied to the PIF video suppressor circuit 15 and the IF
Suppression is performed on the signal during the horizontal synchronization signal period in the frequency video signal. As a result, the signal during the horizontal synchronization signal period of the video signal is suppressed at random timing.

On the other hand, the baseband audio signal is converted into an IF frequency and then subjected to AM modulation in the audio I FAM modulation circuit 18 using the audio υ control signal 21a from the waveform shaping circuit 21. The audio control signal 21a exhibits an audio suppress signal 20d generated by the control circuit 20 during a synchronization suppress period (horizontal synchronizing signal period in which scrambling is performed), and presents an audio stretch signal 20c in a horizontal synchronizing signal period in which scrambling is not performed.

However, each signal 20C, 20d occurs in the latter half of the horizontal synchronization signal period. As a result, the IF audio signal is suppressed by the pulse of the audio suppress signal 20d in the latter half of the horizontal synchronizing signal period in which scrambling is performed, and is stretched in the latter half of the horizontal synchronizing signal period in which scrambling is not performed.

The time charts shown in FIGS. 5(a) to 5(d) show the operation of the encoder, in which (a) shows the scrambled video signal, (b) shows the scrambled control signal 20a,
(C) is a transmitted audio signal, and (d) is an audio control signal.

In this way, on the encoder side, the scramble synchronization signal 1
In the latter half of 11ffiTs, an audio suppress pulse P3 is generated to form a suppress portion S1 in the transmitted audio signal (C), and in the latter half of the non-scrambled synchronization period TNS, an audio stretch pulse P4 is generated to suppress the transmitted audio signal (C). ) is formed with a stretch portion S2. Then, the audio signal having such waveform portions 81 and 82 is transmitted to the decoder side together with the scrambled video signal.

On the L unit l1 decoder side, FSK data (reception contract information, scramble input information) from the center CPU section 11
This authorizes the decoding of the encrypted initial value data to be transmitted, and sets the reception frequency of the pay broadcast channel to the converter tuner 29. This allows converter tuner 29 to receive the scrambled signal.

I obtained by being received by the converter tuner 29
The F-fold signal is a composite signal of a video signal and an audio signal at the timings shown in FIGS. 5(a) and 5(C). Therefore, the stretch circuit 30 generates a descrambling control signal 34a for the video signal and audio signal at the timings (a) and (c).

Now, in the scrambling period TS, the descrambling control signal 34a generates a stretch pulse, so
The audio signal in the section corresponding to the same period TS is stretched. Therefore, in the audio signal of the period TS, the signal of the period not suppressed on the encoder side becomes a stretched waveform, and the signal of the suppress section S1 becomes a normal level. or,
During the non-scramble period T)48, the descrambling control signal 34a does not exhibit a stretch pulse, so the audio signal corresponding to the same period TNS has a waveform in which the stretch portion S2 remains as is.

FIGS. 5(e) to ((+) are time charts showing the above operations, and (e) is a descrambled video signal.

(f) indicates the received audio signal (the audio signal that has passed through the stretch circuit 30), ((+) indicates the descrambling control signal, respectively. As shown in the signal in FIG. 5(f), during the scramble period TS on the encoder side, In the audio signal of the corresponding period TS', a stretch section S3 is formed in which a normal level signal is stretched, and a suppressed section S1 suppressed on the encoder side is restored to the normal level.

Also, a period T corresponding to the non-scrambled period TNS
Since the audio signal of NS' is neither stretched nor suppressed, the stretch section S2 remains as it is and becomes the stretch section S4.

In this way, the audio signal after descrambling is shown in Figure 5(f).
With a waveform like this, the components generated by each stretch section S3 and S4 are centered on the horizontal frequency component and do not spread to the audible range, so noise is generated less than when AM modulation is performed at random timing. can be reduced and the sound quality improved.

Also, since the stretch portion S3.84 is narrowed,
The level of harmonics resulting from this becomes smaller than before.

Furthermore, in this embodiment, a person attempting to eavesdrop on the audio signal can detect the suppressed waveform portion P3. P4 is detected as timing information for decoding. However, the suppressed waveform portion P4 is a normal synchronization signal period, and if this is stretched, the normal synchronization signal will be stretched and the synchronization will be disrupted. Also, even if stretching is performed in S3, the horizontal synchronization signal period has already passed, so normal synchronization stretching is as follows.

This cannot be done and the synchronization will be disrupted.

In this way, in this embodiment, even if a signal related to a timing signal for descrambling is superimposed on an audio signal, the security will not be degraded, and in fact, it is expected that the security will be improved.

Furthermore, this system has a configuration in which the video signal is descrambled at the RF stage, and has the advantage that the decoder device can be provided at a low cost.

Incidentally, in the above embodiment, the period T during which scrambling is not performed
Although the stretch portion S2 of the NS is formed in the second half of the horizontal synchronization signal period, it may be formed in the first half. This is possible by shifting the timing of the signal 53b generated by the timing signal generator 53. Even if 82 is located in the first half, the normal synchronization signal is stretched, so it does not affect the difficulty of eavesdropping. Further, although the decoding data is superimposed on the vertical retrace period, it may be transmitted as FSK data through a data channel.

[Effects of the Invention] As described above, according to the present invention, even if the audio signal is stretched for descrambling the video signal, the influence on the audio signal can be reduced, and moreover, it is possible to easily prevent unauthorized viewing. It never happens.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the encoder side of the video scrambling/descrambling device according to the present invention;
Figure 2 is a block diagram showing Figure 1 in detail, Figure 3 is a block diagram showing Figure 1 in detail.
FIG. 4 is a block diagram showing the configuration of the decoder side corresponding to the embodiment shown in the figure, FIG. 4 is a block diagram showing FIG. 3 in detail, and FIG. 6 and 7 are block diagrams showing the encoder and decoder in a conventional video scrambling/descrambling device, and FIG. 8 is a time chart showing the operation of the device shown in FIGS. 6 and 7. 13... Data superimposition circuit, 15... PIF video suppression circuit, 18... Audio I FAM modulation circuit, 19... Synchronization separation circuit, 20... Control circuit, 30... Stretch circuit, 32 ... Synchronization separation circuit, 33 ... Data separation circuit, 34 ... Control circuit, 56 ... Random value generator, 63 ... Random value generation signal, 20c ... Audio stretch signal, 20d. ...Audio suppression signal, 83.54...Suppression waveform part.

Claims (1)

[Claims] A horizontal synchronizing signal of a video signal is scrambled with a random number pattern, and data for decoding the scramble as an initial value of the random number is transmitted using a vertical retrace period of the video signal or a data channel. In a video scrambling/descrambling device, the encoder side includes means for generating pulses at predetermined timings within the periods of a scrambled horizontal synchronization signal and an unscrambled horizontal synchronization signal, and transmission using the pulses from the pulse generation means. It has means for AM modulating the audio signal, and frequency conversion means for mixing the output of this means with a scrambled video signal and converting it into an RF frequency, and the decoder side reproduces based on the scramble decoding data. 1. A video scrambling/descrambling device comprising means for descrambling an RF signal that is a composite of video and audio signals using a descrambling timing pulse.