JPS6326026A - Emitter coupling type logic circuit - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a frequency characteristic and to surely execute a level shift by connecting a load resistor and a diode in forward polarity in series with both collectors of two transistors (TRs) constituting a differential amplifier respectively and connecting the terminal of the diode at the opposite terminal connected to the load resistor to a power supply. CONSTITUTION:A series connection between a diode 8 and a load resistor 12 and another series connection comprising a diode 9 and a load resistor 13 are connected separately between collectors of differential pair transistors (TRs) 10, 11 and a power terminal 1. The effective load resistance of the amplifier is expressed as the sum of the load resistor 12 and the resistive component of the level shift diode 8. Furthermore, the DC potential at the connecting points between the diodes 8, 9 and the resistors 12, 13 is set lower by the forward voltage drop of the diodes 8, 9 than the power potential. Thus, the signal outputted from the collectors of the TRs 10, 11 is level-shifted by one diode voltage drop. thus, the resistance of the collector load resistors is reduced more than the level shift by the resistors only.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an emitter-coupled thinking circuit, and in particular, to a 5Q
The present invention relates to an emitter-coupled logic circuit suitable for obtaining a high voltage gain in a high frequency range of Q MHz or higher.

[Conventional technology]

Conventionally, this type of emitter-coupled logic circuit has a second
Two transistors 1 form a differential amplifier as shown in the figure.
Two load resistors connected to the collector of 0.11
2.13 uses a circuit that is common on one side and connected to the power supply terminal 1 via a forward-connected level shift diode 8.9. In Figure 2, the level shift diode 8.9 is connected to the load resistor 12.1.
3 and the power supply terminal 1, and by setting the common side potential of the load resistor 12.13 lower than the power supply voltage by the forward voltage of the diode, the voltage can be taken out from the collector of the differential pair transistor 10.11. Shifts the level of the output signal to the next stage.

Next, amplify the five-person signal without using diodes,
An example of a circuit for level shifting is shown in FIG.

In this circuit, the resistance value of the load resistor 12.13 is set within a range that does not saturate the differential pair transistor 10.11 so that a predetermined output voltage is obtained, and the voltage drop due to the resistance is added to the M source voltage. However, the output signal was at a low DC potential.

[Problem that the invention seeks to solve]

In the conventional emitter-coupled logic circuit described above, if you want to increase the voltage gain or shift the level, you just need to increase the resistance value of the load resistor, but in order not to saturate the differential pair transistor, the resistance value naturally increases. The upper limit of is limited and sufficient level shifting cannot be performed, and when integrated into a semiconductor circuit, increasing the resistance value increases the resistance area on the semiconductor substrate, increases stray capacitance, and deteriorates frequency characteristics. There is.

SUMMARY OF THE INVENTION An object of the present invention is to provide an emitter-coupled logic circuit that can reliably perform level shifting and does not cause deterioration in frequency characteristics.

[Means for solving problems]

In the semiconductor integrated circuit of the present invention, separate load resistors and diodes are connected in series in the 1111 direction to both collectors of two transistors constituting a differential amplifier, and the opposite side of the diode is connected to the load resistor. The side electrode is iI
It has a configuration in which it is connected to an r source, so that an output voltage whose level is shifted by one diode can be obtained.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

A level shift diode 8 and a load resistor 1 are connected between the collectors of the differential pair transistors 10 and 11 and the power supply terminal 1.
2, a level shift diode 9, and a load resistor 13 are each separately connected in series.

The effective load resistance of this amplifier can be taken as the sum of the resistances of the load resistor 12 and the level shift diode 8, and the voltage gain is determined as follows. Additionally, level shift diode 8.9 and resistor 12.13
The DC potential at the connection point of transistor 1 is set lower than the power supply voltage by one voltage in the forward direction of diode 8.9.
The signal output from the 0.11 collector is level shifted by one diode.

Next, the voltage gain of this embodiment will be explained.

In FIG. 1, a signal is input to differential pair transistor 10.11, and the base potential of 10.11 is set to VBIOJBI.
I, the lightning current flowing through the transistor 10.11 ICl0
, ICII, where & k is Boltzmann's constant, T is absolute temperature, and q 1
The amount of cargo is M. If the input voltage difference is ΔVin, then the formula (
1) From (2), let the output voltages taken from the collectors of transistors 10 and 11 be VOIO and Volt, respectively, the forward voltage between the base and emitter of the transistor be vBε, and the evening pressure be V.
If the resistance value of CC1 resistors 12 and 13 is RL, then Vo1o=Vcc-RLXllo -VBEIO-・-
・-・(4)"oll=vcc RLXIII V
BEll-"...(5) Let the output voltage difference be Δ■o, Σ, and from equations (4) and (5), ΔVo=RL(11-2Ito)+
VBaxt Vngl.

Here, by differentiating Equation (6)'jkΔVin from (3) and (3)', the voltage gain shown in Equation (7) below can be obtained.

From equations (5) and (7), when the collector current on one side of the differential pair transistor changes in the direction of decreasing due to the signal, if the transistor is made on a silicon substrate, the potential difference between the two electrodes of the diode will be From the point when the voltage drops below 0.7V, the forward voltage decreases exponentially as the collector current decreases, so the collector potential reaches its maximum potential more quickly than when the load is only a resistor. . This is an advantage in logic circuits such as ECL.

〔Effect of the invention〕

As explained above, the present invention connects in series a load resistor and a separate diode forwardly connected to the source to both collectors of two transistors constituting a differential amplifier. If the level shift of one transistor is possible at the same time, the resistance connected to the collector including the resistance of the diode can be regarded as a load resistance, and especially if one of the differential pair transistors is input signal When the voltage approaches the cut-off state, the rate of change at which the collector potential reaches its maximum potential increases rapidly due to the effect of the diode, leading to a substantial improvement in the slew rate.

In addition, it has a level shift effect in the conductive state, and the value of the collector load resistance can be reduced compared to the case where the level shift equivalent to the present invention is performed using only the resistance value, reducing the output impedance and reducing the resistance area on the semiconductor substrate. Frequency characteristics can be improved due to the effect of reducing stray capacitance due to the reduction in resistance. Moreover, in the linear region, that is, in the input signal range in which the differential pair transistors are not cut off, the ε-tooth coupled logic circuit of the present invention can maintain the output DC level of the collector almost the same as in the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional example. 1...Power terminal, 2...Ground terminal, 3
... Constant current source, 4.5 ... Input terminal,
6.7... Output terminal, 8.9... Level shift diode, 12.13... Load resistance, 14... Bypass capacitor. −・−゛. Agent Patent Attorney Haku Uchihara i,'+ ,,,
+', -,'f=2fEJ Kaya 3ki

Claims (1)

[Claims] An emitter-coupled logic circuit characterized by consisting of a pair of transistors whose collectors each receive a power supply voltage through a series circuit of a level shift diode and a load resistor.