JPS63260222A - Clock frequency division circuit - Google Patents

Abstract

PURPOSE:To cope with the request of a clock signal economically by outputting a clock signal having a frequency relating to a ratio of values between two sets of integral numbers from a basic clock signal depending on a count output of a count means. CONSTITUTION:In receiving a switching signal Sa from a changeover means 300 in a clock frequency division circuit, a carry signal co is outputted from a count means 100 at each Na period of a basic clock signal mck and in receiving a signal sb, the signal co is outputted at each Nb period of the signal mck. A means 300 outputs a signal sa when the count n2 of a 2nd count means 200 belongs to a count group n2a and outputs a signal sb when the count n2 belongs to the count group n2b. Thus, the ratio of number of times of the output of the signal co at the periods Na, Nb of the signal mck from the means 100 is decided by arranging number of the count n2 of the means 200 belonging to the count groups n2a, n2b. Then the clock signal of the frequency relating to a ratio between the two sets of integral numbers Na, Nb is outputted from the signal mck.

Description

[Detailed Description of the Invention] [Summary] A first counting means that repeatedly counts by switching the basic clock signal to Na-base and Nb-base (however, the difference between Na and Nb is 1) according to an input switching signal; A second counting means that repeatedly counts the carry signal outputted by the first counting means by a predetermined integer value and outputs the counted value; and a switching means for inputting a switching signal corresponding to the category to which it belongs to the first counting means, and by the counting output of the second counting means, the division ratio is determined from the basic clock signal to an integer. This makes it possible to generate a unique clock signal.

[Industrial application field]

The present invention relates to a clock frequency divider circuit that generates a clock signal whose frequency division ratio is not an integer from a basic clock signal.

For example, in a data communication device that accommodates communication lines having multiple types of communication speeds, it is necessary to generate a plurality of clock signals each having a different frequency in order to transmit and receive data via each communication line.

In order to generate such a plurality of clock signals, a method is widely adopted in which a basic clock signal having a frequency that is an integer multiple of each clock frequency is divided by an integer number of -.

However, as the types of clock signals become more diverse, there are cases where a clock signal with a frequency division ratio that is not an integer with respect to the existing basic tally signal is required. , it is desired to realize a clock frequency dividing circuit that generates clocks economically.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional clock frequency dividing circuit.

In FIG. 4, a clock frequency dividing circuit 1 converts a basic clock signal mck of a frequency of 6.144 MHz outputted from an oscillator 2 into a clock signal o of a frequency of 56 kHz.
Assume that it is requested to generate ck.

The clock frequency dividing circuit l has a hexadecimal counter 11 and -
and 12.

The counter 11 is in a counting enabled state as a logic "1" enable signal is always input to the terminal EN, and the counter 11 is in a state where it can count by receiving a logic "1" enable signal from the oscillator 2 to the terminal CK.
Repeatedly counts the basic clock signal mck input to the
The count value n1 is r15J (in decimal notation, the same applies below))
Each time the count reaches the terminal CO, a carry signal col (logic "1") is outputted from the terminal CO and inputted to the terminal EN of the counter 12 as an enable signal.

The counter 12 receives the carry signal c from the counter 11.

Every time 1 is input, the basic clock signal m c k input to the terminal CK is counted by "1", and the counted value n2 is "
15'', a carry signal co2 is sent from terminal CO.
(logic "1") and outputs it to the outside as a clock signal ock, and the terminals LD of counters 11 and 12
input as the initial value setting signal.

As a result, each time the carry signal co2 is output from the counter 12, the counters 11 and 12 are set to the initial values inputted to the terminals A and 12, and start counting from the initial values.

In FIG. 4, 0", 11", 10", and "03 (binary representation, the same applies hereinafter) are input as initial values to terminals A to A of the counter 11, respectively, and terminal A of the counter 12 is input as an initial value.
Unfortunately, “1”, “0”, “0”, “1” respectively.
(binary representation, the same applies hereinafter) is input as the initial value, so the clock frequency divider circuit 1 constitutes a 110-decimal counting circuit, and the basic clock signal mck with a frequency of 6.144 MHz output by the oscillator 2 From, frequency 55.854
. . . A kilohertz clock signal ock is generated, and a clock signal ock with a desired frequency of 56 kilohertz cannot be obtained.

In addition, the initial value input to terminal A of the counter 11 is 1"
, '1', 0', '0', and if the clock frequency divider circuit 1 is a 109-decimal counting circuit, the frequency B56.366...
- A kilohertz clock signal Ock is generated, and a clock signal Ock with a desired frequency of 56 kilohertz cannot be obtained.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in conventional clock frequency divider circuits, the frequency division ratio is an integer (for example, 110 or 10
Since only the clock frequency dividing circuit 9) can be realized, for example, the basic clock signal mc having a frequency of 6.144 MHz can be realized.
From k, frequency 5 has a division ratio of 109.714...
It is impossible to generate a clock signal ock having a frequency of 6 kHz; for example, if the frequency division ratio of the clock frequency divider circuit 1 is set to 110, the frequency is 6.16 MHz, and the frequency division ratio is set to 109. In this case, it is necessary to newly provide an oscillator 2 for generating the basic clock signal mck having a frequency of 6.degree. 104 MHz, and there is a problem that it is not possible to economically meet the diversifying requirements for clock signals.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is two consecutive integer values Na
.

200 repeatedly counts the carry signal CO output by the first counting means 100 by a predetermined integer value Nc,
This is a second counting means that outputs a count value n2.

300 is the count value n2 output by the second counting means 200
determines which of two predetermined count value groups n2a and n2b it belongs to, and determines which of the count value groups n2a and n2b it belongs to.
2b, the switching signals Sa and sb corresponding to the first counting means 1
This is a switching means for inputting 00.

[Effect]

When the switching signal sa is inputted from the switching means 300, the first counting means 100 repeatedly counts Na cycles of the basic clock signal mck, and when the switching signal sb is inputted from the switching means 300, Basic tarokk signal mck
is repeatedly counted for Nb cycles. Note that the difference between the integer value Na and the key is "1".

That is, when the switching signal Sa is inputted from the first counting means 100, a carry signal co is outputted every Na period of the basic clock signal mck, and when the switching signal sb is inputted, a carry signal co is outputted. A carry signal co is output every Nb periods of the basic clock signal m c k.

The switching means 300 selects the count value n2 of the second counting means 200.
When the count value n2 belongs to the count value group n2a, the switching signal 5a is output, and when the count value n2 belongs to the count value group n2b, the switching signal sb is output.

Therefore, by appropriately distributing the count value n2 of the second counting means 200, the number belonging to the count value group n2a and the number belonging to the count value group n2a, the first counting means 1
00, the ratio between the number of times the carry signal CO is outputted in the Na period of the basic clock signal mck and the number of times the carry signal co is outputted in the Nb period of the basic clock signal mck is determined.

Since the frequency of the output clock signal ock is determined by the count output of the second counting means 200, a clock signal having a frequency related to the ratio of a value between two sets of integer values Na and Nb is obtained from the basic clock signal mck. It becomes possible to output a signal.

〔Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a clock frequency dividing circuit according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating various signals in FIG. 2.

In FIG. 2 as well, it is assumed that a clock signal ock having a frequency of 56 kHz is generated from a basic clock signal m c k having a frequency of 6.144 MHz output from an oscillator (2) not shown.

The division ratio between the basic clock frequency of 6.144 MHz and the clock frequency of 56 kHz is 109°714...
・The half period of the clock signal ock is 6144÷(56×2)(=54.82) of the basic clock signal mck.
1...) period, so 54.821...
Define 55 and 54, respectively, as two sets of consecutive integer values Na and Nb with , with The corresponding half period h(
54).

Furthermore, the occurrence ratio of half cycles h(55) and h(54) is
The average half period is determined to be 6144÷(56×2).

In order to easily select the occurrence ratio, the frequency division ratio is 6144+56.
Dividing by the greatest common divisor gives 768÷7. Therefore, the half period of the clock signal ock is 7X2=14, the half period h(55) is x1, and the half period h(54) is x2 (
However, in order to have a total of 768 cycles of the basic clock signal mck, xl=1
It is easily found that it is sufficient to set 2 sets, x2=2 sets.

As described above, the first counting means 100 is configured as a counting circuit capable of switching between 55-base and 54-base, and half period h (55
) and h(54), and the second counting means 200
is configured as a hexadecimal counting circuit, and the first counting means 100
The second counting means 200 counts half cycles h(55) or h(54) generated by the switching means 300.
If the half-cycles of 14ffl counted by are divided into 12 sets that generate a half-cycle h(55) and 2 sets that generate a half-cycle h(54), and the first counting means lOO is switched,
Desired clock signal oc from basic clock signal mck
k can be generated.

In FIG. 2, hexadecimal counters 101 and 102
constitutes the first counting means 100, and a hexadecimal counter 20
1 constitutes the second counting means 200, NOR circuits 301 and 302, AND circuit 303, NOR circuit 304
and the OR circuit 305 constitute the switching means 300.

The counter 101 always sends an enable signal (logic “1”) to the terminal EN.
) is input and is in a countable state, and the basic clock signal m c is input from the oscillator 2 (not shown) to the terminal GK.
k is repeatedly counted, and every time the count value n1 reaches "15", a carry signal coil (logic "L") is sent from the terminal CO.
is output and inputted to the terminal EN of the counter 102 as a permission signal.

The counter 102 receives a carry signal coil from the counter 101.
is input, the basic clock signal m c k input to the terminal CK is counted by "1", and the counted value n2 is "1".
5'', a carry signal co12 is sent from the terminal CO.
(logic "1") is inputted to the terminal EN of the counter 201 constituting the second counting means 200, and is also inputted to the terminals LD of the counters 101 and 102 as an initial value setting signal.

In FIG. 2, "0", "0", "1", and "1" are fixedly input as initial values to terminal A of the counter 102, and terminals A to terminal A of the counter 101 are input as initial values. The initial values are °l", "O", "0", 1" and 'O", 11".
, O'', and "1" can be switched and input.

As a result of the above, the counter 101 has “1” and “0” as initial values.
”, “0”, “1”, the counter 10
1 and 102 constitute a 55-decimal counting circuit, and the counter 101 is set with "0", "1", and 60 as initial values.
When ", '1" is input, counters 101 and 102 constitute a 54-base counting circuit.

Next, the counter 201 receives a carry signal CO from the counter 102.
12 is input, the basic clock signal mck input to the terminal CK is counted by "1", and the counted value n2 is "1".
5'', a carry signal co21 is sent from terminal CO.
(logic "1") and input it to terminal LD as an initial value setting signal.

In FIG. 2, since "0", "1", "0", and "0" are fixedly input as initial values to terminal A of the counter 201, the hexadecimal counting circuit is It is configured.

On the other hand, the switching means 300 is connected to terminals QA to Q of the counter 201.
Of the count value n2 output from B, terminals QA and QC
The signals qa and qC output from the AND circuit 3
03 and the NOR circuit 304, and the signals qb and qd output from the terminals QB and QD are input to the AND circuit 30 via the NOR circuits 30.1 and 302, respectively.
3 and input to the NOR circuit 304.

As a result, when the count value n2 of the counter 201 indicates "5", the switching signal s5 output from the AND circuit 303 is set to logic "1", and the count value n' of the counter 201 is set to logic "1".
2 indicates "10", the switching signal S10 output from the NOR circuit 304 is set to logic "1" and is input to the OR circuit 305, but the count value n2 of the counter 201 is "10". 2” to “4”, “6” to “9”, and “
11” to “15”, the NOR circuit 3
Switching signal s5 output from 04 and OR circuit 3
All switching signals S10 output from 05 are logic "O"
is set and input to the OR circuit 305.

When the switching signal S5 or S10 is set to logic "1", the OR circuit 305 outputs the switching signal S of logic "1".
is outputted and inputted to the first counting means 100, and when the switching signals S5 and slo are both set to logic "O", the switching signal S of logic "0" is outputted and inputted to the first counting means 100. input to means 100;

That is, the switching signal S indicates that the count value n2 of the counter 201 is "2".
4 to 4, 6 to 9, and 11 to 9.
15”, it is set to logic “0” and the counter 2
When the count value n2 of 01 indicates "5" and "10", it is set to logic "1".

In the first counting means 100, when the switching signal S of logic 10 is input, the terminals A of the counter 101 are set as initial values of "1", "0", "0", " Since "1" is input, the circuit operates as a 55-decimal counting circuit, and when the logic "1" switching signal S is input, the counter 1
01 terminals A to 01 have initial values of “0”, “1”,
Since "0" and "1" are input, it thereafter operates as a 54-decimal counting circuit.

Therefore, when the count value n2 of the counter 201 indicates "2" to "4", "6" to "9", and "11" to "15", the first counting means 100 calculates It operates as a counting circuit, and when the count value n2 of the counter 201 indicates "5" and "10", it operates as a 54-decimal counting circuit.

Further, since the counter 201 outputs the signal qa output from the terminal QA as the clock signal ock, the period in which the carry signal C012 is output from the counter 102 constitutes a half period of the clock signal ock.

Therefore, among the 14 half cycles of the clock signal ock, the first to fourth, sixth to ninth, and eleventh to 14th half cycles are half cycles h(55), and the fifth and tenth half cycles are half cycles. The period is h (54), and the total of 14 half periods corresponds to 768 periods of the basic clock signal m c k.

As is clear from the above description, according to this embodiment, the basic clock signal mc having a frequency of 6.144 MHz
k to half period h(55) of clock signal ock and h
(54) and half periods h(55) and h(54)
By generating
A clock signal ock having 6 kilohertz is generated.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the frequencies of the basic clock signal mck and clock signal ock are not limited to 6° 144 MHz and 56 kHz, respectively. Although many other modifications may be considered, the effects of the present invention remain the same in any case. Furthermore, the configurations of the first counting means 100, the second counting means 200, and the switching means 300 are not limited to those shown in the drawings, and many other modifications may be considered; The effect of the invention remains the same.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to easily generate a clock signal that does not have an integer frequency division ratio from a basic clock signal.
It becomes possible to economically meet diversifying clock signal requirements.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a clock frequency dividing circuit according to an embodiment of the present invention, FIG. 3 is a diagram illustrating various signals in FIG. 2, and FIG. 1 is a diagram showing an example of a conventional clock frequency dividing circuit. In the figure, 1 is a clock frequency divider circuit, 2 is an oscillator, 11
．． 12.101.102 and 201 are counters, 100
200 is a first counting means, 200 is a second counting means, 300 is a switching means, 301 and 302 are NOT circuits, 303 is an AND circuit, 304 is a NOR circuit, and 305 is an OR circuit. Honsha U Old Principle Sen No. 1 771C/2-DingLlfanJ"'L----------,-
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Claims (1)

[Claims] A basic clock signal (mck) is repeatedly counted until one of two consecutive integer values (Na, Nb) specified by an input switching signal (sa, sb) is reached. a first counting means (100) that outputs a carry signal (co); and a first counting means (100) that outputs a carry signal (co), the carry signal (co) outputted by the first counting means (100), by a predetermined integer value (Nc). a second counting means (which performs repeated counting and outputs a counted value (n2));
200), and the count value (200) output by the second counting means (200).
n2) is two predetermined count value groups (n2a,
n2b), and selects one of the switching signals (sa, sb) corresponding to each count value group (n2a, n2b) to which it belongs to the first counting means (1).
a switching means (300) for inputting the input to the basic clock signal (mck), and a switching means (300) for inputting the two sets of integer values (N
1. A clock frequency divider circuit, characterized in that it outputs a clock signal having a frequency related to a ratio of values in the middle of (a, Nb).