JPS63259877A - Processor for optical disk signal - Google Patents

Abstract

PURPOSE:To improve the processing speed for the defective data by providing the registers of plural bytes on plural buses at every input/output line set for a data buffer and adding an address circuit and a timing control circuit against those registers. CONSTITUTION:The write data are written into plural divided addresses of a data buffer 9 via a register 3 and a pre-register 4. When a prescribed quantity of the write data is fetched, the control information is added to the write data. Then this write data is sent to an optical disk drive. When a read instruction is received, the output received from an error correcting circuit 13 is written into the buffer 9 via a register 11 and a pre-register 10. When said output reaches a prescribed quantity, an access is given as necessary to the buffer 9 via a register 16 and a pre-register 17 based on the error correcting information. Thus an error is corrected. Then the data are sent to a host interface control circuit 1 via the pre-register 4 and the register 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an optical disk signal processing device for data recording and reproduction, and particularly to an optical disc signal processing device for data recording and reproduction, and particularly to an optical disc signal processing device for data recording and reproducing. Related to Optical Disk Signal Processing Devices (Prior Art) Conventional optical disk signal processing devices attach error correction codes (E, CC) to optical disk media and perform interleaving to arrange data. Two series of data buffers were provided and used alternately to absorb the delay time due to error correction.Also, for writing, two series of data buffers were used alternately.

[Problem that the invention seeks to solve]

In the conventional photon isk processing device described above, two series of data buffers (normally one track capacity of bytes are used)
The problem with this method is that if there is a delay in the processing of one series, the other data buffer cannot be used for one buffer and the system goes into a standby state. This occurs because the raw error rate of the medium is extremely low compared to a magnetic disk processing device, requiring powerful error correction, and the correction process takes a long time.Therefore, one buffer is allocated to each track. However, there is a drawback that the next track cannot be processed until the error correction processing or error recovery processing for that track is successful.

[Means for solving problems]

An optical disc signal processing device according to a first aspect of the present invention is an optical disc processing device that adds an error correction code, performs interleaving on a photon disk medium, arranges data, and corrects parse 1 to errors. a data buffer device, a post interface control circuit, a multi-byte two-stage register device corresponding to each of the drive interface and the microprocessor bus, and a timing control device and an address control device corresponding to each of the two-stage register devices; The optical disk signal processing device according to the second aspect of the present invention, which is configured with a queuing device for access requests from a data buffer device, adds 11 error correction codes and arranges data by interleaving on the optical disk medium. 1. In an optical disk processing device for correcting errors, a first data buffer device consisting of a plurality of bytes of word 1 and a plurality of bytes of two-stage register device corresponding to each of a host, an interface drive interface, and a microprocessor bus are provided. , a timing control device and an address control device corresponding to each of the two-stage register devices, a queuing device for responding to access requests from the data buffer device, and a second stage for temporarily storing read data in a stage before the error correction processing device.
[Embodiment] An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the data buffer and register of the present invention, and FIG. FIG. 4 is an explanatory diagram showing an example of dividing the data buffer.
FIG. 5 is a block diagram showing the configuration of an embodiment of the invention, FIG. 5 is a diagram showing the configuration of an error correction code used in the second invention of the invention, and FIG. 6 is a timing supplement diagram of the second invention of the invention. This is a time chart.

First, an embodiment of the first aspect of the present invention will be described with reference to FIG. 1. In FIG. is transferred to one microprocessor through the data bus 104] 9. When a data transfer request is sent to the data request control circuit 18, the microprocessor receives and receives data from the host system. At the same time, data buffer 79 is sent via register 3 and pre-register 4.
To determine the address that will receive the data,
A register timing control circuit 2 receives an address from the address control circuit 5, and a 3-data request control circuit 18 sends a clock signal to the register 3 and pre-register 4.
Then, the write signal 130 is output and the data is written into the data buffer 9. After the data buffer 9 has taken in a specified number of children, the microprocessor 19 writes the data into the register 16.
In order to access the child taha sofa 9 via the register register 7, a signal is sent to the address control circuit 7, register timing control circuit] 5, and data request control circuit 18, and control information ( For example, add an alternative toe/tsk address, selector address, etc.), then add error correction circuit 13, trifinterface control circuit]4 (this knee is collectively referred to as trifinterface). Optical disc)・Life I＼
Since the data is transferred, the MicroBrosse 19 is transferred to the register 0. Register timing 'control circuit 12 and address control circuit corresponding to register 11 -? By repeating the above operations, if a read command is received via the post interface control circuit 1, the write data will be continuously transferred to the optical disk drive I. The interface control circuit 14 and the error correction circuit 13 are activated.The output from the error correction circuit 13 is to register 1 and register 1.
0 to the data buffer 9 via the 2-resistor timing control circuit 12. The control contents of the address control circuit 6 and the like are set by the microprocessor 9.

When the predetermined number is reached in the read data buffer 9, the micro processor 19 reads error correction information (syndrome pointer, etc.) from the error correction circuit 13, and
If necessary, error correction is performed by accessing the data buffer via the register 16 and pre-register 17.This error correction ability also means that the data read from the optical disk drive is continuously captured. Once completed, the corrected data (no correction required if correct) is transferred to the host interface 1 via the register 4 register 3. Normally, the processing speed of the host interface control circuit is higher than the reading speed of the optical disk drive, so even if error correction takes time, there is a permissible correction time corresponding to the capacity of the data buffer 9. Furthermore, even if data defects occur continuously, the capacity of the data buffer can be increased to allow continuous processing, thereby improving processing speed.

Next, the method of accessing the data buffer 9 will be described with reference to Figures 2 and 3.7 Here, the data buffer 9 is divided into four parts, and addresses are assigned to each as a buffer A to F) as shown in Figure 3. Figure 2 shows an example in which buffer A → buffer B → buffer buffer C → buffer D - buffer buffer A. Circuit 6 The output from the address control circuit 7 for the microprocessor is selected by the selector 8 and becomes address signals for the buffers A to D as required. As for the active pre-registers and registers, only those corresponding to the error correction circuit are described, and the same applies to the others.To explain the writing, data from the error correction circuit 13 is transferred to the register 11/2 through the data hash 100.
The transfer strobe signal 114 from the 2-process error correction circuit to be written] 3 is sent as a register control signal]] 7 to the register timing control circuit 12 via the data request control circuit 18, and is sent to the register A and register B of the register 11.・Register C, Register D, Register A, etc. Each register is set in this order. Register A
At the time when register D is input, free register 10
Pre-registers A to D are also set at the same time. After setting, write signal 1 is sent from the data request control circuit.
30 (see Figure 1), writing to the data buffer 9 is suspended for up to 4 bytes if the bus is in use at the time, and is written after another bus is used. Conversely, the value is read from the data buffer 9 to the pre-registers A to D of the register 10 at once according to the control signal 120, and then the value is transferred to the registers A to D of the register 11 according to the control signals 121 to 124.
Data is sent from register 11 to the error correction circuit by sequentially selecting the outputs of registers A to D.
By configuring as shown in 2.
Input/output can be performed from a single lotus, making efficient processing possible Next, an embodiment of the second invention of the present invention will be described with reference to FIG. 11. Describe the differences between the example (see Figure 11) and the embodiment of the first invention (see Figure 4, 9).
The embodiment of the second invention is comparable to the embodiment of the first invention.
\, the second child-taha interface 2o, the second data buffer control circuit 2], the timing complement circuit 22 and the goo 1
~ circuit 23 is additionally provided, and the data buffer 0 is replaced by a first data buffer sofa 9A (the configuration and operation are the same as the data buffer sofa (:), only the name and reference numerals are different). Accordingly, the explanation will focus on a modification different from one embodiment of the first invention, that is, the second data buffer 20.

Next, the second data buffer sofa 2o near the error correction circuit 13 and the second data buffer control circuit 21 will be described with reference to FIGS. 5 and 6.

Further, FIG. 5 shows the format of the error correction code of the optical disc device.

The number of interleaves is λ, ] interleave Dn1
This allows several bytes to be corrected for Dn2 and Dn3-EnlHEn2.

For example, there is a defect in the take mark when reading data.D
Consider a case where the data is not transferred as expected, and the take transfer is started from the next resynchronization mark.The error correction circuit 13 will miss the target byte for the syndrome operation, and will not be able to perform correct calculations, making correction impossible. Furthermore, as long as the byte position is sent correctly, the error correction circuit 13 can make sufficient corrections.

We will now discuss the error correction code 1 input format shown in Figure 5.Enter from the top of the left column in this figure, and when you reach the bottom, enter the input format in the same format from ``2'' in the next column on the right. Continuing from right to left I\, the last error correction code, Forma So 1~, is input/output. Take mark 5
For the lost data (Pro-Tsuku), the data buffer and a) hereless control circuit transfer the data D1, D21'D3□, D1□D22, up to the next resynchronization mark.
Complement D3□..., error correction circuit! In this case, the supplementary data is optional “00 (hexadecimal display)”
If the error correction code is large and the correction ability is high, then the data up to the second or third resynchronization mark is Complementing the transfer take allows the microprocessor 19 to instruct the timing complement circuit 221 to complete the specified number of bytes. The timing chart of the complementary cheater strobe is not shown in Fig. 0, which is the gate for displaying) Normally, the read cheater strobe occurs from the position of the take mark, as shown at timing A during normal operation. . If there is a defect in the take mark, the data mark is not detected as shown in imink B. -13 = If the take mark is small, the child up to the first resync will not be sent. When data is transferred from the second data buffer by the timing complement circuit 22, the data is complemented and transferred to the error correction circuit I\ as at timing C. Although the probability of data mark abnormality occurring is relatively small, the second data buffer is used only in that case.

〔Effect of the invention〕

As explained above, the present invention provides two stages of multiple-byte registers from three buses for each input/output line to the main data buffer, and provides an address control circuit and a timing control circuit for the registers. Since input/output can be performed from three or more hubs, it is possible to enable simultaneous operation of, for example, a post-interface, drive interface, or microprocessor, and it is also possible to correct defective data that requires a long time for error correction. ,
By arranging the second tabbed sofa before the error printing circuit, which has the effect of being able to perform continuous take processing, even if the data start position (data mark) is incorrect, the next resync can be performed. (G) Complementing (or interpolating) data has the effect of making miller corrections possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the first embodiment of the present invention, FIG. 2 is a flow diagram showing the configuration of the data buffer and register of the present invention, and FIG.・An explanatory diagram showing an example of dividing a sofa. ・FIG. 4 is a block diagram showing the configuration of an embodiment of the second invention of the present invention. FIG. 5 is an error correction code used in the second invention of the present invention. Figure 0 is a time chart 7 of the timing complementation of the second invention of the present invention.

Claims (2)

[Claims] (1) In an optical disk processing device that adds an error correction code, performs interleaving on an optical disk medium, arranges data, and corrects burst errors, a data buffer device with a word length of multiple bytes, a host interface control circuit, and a drive interface are used. and a multi-byte two-stage register device corresponding to each of the two-stage register devices, a timing control device and an address control device corresponding to each of the two-stage register devices, and a queuing device for responding to access requests of the data buffer device. An optical disc signal processing device characterized by: (2) In an optical disk processing device that adds an error correction code and performs interleaving on an optical disk medium to arrange data and correct burst errors, a first data buffer device having a word length of multiple bytes and a host interface drive are used. A multi-byte two-stage register device corresponding to each of the interface and microprocessor bus, a timing control device and an address control device corresponding to each of the two-stage register devices, a queuing device for a data buffer device access request, and an error correction device. An optical disc signal processing device comprising: a second data buffer for temporarily storing read data at a stage before a processing device; and a timing control device and an address control device corresponding to the second data buffer.