JPS6325881A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent an erroneous action in which noise from a writing bit line is assumed as a cause by laying in extending a ground line which decrease the capacity between a writing bit line and a reading bit line between a writing bit line and a reading bit line. CONSTITUTION:An aluminum wiring 8 connected to a ground (earth) is laid in extending in a Y direction, this is constituted as a ground line GND, and this is laid in extending in parallel to respective writing reading bit lines BW and BR and between both these bit lines BW and BR. The ground line GND is connected to a diffusion area 2a in a contact 10. Thus, since the ground line GND is functioned as the shield to interrupt electrically both bit lines BW and BR, the capacity between both bit lines BW and RR is cancelled, and even by the change in a writing bit line BW, the noise will not occur at the reading bit line BR.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that performs read and write operations asynchronously, and particularly to a dynamic semiconductor memory device in which a memory cell is configured with three elements.

[Conventional technology]

2 and 3 have been proposed as dynamic three-element memory cells that perform read and write operations asynchronously.

That is, as shown in FIG. 2, the memory cell is composed of three MOS transistors Q, , q, , Q3, and a word line W is used to write to the MOS transistors. and bit line B.

and word line WR and bin for reading) %'A
B11 are connected to each other. Also, the readout pin)
MOS transistors Q4, Qs and Qb, Q7 are connected to h%BR, respectively, to form an information readout circuit.

As shown in FIG. 3, this memory cell is constructed of a polycrystalline silicon film 3.4 extending approximately in the X direction on diffusion regions 2a and 2b formed in a semiconductor substrate 1, and connected to the write and read word lines W1. The writing and reading bit lines Bw and B are made up of aluminum wirings A6 and 7 extending in the Y direction. In the figure, reference numeral 5 denotes a polycrystalline silicon film for configuring the cell capacitor 1c and the MOS transistor Q.
connected to b. Moreover, 8 is an aluminum wiring as a ground line connected to GND (earth), and is connected to the diffusion region 2a through a contact 1-10. Furthermore, 11 and 12 are write and read bit lines B, respectively.
These are contacts for connecting w and B* to the diffusion regions 2b and 2a.

[Problem that the invention seeks to solve]

The conventional memory cell described above shares the aluminum wiring 8 as a ground line with an adjacent memory cell (not shown) as shown in FIG. Aluminum wirings 6 and 7 constituting B* are extended adjacent to each other. Therefore, both bits 'faBw.

Write bit line B due to capacitance CX between B1. When the read bit lines B and I change, the read bit lines B and I are in a state where they are susceptible to noise.

By the way, in this memory cell, the content of the cell is L (Low
), the read bit line Be becomes H()Iigh), but it is the transistor Q4 that maintains this H state, and the current capacity of this transistor Q4 cannot be increased very much. That is, when the content of the cell is H, the read bit line BR becomes L, and this L is caused by the transistor Q4. Qz
, Q+, so the transistor Q
When increasing the current capacity of transistor Q, the current capacity of transistor Q is increased.
Q also becomes larger, leading to an increase in the size of the cell.

Therefore, when the read bit line B is at H, the H holding ability is weak (it is extremely vulnerable to external noise. Therefore, the above-mentioned noise from the adjacent write bit vAB w causes the read bit line Bl to Normal readout of the data will be inhibited, resulting in malfunction.

[Means for solving problems]

The semiconductor memory device of the present invention solves the above problems, prevents malfunctions caused by noise from the write bit line, and enables normal reading.

The semiconductor memory device of the present invention has a configuration in which a ground line is extended between a write bit line and a read bit line to reduce the capacitance between the write bit line and the read bit line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan layout diagram of a memory cell in one embodiment of the present invention, and its circuit is as shown in FIG.

As shown in FIG. 1, word lines W for writing and reading are formed by polycrystalline silicon films 3.4 extending in the X direction shown on the diffusion regions 2a and 2b formed in the semiconductor substrate 1, respectively. ,W,
, and the aluminum wiring 6.7 extended in the Y direction shown in the figure.

They constitute read bit lines Bw and BR.

Further, a polycrystalline silicon film 5 for forming a cell capacitor C and a MOS transistor Q1 is formed on the diffusion region 2a and a part of the diffusion region 2b, and is connected to the diffusion region 2b by a contact 9. . Also, the ground (
An aluminum wiring 8 connected to the ground (ground) is extended in the Y direction in the figure to constitute a ground line GND, and is connected to each of the write and read bit lines B. Both bit lines B are parallel to +BR. +B11. This ground line GND is connected to the diffusion region 2a at a contact 10. Furthermore, each of the write and read bit lines Bw and B* is connected to contact 1.
1.12 to the diffusion regions 2b, 2a.

According to this configuration, the memory cell circuit is the same as before as shown in FIG. 2, but by extending the ground line GND between the write and read bit lines Bt, +, and Bm lines, This ground line GND is both bit line Bw
, B*.

Therefore, both bit lines B. , 81 and eliminates the capacitance between the write bit line B. Noise is not generated on the read bit line B even due to a change in .

Therefore, even if the current capacity of the transistor Q (see Figure 2) connected to the read bit line BR is small, the H state in the read bit line B can be stably maintained, resulting in read malfunction. can be prevented. Thereby, there is no need to increase the size of transistor Q4, and correspondingly transistors Q, ,Q,
It is effective in reducing the size of the storage cell without the need to increase the size of the memory cell.

Note that even if the ground line GND is placed between the write and read bits '4iABW and BN, the first
As can be seen from the comparison between this figure and FIG. 3, the size of the memory cell is not increased.

(Effects of the Invention) As explained above, the present invention extends the ground line between the write bit line and the read bit line to reduce the capacitance between the write bit line and the read bit line. Therefore, even changes in the write bit line do not generate noise in the read bit line, and a stable read operation without malfunction can be realized, and a micro-sized memory cell can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan layout diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a memory cell, and FIG. 3 is a plan layout diagram of a conventional memory cell. DESCRIPTION OF SYMBOLS 1...Half-quad board, 2a, 2b...Diffusion region, 3,
4゜5...Polycrystalline silicon film, 6,7.8...Aluminum film, W8...Write word line, wR...
Read word line, BR...Write bit line, BR
...Read bit line, GND...ground line.

Claims (2)

[Claims] (1) Configure a memory cell with three transistors, write,
1. A semiconductor memory device in which reading is performed asynchronously, characterized in that a ground line is extended between a write bit line and a read bit line of the memory cell. (2) A semiconductor memory device according to claim 1, wherein a write bit line and a read bit line extend in parallel, and a ground line extends between and in parallel with these bit lines.