JPS6325832A - Rf signal generating circuit for optical information reader - Google Patents

Abstract

PURPOSE:To delay one of outputs of two elements in accordance with the pit depth to obtain a distortionless RF signal by delaying one of outputs of two elements in accordance with a difference signal and adding the other to the delayed output. CONSTITUTION:This RF signal generating circuit consists of a 4-divided photodetector 1, adders 2, 3 and 5, a variable delay circuit 10, and a subtractor 11. If the pit depth is lambda/4, the level of the output of the subtractor 11 is zero; and if it is shallower than lambda/4, for example, lambda/5, the output of the subtractor 11 has a certain level, and a certain phase is outputted. Since the level of the output of the subtractor 11 is changed in accordance with the pit depth, the signal delay time in the variable delay circuit 10 is changed in accordance with the pit depth. Since the pit depth is so determined that it is shallower than lambda/4, the phase difference between the output of the variable delay circuit 10 and that of the adder 3 is eliminated to output the good distortionless RF signal from the adder 5.

Description

TECHNICAL FIELD The present invention relates to an RF signal generation circuit for an apparatus for reading recorded information on an optical recording disk such as a digital audio disk.

BACKGROUND ART A circuit as shown in FIG. 4 has already been devised as an RF signal generating circuit for an optical information reading device such as a digital audio disc player and is disclosed in Japanese Utility Model Application No. 60-23932. In FIG. 4, reference numeral 1 denotes a four-part photodetector as a light receiving element. The four-segment photodetector 1 is composed of four elements la, lb, 1c, and ld arranged adjacent to each other with two straight lines A and B orthogonal to each other as boundary lines on the light-receiving surface. This 4-split photodetector 1 has a 4-split photodetector 1 that detects 4 parts through the recording surface of a recording disc (not shown) in accordance with the movement of an information reading optical spot on a recording track of a recording disc (not shown) during information reading.
The split photodetector 1 is installed in a pickup (not shown) so that the pattern of the intensity distribution of light incident on the light receiving surface of the split photodetector 1 moves in a direction parallel to the straight line A, for example. Among the elements 1a to 1d of this four-part photodetector 1, the element la is located behind the straight line B in the moving direction of the pattern of the intensity distribution of the incident light.

Each output of 1d is added by adder 2. Further, the outputs of elements lb and lc are added by an adder 3. The output of adder 2 is supplied to delay line 4. The signal delay time in the delay line 4 is, for example, 2
It is 20ns.

The output of the delay line 4 is added to the output of the adder 3 by an adder 5. The output of this adder 5 is output as an RF multiplied signal.

In the above configuration, when the pit depth on the recording track is λ/5 (λ is the wavelength of the information reading laser beam), the center of the information reading optical spot 7 is as shown in FIG. 5(A). The intensity distribution pattern of the reflected light on the light receiving surface of the four-segment photodetector 1 when located at the end of the pit 8 is as shown in FIG. Also, pit 8 is shown in the same figure (A).
When moving in the direction shown by the arrow in , the pattern of the intensity distribution of the reflected light moves in the direction shown by the arrow in FIG.

Therefore, element la of quadrant detector 1.

The sum of outputs of elements 1d and the sum of outputs of elements 1b and 10 have almost the same waveform only with a certain fixed time difference (phase difference). By delaying the output of adder 2 by delay line 4 by the same time as this time difference, la
, ld and the time difference between the outputs of 1b and lc can eliminate distortion caused by the RF multiplied signal.

However, there are variations in the depth of the pit, and for example, when the depth of the pit is λ/4, even when the light spot 7 is located at the edge of the pit as shown in FIG. The intensity distribution pattern of the reflected light on the light receiving surface 1 becomes as shown in FIG. Furthermore, when the depth of the pit is deeper than λ/4, the moving direction of the pattern of the intensity distribution of the reflected light is opposite to that when the pit depth is λ/4. Therefore, in the conventional RF signal generation circuit, when the depth of the pit becomes approximately equal to λ/4, the distortion becomes large, and the distortion cannot be removed sufficiently.

SUMMARY OF THE INVENTION The present invention was made to eliminate the drawbacks of the conventional circuits as described above, and provides an RF signal generation circuit for an optical information reading device that can sufficiently eliminate distortion appearing in an RF multiplied signal. The purpose is to

The RF signal generation circuit of the optical information reading device according to the present invention generates a pattern of the intensity distribution of light from the recording surface in a straight line substantially perpendicular to the direction in which it moves in accordance with the movement of the information reading light spot on the recording track. A difference signal is generated according to a level difference between the outputs of at least two elements arranged adjacent to each other so as to be divided into two and forming a light receiving element, and an output of one of the two elements is generated according to the difference signal. The configuration is such that the output is delayed and added to the output of the other of the two elements.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the mount, there is a 4-part photodetector, an adder 2,
3 and 5 are connected similarly to the circuit of FIG. However, in this example the output of adder 2 is supplied to variable delay circuit 10.

The output of the adder 2 delayed by the variable delay circuit 10 is supplied to the adder 5. Further, the outputs of adders 2 and 3 are supplied to a subtracter 11, and a signal corresponding to the difference between the two outputs is output. The output of this subtracter 11 is the variable delay circuit 1
0 as a control signal. The variable delay circuit 10 is
The signal delay time changes depending on the level of the control signal.5
It is composed of

In the above configuration, when the pit depth is λ/4, the output level of the subtracter 11 becomes zero. Further, when the depth of the pit is shallower than λ/4, for example λ/5, the output of the subtracter 11 has a certain level and becomes an output of a certain phase. Also,
When the depth of the pit is deeper than λ/4, for example λ/3, the output of the subtracter 11 has the opposite phase to the output when the bit depth is λ/4.

In this way, since the level of the output of the subtracter 11 changes depending on the depth of the pit, the signal delay time in the variable delay circuit 10 changes depending on the depth of the bit.

Therefore, for example, in a small digital audio disc called a compact disc, the pit depth is set to be shallower than λ/4, so that the distance between the output of the variable delay circuit 10 and the output of the adder 3 is determined to be shallower than λ/4. This makes it possible to eliminate the phase difference between the adder 5 and the adder 5.
A doubled signal will be output.

FIG. 2 is a circuit block diagram showing another embodiment of the present invention, in which power is supplied to the cathodes of photodiodes Da, Db, Dc, and Dd corresponding to elements 18 to 1d, respectively. Both photocurrents output from the anodes of the photodiodes Da and Dd are supplied to the negative input terminal of the operational amplifier 12. Also, photodiode D
b. The photocurrent output from the DC anode is both supplied to the negative input terminal of the operational amplifier 13. The positive input terminal of operational amplifier 12 is grounded. Operational amplifier 12
A feedback resistor R1 is connected between the negative input terminal and the output terminal of. An adder 14 is formed by the operational amplifier 12 and the feedback resistor R1. The positive input terminal of the operational amplifier 13 is grounded. Further, a feedback resistor R2 is connected between the negative input terminal and the output terminal of the operational amplifier 13. An adder 15 is formed by the operational amplifier 13 and the resistor R2.

The output of adder 14 is connected to delay line 1 via resistor R3.
6. The output of the delay line 16 is supplied to the negative input terminal of the operational amplifier 17 via a resistor R4. An adder 15 is connected to the negative input terminal of the operational amplifier 17.
The output of is supplied via resistor R5. The positive input terminal of operational amplifier 17 is grounded. Operational amplifier 17
A feedback resistor R6 is connected between the negative side input terminal and output terminal of. These operational amplifiers 17. An adder 18 is formed by resistors R4 to R6.

On the other hand, the outputs of adders 14 and 15 are respectively resistor R7
and is supplied to each of the positive input terminal and negative input terminal of the operational amplifier 19 via R8. The positive input terminal of the operational amplifier 19 is grounded via a resistor R9. Further, a feedback resistor RIo is connected between the negative input terminal and the output terminal of the operational amplifier 19. These operational amplifiers 19.
A differential amplifier 20 is formed by resistors R8 to RIo.

The output of this differential amplifier 20 is supplied to the negative input terminal of a comparator 22 via an integrator 21 consisting of a resistor R1+ and a capacitor C. A reference voltage Vr obtained by dividing the power supply by resistors RI2 and RI3 is applied to the positive input terminal of the comparator 22. The output of this comparator 22 is an FET (field effect transistor) 2
It is supplied to gate 3. The drain and source of FET 2B are connected to both ends of delay line 16, respectively.

In the above configuration, if the bit depth is shallower than λ/4, when the adder 14 outputs the addition output a as shown in FIG. 3(A), the adder 15 outputs the addition output a as shown in FIG. As shown, an addition output is output which has a time difference T from the addition output a and has substantially the same waveform as the addition output a. Therefore,
By making the signal delay time in the delay line 16 equal to the time difference T, the signal delay time from the delay line 16 in the same figure (
When added and output as shown in C), the delayed signal C whose phase matches
is output.

On the other hand, at this time, the differential amplifier 20 outputs a signal as shown in the figure (D), and this signal passes through the integrator 21 and becomes smaller than the reference voltage Vr as shown in the figure (E). Therefore, the output of the comparator 22 becomes a low level as shown in FIG. 2(F), and the FET 2B remains off. Therefore, when the adder 18 outputs the addition, the delayed signal C having the same phase is added to the added output, resulting in an RF multiplied signal having a waveform with steep rises and falls as shown in FIG. Output. Note that when the addition output a is supplied to the adder 18 without being delayed by the delay line 16, an RF multiplied signal with a slow fall and a slow fall is output as shown in FIG.

Further, when the bit depth becomes approximately equal to λ/4 and there is no phase difference between the addition outputs a and 5, the level of the output of the integrator 21 becomes equal to or higher than the reference voltage Vr, and the comparator 22 A high level signal is output from the FET
23 is turned on.

Then, the addition output a will be directly supplied to the adder 18 without passing through the delay line 16, and an RF multiplied signal without distortion will be obtained.

In the above embodiment, the sum of the outputs of the elements 1a and 1d is supplied to the signal delay means, but depending on the moving direction of the pattern of the intensity distribution of the light incident on the light receiving surface, the sum of the outputs of the elements 1b and 1c may be supplied to the signal delay means. It may also be supplied to signal delay means. Also, the variation in pit depth is λ/
In the case of a wide range from a value smaller than 4 to a value larger than 4, the output sum of elements la and lb and element lb
.

It is also conceivable to provide a signal switching means for selectively supplying one of the output sums of the IC to the signal delay means by the output of the subtracter 11 or the output of the differential amplifier 20. Also, the output of the subtracter 11 or the output of the differential amplifier 20 is R
It is also conceivable to perform normalization through division processing using the F-fold signal to eliminate the influence of RF-fold signal level fluctuations due to changes in disk reflectance, etc.

Effects of the Invention As detailed above, the RF signal generation circuit according to the present invention has a pattern of light intensity distribution from the recording surface that is substantially perpendicular to the direction of movement in accordance with the movement of the information reading optical spot on the recording track. A difference signal corresponding to a level difference between the outputs of at least two elements arranged adjacent to each other so as to be divided into two by a straight line and forming a light receiving element is generated, and one of the two elements is selected according to the difference signal. Since the output of the pit is delayed and added to the output of the other of the two elements, even if the bit depth changes and the time difference between the outputs of the two elements changes, the pit depth remains unchanged. The output of one of the two elements is delayed in accordance with this, and an RF multiplied signal without distortion is obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a circuit block diagram showing another embodiment of the invention, and Fig. 3 shows the operation of each part of the circuit in Fig. 2. The waveform diagram, FIG. 4 is a block diagram showing a conventional circuit, and FIGS. 5 and 6 are
FIG. 3 is a diagram showing the relationship between the position of a light spot and the pattern of intensity distribution of reflected light. Explanation of symbols of main parts 1... 4-segment photodetector 2.3, 5, 1
4.15.18...Adder 10...Variable delay circuit 11...Subtractor 16...Delay line 20...Differential Amplifier 23...FET

Claims (1)

[Claims] An RF signal generation circuit for an optical information reading device that irradiates light onto a recording surface of a recording medium to form an information reading light spot and reads information by the light that passes through the recording surface, the circuit comprising: The spots are arranged adjacent to each other so that the pattern of the intensity distribution of the light passing through the recording surface is divided into two parts by a straight line substantially perpendicular to the direction of movement according to the movement of the spots in the elongation direction of the recording track formed on the recording surface. a light-receiving element made up of at least two elements, a difference signal generating means for generating a difference signal according to a level difference between the outputs of the two elements; a signal delay means for delaying the difference signal according to the difference signal, and a signal obtained by adding the other of the two elements and the output of the signal delay means is R.
An RF signal generation circuit for an optical information reading device, characterized in that it outputs an F signal.