JPS63255705A - Velocity equalizing controller - Google Patents

Abstract

PURPOSE:To control velocities of two motors to equalize them by providing a two-phase pulse generating means which outputs a pair of two-phase pulses obtained by averaging two pairs of two-phase pulses, an adjusting signal output means, and an arithmetic part. CONSTITUTION:Servo parts 71 and 72 drive motors M1 and M2 by signals of a tachogenerators TG1 and TG2 and pulse generators PG1 and PG2 and control signals. A velocity equalizing controller consists of a two-phase pulse generating part 10 consisting of pulse processing circuits 11 and 12, OR circuits 21 and 22, a counter 31, and a two-phase pulse generating circuit 5, an adjusting signal output part 20 consisting of OR circuits 23 and 24, a counter 32, and a D/A converting part 4, and an arithmetic part 30 consisting of computing elements 61 and 62. In this controller, the pair of two-phase pulses are fed back, and the adjusting signal output part 20 outputs an adjusting signal so that the difference of the number of pulses between them is zero, and an inputted velocity command signal is adjusted by this adjusting signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device that rotates two motors in the same direction and by the same rotation angle.

[Conventional technology]

Conventionally, this type of control device has performed tandem control using a dedicated controller as shown in FIG. 3 in order to move two motors in unison in country-type machines such as plano mirrors and gas cutters.

As shown in FIG. 3, the dedicated controller described above has an instantaneous command register 1. which inputs an X-axis pulse command CTL for driving both wheels in the X-axis direction. ．． 12, and Moshula Serpo Motor 9. ．． 92 pulse generators PG, PG2
Current value register 2, which inputs the pulse output outputted by the current value register 2. ．． 22, the instantaneous command 11, and the data of the current value register 21, and the difference between the input data is calculated as the tracking error.

3. and an arithmetic unit 32 which inputs the data of the instantaneous command register 12 and the current value register 22 and outputs the difference between the input data as a tracking error D2, and a D/A which inputs the following error and performs D/A conversion. A converter 7I
The output of the D/A converter 71 and the output of the tachogenerator TG of the modular servo motor 91, which is the 9 original input, are inputted to the moshular servo motor 9. a drive unit 8 for driving the motor M; and tracking error D1゜D2
Synchronization, which inputs and outputs the synchronization error,,! 'i difference amplifier 4
, an amplifier 5 inputs the synchronization error and outputs the non-synchronization error, an amplifier 5 inputs the non-synchronization error and the tracking error D2, and outputs the correction signal D3 [10 IJI correction section 6 and the correction signal D3 D/A converter 72 that inputs and converts D/A, and D
The drive unit 82 drives the motor M2 of the mosular servo motor 92 by inputting the output of the /A converter 72 and the output of the tachogenerator TG of the modular servo motor 92, which has nine inputs.

[Problem that the invention attempts to solve]

The conventional control device described above can drive two motors (a controller for V must be used, and the existing system that drives one motor as shown in Figure 2 can drive two motors). The disadvantage is that the controller itself must be replaced when attempting to drive multiple motors.

(Means for Solving the Problems) The uniform speed control device of the present invention outputs a speed command signal and receives the speed command signal from an NC section that inputs a two-phase pulse to move an Xtl controlled object to a predetermined position. 1. A second pulse generator is connected to the first pulse generator, which moves the controlled object. The first motor drives the second motor, respectively. the first servo section and the second servo section respectively.
．． A constant speed control device that outputs a second control signal and outputs two-phase pulses to an NC unit, which inputs first and second two-phase pulses from a first and second pulse generator, respectively, and outputs two-phase pulses to an NC unit. 1. When the second motor is rotating in the positive direction, an up pulse is output to the first output terminal, and when the motor is rotating in the negative direction, a down pulse is output to the second output terminal. Y-constrain the frequencies of the first pulse generator and the second pulse generator from the up pulse or down pulse output from the first and second pulse processing circuits that output. a two-phase pulse generation means for outputting a third two-phase pulse having a frequency of Detect the difference in the number of two-phase pulses and make adjustments based on the difference in the detected number of pulses.)
Input the speed command signal from the NC section and the adjustment signal output stage 1 that outputs the signal, input the A adjustment signal from the adjustment signal output stage 1, and set the difference in the number of pulses detected by the signal output means to zero. The input speed command signal is adjusted by the adjustment signal so that the first. and an arithmetic unit that outputs a second control signal.

(Function) Therefore, the NC section outputs a speed command signal, and one set of two
Since the phase pulses are fed back, from the perspective of the NC unit, it is the same as driving one motor. Therefore, if the present invention is applied, it is possible to drive two motors using a conventional control device that controls one motor. Uniform speed control is possible.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the speed constant control device of the present invention.

In this embodiment, motors M, M2, and motor M are used.

a tacho generator TG, a pulse generator PG, and a tacho generator TG2, connected to a motor M2. A pulse generator PG2 and a control signal CTL at one input terminal.

CTL7. A servo section 7 which inputs the outputs of the tachogenerators TG, TG2 as negative feedback inputs to the other input terminal and drives the motors M and 1M2, respectively. ,7. and pulse generator PG.

The two-phase pulses S, , S2 of PO2 are respectively input, and the pulse output obtained by performing quadruple differential processing on the input two-phase pulses S, , S, is sent to the motor MI.

When rotating in the positive direction, a negative logic up pulse 10FB, ,+FB is sent to the output terminal P, respectively.

When the motors M, , M2 are rotating in the negative direction, a negative logic down pulse -F is output to the output terminal N respectively.
Pulse processing circuit 1 which outputs as B, , -FB. ．． 1
．． and an up pulse 10 FB at the input terminal of one negative logic,
, an OR circuit 21 which inputs an up pulse 10FB to the other negative logic input terminal and outputs the output to the negative logic output terminal;
An OR circuit 22 inputs a down pulse -FB to one negative logic input terminal, a down pulse -FB to the other negative logic input terminal, and outputs the output I' to the logic output terminal; Up pulse ten FB at the input end of negative logic.

An OR circuit 23 that inputs a down pulse -FB2 to the other negative logic input terminal and outputs the output to the negative logic output terminal, and an up pulse +FB to one negative logic input terminal, and the other negative logic input. The OR circuit 24 inputs the down pulse -FB to the terminal and outputs the output to the negative logic output terminal, and the output of the OR circuit 21 is input to the negative logic up count input IU.
Input the output of the OR circuit 22 to the negative logic down count input D3iD, count up by inputting the up count input terminal U, count down by inputting the down count input HD, and convert the result into a binary output to 20.2+
, 22. The output of the 23rd place is output Q Q A ,
Output to Q R, Q c, Q o and clear terminal CLR
When a clear signal is input to the output terminals Q A and Q a
, Qc.

Input the output of the OR circuit 23 to the counter 31 that clears the output of Qo and the up-count input O4U of negative logic,
OR circuit 2. to negative logic down count input iD. Input the output of , count up by inputting up count input > 2u, count down by inputting at the end of down count input, and use the result as binary output as 2° 21,2
2.The output of the 23rd place is output terminal Q A, Q B respectively.
, Q c , Q o and clear 9:f-C
When a clear signal is input to L R, the output terminal Q A,
A counter 32 that clears the outputs of Q R, Q c and Q o, and output terminals Q A and Q a of the counter 32.

A D/A converter 4 inputs the outputs of Q c and Q o, performs D/A conversion, and outputs an adjustment signal, and the output of the output end Qc of the counter 3I is set as the A phase. Output end Q of
A two-phase pulse output circuit 5 which performs the exclusive OR of the outputs of e and Qc, sets the result as the B phase, and outputs a two-phase pulse S3 consisting of A and B phases to an NC section (not shown); Input the speed command signal (-) CTL from the NC section to one end, input the output of the D/A converter 4 to the other input end, and control by subtracting the output of the D/A converter 4 from the speed command signal CTL. Signal CTL.

A computing unit 61 outputs a speed command 11 to one input terminal.
A calculation that inputs No. 1 CTL, inputs the output of D/A converter 4 to the other input terminal, adds the input speed command signal CTL and the output of D/A converter 4, and outputs control signal CTL2. It is composed of a container 62.

Also, the OR circuit 21+22 and the counter 3. and the two-phase pulse generation circuit 5 are the two-phase pulse generation section IO, the OR circuit 23, 24, the counter 32, and the D/A converter 4 are the adjustment signal output section 20, and the calculation side 6 and 62 are the two-phase pulse generation section IO. This is a calculation section 30.

Next, the operation of this embodiment will be explained.

Counter 3. ．． 32 inputs a clear signal to the clear terminal CLR and outputs the output terminal Q A I Q a + Q c +
It is assumed that the output of Qo is cleared. When the NC section outputs the speed command signal CTL that rotates the motors M, M2 in the forward direction, the output of the D/A converter 4 becomes "0".
This means that the calculation unit 6. ．． 6. input speed command signal CTL to control signal CTL3. Output as CTL2. Servo section7. , 77 are control numbers CTL, respectively.

CTL, and tacho generators TG,,T which are recursive inputs
Input the output of G2 and motor MI.

M2 is driven in response to the speed command signal CTL.

When motors M, M2 rotate, pulse generator PG
, , PG2 output two-phase pulses S, , S2 consisting of an advance signal A and a lag signal B, respectively, and these two-phase pulses S, , S2 are respectively output from the pulse processing circuits 1 . ．． 1. is input. Pulse processing circuits 12, 1□ are motors M, , M
When 2 is rotating, pulse generator PG,,PG
The two-phase pulses S, S2 output by the motors M, S2 are input, and the direction of rotation of the motors M, M2 is determined based on the logic level of the other with respect to the differential output of either the lead signal A or the delay signal B at the time of rising. , when the rotation is in the positive direction, the rise is advanced and the signal A
Up pulse 10 FB, +FB2 synchronized with the rising edge of
A down pulse -F is output from each output ip, and when the rotation is in the negative direction, the rising pulse progresses and is synchronized with the rising edge of signal A.
B,,-FB.

They are output from the output terminal N, respectively.

The counter 31 receives an up pulse +F via the OR circuit 2.
Input B,, +FB2 to the up count input terminal U, count up pulses 10 FB,, +FB2, and output 2◇ 21.27° 23rd place output terminal Q A as the binary output.
Output to Qa, Qc, and Qo.

The two-phase pulse output circuit has the output of the output terminal Qc as the A phase,
A positive direction two-phase pulse S3, which is the IJF transitive OR phase of the output of the output terminal Q6 and the output of the output terminal Qc, is output to the NC section.

On the other hand, the counter 32 counts up with the up pulse +FB input to the up count input 6mU via the OR circuit 23, and the counter 32 counts up by the up pulse +FB input to the up count input 6mU via the OR circuit 23. The countdown is performed by the up pulse +FB input to the down count input end via the up pulse 10 FB, and the up pulse +
The difference between FB2 or the output terminal Q A , Q a , Q c
, Q o is output as a binary output. (Here, it is assumed that the rotation angle of motor M is ahead of the rotation angle of motor M2). The D/A converter 4 converts the output of the counter 32 into a D/A and outputs it to the calculation W6+, 62 as an adjustment signal.

Arithmetic unit 6. uses the adjustment signal difference from the speed command signal CTL and outputs it to the servo unit 7I as a control signal CTL.

Arithmetic unit 62 adds adjustment No. 13 to speed command signal CTL and outputs the result to servo section 72 as control signal CTL2. Therefore, the rotational speed of motor M, is different from the rotational speed of motor M2, and the rotational angles of motors M, .

When the speed command signal CTL for rotating the motors M, M2 in the negative direction is output from the NC section, the motors M, M2 start rotating in the negative direction, and the pulse processing circuit 1. ．． 12 are down pulses -FB, respectively.

-FB is output from the output terminal N.

The counter 31 inputs the down pulses -FB+ and -FB2 to the down count input iD via the OR circuit 22, and outputs the negative direction two-phase pulse S3 to the NC section.

The counter 32 inputs the down count input 68D via the OR circuit 24. The down pulse -FB is counted down by the town pulse -FBl, and the down pulse -FB, which is input to the up count input QQU via the OR circuit 23, and the h of the down pulse -FB are output to the D/A converter 4 as a binary output. .

The D/A converter 4 converts the input output of the counter 32 into a D/A converter.
The arithmetic unit 6I converts the signal and uses it as an adjustment signal.

6, output to. Arithmetic units 61 + 62 adjust the input speed command signal CTL with an adjustment signal, and
Control signals CTL, , CT are applied so that the rotation angles of the two rotation angles are the same.
L, are output to servo units 71 and 72, respectively.

Therefore, the two motors M, M2 can be controlled at uniform speed by the NC section that drives one motor, so if the uniform speed control device of the embodiment is used, there is no need to change the conventional N0 section to a dedicated controller. It disappears.

〔Effect of the invention〕

As explained above, the present invention has the following features: a two-phase pulse generation means for outputting one set of two-phase pulses obtained by averaging two sets of two-phase pulses from two sets of two-phase pulses respectively output from a second pulse generator; and two sets of two-phase pulses. By providing a lower adjustment signal output stage and a calculation section that make the number of pulses the same, the NC section that drives one motor can generate two
This has the effect of controlling the speeds of multiple motors at the same speed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the speed constant control device of the present invention, FIG. 2 is a diagram showing a control device that controls one motor,
FIG. 3 is a configuration diagram showing a conventional example. 1. 1. ...Pulse processing circuit, 21.22,23,2. ...OR circuit, 3,. 32・
・・Counter, 4・・・・・・・・・・・・・D/A converter, 5・
・・・・・・・・・・・・・・・Two-phase pulse output circuit, 6
,． 6. ...Performance equipment, 7. 72...Servo section, 10...2-phase pulse generation section, 20...................................1;) Adjustment ,i
No. output section, 30......41 (
Calculation, M, ,M,...Motor, TG,,TG,...Tachogenerator, PG,,PG
,...Pulse generator.

Claims (1)

[Claims] A speed command signal is input from an NC unit that outputs a speed command signal and inputs a two-phase pulse to move the controlled object to a predetermined position, and the first and second pulse generators are connected to each other. The first and second servo parts respectively drive the first and second motors that move the controlled object.
A constant speed control device that outputs a control signal of 1 and outputs a 2-phase pulse to an NC section, the device receives first and second 2-phase pulses from a first and second pulse generator, respectively, and outputs a 2-phase pulse to an NC section. When the second motor is rotating in the positive direction, it outputs an up pulse to its respective first output terminal, and when the motor is rotating in the negative direction, it outputs a down pulse to its respective second output terminal. The first thing to do is
a second pulse processing circuit; and a third pulse having a frequency obtained by averaging the frequencies of the first pulse generator and the second pulse generator from the up pulses or down pulses output from the first and second pulse processing circuits. A two-phase pulse generation means that outputs two-phase pulses to the NC section, and two-phase pulses output from the first and second pulse generators from up pulses or down pulses output from the first and second pulse processing circuits. an adjustment signal output means for detecting a difference in the number of pulses and outputting an adjustment signal based on the difference in the detected number of pulses; A constant speed control device comprising: an arithmetic unit that adjusts an input speed command signal using an adjustment signal and outputs first and second control signals so that the difference in the number of pulses detected by the means is zero.