JPS63254761A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify a manufacturing step, by intentionally increasing the design value of a gate length, and making it possible to form the base region of an NPN transistor, the source region, the drain region and the emitter region of a P-channel MOS transistor, and the source region and the drain region of an N-channel MOS transistor in the same step. CONSTITUTION:When a gate electrode 11 is formed, the length of a gate is made long beforehand in order to suppress the decrease in effective channel length. Thereafter, P-type dopant ions are implanted and diffused. Thus the base region of an NPN transistor and a source region 13, a drain region 113 and a guard band region 14 of a P-channel MOS transistor are formed. Then, N-type dopand ions are implanted and diffused. An emitter region 15, a collector contact region 16 and a bottom gate contact 17 of an NPN transistor and a source region 18 and a drain region 118 of an N-channel MOS transistor are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOS transistor are formed within the same semiconductor substrate.

2. Description of the Related Art A conventional semiconductor integrated circuit in which a bipolar transistor and a CMO8 (complementary MO3) transistor are integrated on the same semiconductor substrate has been formed according to a process flowchart as shown in FIG. The structure of a conventional semiconductor integrated circuit and its manufacturing method will be described below with reference to FIG.

First, as shown in FIG. 2a, an n-type silicon epitaxial layer 4 is formed on a p-type wheel crystal silicon substrate 1 in which an n-type buried region 2.21 and an n-type buried region 3.31 are selectively formed. A p-type isolation region 5 is formed on the n-type buried region 3 and a p-type isolation region 5 is formed on the n-type buried region 3, and a p-well region 6 is formed on the n-type buried region 31 by diffusion of p-type impurities.

Next, as shown in FIG. 2, an n+ channel stop diffusion layer 7 is formed in the region on the n-type epitaxial layer 4 where element isolation is to be formed, and a p+ After forming the channel stop diffusion layer 8,
A thick silicon oxide film 9 is grown by selective oxidation to form element isolation regions.

Next, as shown in FIG. 2C, a thin silicon oxide film 10 is formed to serve as a gate oxide film for a MOS transistor, and a conductive film such as polycrystalline silicon is selectively formed on this to form a gate electrode 11. form. Thereafter, the base region 12. of the NPN transistor is ion-implanted with a p-type dopant. Source region 13 of n-channel MOS transistor. Drain region 113 and guard band region 14 are formed. Also, by ion-implanting an n-type dopant, the emitter region 15 of the NPN transistor. Collector contact area 16. Bottom gate contact region 17. A source region 18° and a drain region 118 of an n-channel MOS transistor are formed. Note that the diffusion depth of the source and drain diffusion layers is 0.6 to 0.7 μ on the p-channel side and 0.3 to 0.4 on the n-channel side, taking the case where the gate length is 3 μ- as an example.
It is about μm.

Finally, as shown in FIG. 2d, after a PSG film 19 serving as an interlayer insulating film is formed on the surface, a contact window is opened and an aluminum electrode 20 is formed in this part.

Problems to be Solved by the Invention In such conventional manufacturing methods, the diffusion depths of the source and drain are designed to be relatively shallow in order to suppress reduction in the effective channel length of the MOS transistor. Therefore, in order to reduce the number of steps, when the source/drain of a p-channel MO8) transistor and the base of an NPN transistor are shared, and the source/drain of an n-channel MOS transistor and the emitter of an NPN) transistor are shared,
There was a problem in that the withstand voltage of bipolar transistors was limited.

Means for Solving the Problem In order to solve this problem, the present invention intentionally increases the design value of the gate length of the MOS transistor, and increases the base diffusion depth and emitter depth in order to improve the withstand voltage of the NPN transistor. Even if the diffusion depth is increased, the base region of the NPN transistor, the source region and drain region of the n-channel MOS transistor, the emitter region and the n-channel MOS transistor
The source region and drain region of the OS transistor are formed in the same process.

Operation With this configuration, the base region of the high voltage bipolar transistor, the source region and drain region of the n-channel MOS transistor, the emitter region and the n-channel MOS
A source region and a drain region of a transistor can be formed in the same process.

Embodiment An embodiment of the semiconductor integrated circuit of the present invention will be described with reference to FIG. First, as shown in FIG. 1A, an n-type buried region 2.21 is formed by selectively doping antimony or arsenic into a p-type crystalline silicon substrate 1. Next, boron is selectively doped to form a p-type buried region 3.31.

Next, an n-type silicon epitaxial layer 4 having a resistivity of 1 to 5 Ωcm is grown over the entire surface in an area of 10 to 20 ua+. Next, boron is selectively doped into the surface portion of the n-type epitaxial layer corresponding to the p-type buried regions 3 and 31, and an isolation region 5 is formed above the p-type buried region 3 to connect thereto.
Furthermore, a p-well region 6 for forming an n-channel MOS transistor is formed on the p-type buried region 31.

Next, as shown in FIG. 1, an n+ channel stop diffusion layer 7 is formed in the region on the n-type epitaxial layer 4 where element isolation is to be formed, and a p+ channel stop diffusion layer 7 is formed in the region where element isolation is to be formed on the p well region 6. After forming the stop diffusion layer 8,
A thick silicon oxide film 9 is grown by selective oxidation to form element isolation regions.

Next, as shown in FIG. 1C, a thin silicon oxide film 10 is formed to serve as a gate oxide film for a MOS transistor, and a conductive film such as polycrystalline silicon is selectively formed on this film to form a gate electrode. 11 is formed. At this time, high voltage NPN
Transistor deep diffusion base emitter and M
OS) Considering that the source and drain of the transistor are shared, the gate length is lengthened in advance to prevent reduction in the effective channel length. At this time, if the base diffusion depth of the NPN transistor is set to 1.0 Um or more and the channel length of the n-channel MOS transistor is set to 3.0 μm, then
The gate length must be 4.5 Um or more. After that, by ion-implanting a p-type dopant and performing a diffusion process, the base region of the NPN transistor with a diffusion depth of 1.0 U- or more is formed into the source region 13° drain region 113 and guard band region of the n-channel MOS transistor. form 14. Next, an n-type dopant is ion-implanted and diffused to form the emitter region 15. of the NPN transistor. Collector contact area 16.
Bottom gate contact 17. n-channel MOS) transistor source region 18. A drain region 118 is formed.

Finally, as shown in FIG. 1d, after a PSG film 19 serving as an insulating film between the eyebrows is formed on the surface, a contact window is opened and an aluminum electrode 20 is formed in this part.

Effects of the Invention As described above, according to the present invention, the base region of a Bi-CMOS integrated circuit including a high voltage NPN transistor, the source and drain regions of an n-channel MOS transistor, and the emitter region and the source and drain regions of an n-channel MOS transistor. Since each can be formed in the same process, the manufacturing process can be simplified and the economic effect is large.

[Brief explanation of the drawing]

1...P-type car crystal silicon substrate, 2, 21...
...N type buried region, 3, 31... N type buried region, 4... N type silicon epitaxial layer, 5... P type isolation region, 6.・・・・・・
p-well region, 7.8... channel stopper region, 9... thick silicon oxide film, 10...
... silicon oxide film, 11 ... gate electrode, 12 ... NPN) transistor base region,
13... Source region of n-channel MOS transistor, 113... Drain region of n-channel MOS transistor, 14... Guard band region, 15... NPN transistor emitter region, 16...collector contact region,
17...Bottom gate contact region, 18.
... Source region of n-channel MOS transistor, 118 ... Drain region of n-channel MOS) transistor, 19 ... PSG film, 20.
...Aluminum electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person Figure

Claims (1)

[Claims] a step of separately forming first and second regions of an opposite conductivity type on a semiconductor substrate of one conductivity type, and forming an oxide film on the surface of the semiconductor substrate; forming a gate electrode with a longer gate length on the oxide film located above, and implanting impurity ions of the same conductivity type as the semiconductor substrate to form a base region in the first region; a step of simultaneously forming source and drain regions in a second region, ion-implanting an impurity of a conductivity type opposite to that of the semiconductor substrate, forming an emitter region in the first region and a source region in the second region; and a step of simultaneously forming a drain region.