JPS6325360B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital waveform generation circuit suitable for use in, for example, a sound source section of an electronic musical instrument, and in particular to a digital waveform generation circuit that prevents aliasing errors that occur when waveform data other than sine waves is handled as waveform data of the digital waveform generation circuit. This relates to a waveform generation circuit. In general, methods for generating digital waveforms can be roughly divided into read-only memory (hereinafter referred to as ROM),
The variable clock method reads out waveform data stored in a random access memory (hereinafter referred to as RAM) or a shift register continuously using a clock corresponding to the musical scale frequency, and the variable clock method reads out waveform data stored in a random access memory (hereinafter referred to as RAM) or a shift register continuously using a clock that corresponds to the musical scale frequency. There is a fixed clock method in which the clock is applied to RAM and the waveform data is read out. Of these two digital waveform generation methods, in the fixed clock method, the sampling clock frequency is
_c and the number of data samples is N, there is a possibility that address skipping occurs and an aliasing error occurs when the generated frequency is greater than _c /N. In order to prevent this error from occurring, there is a method of exchanging data each time according to the frequency of occurrence, but this method requires high-speed transfer and has drawbacks such as the complexity of the device. In view of these points, the present invention provides a digital waveform generation circuit that has a simple configuration and can quickly and reliably prevent aliasing errors. An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. FIG. 1 shows the basic circuit configuration of a digital waveform generating circuit according to the present invention. In FIG. 1, 1 is an input terminal that is connected to a key assigner (not shown) connected to a keyboard, for example, and receives information on the signal waveform to be generated, and 2 is an input terminal that receives information about the signal waveform to be generated. For example, it is a constant setting circuit for setting the addend n (positive integer), channel, and word of 4-bit information. Normally, when it is desired to generate a signal waveform of a desired frequency, let the generation frequency be F, the sampling clock frequency be _c , and the number of operating bits of the accumulator used be B. These and the above addend n can be expressed as in the following equation. A relationship is established. F=n _c /2 ^B ...(1) Therefore, from equation (1) above, if the sampling clock frequency _c and the number of operating bits B of the accumulator are constant, the generation frequency F can be varied by changing the addend n. be understood. For example, when the sampling clock frequency _c is 50 kHz, the number of operating bits B of the accumulator is D ₀ as shown in Figure 2.
~0.04678Hz as being 20 bits of D ₁₉
When it is desired to generate a frequency F of 19.9998 kHz, it is sufficient to set an addend n in the range of 1 to 419430 in the constant setting circuit 2 corresponding to each generated frequency. The addend n determined in this manner is written from the constant setting circuit 2 to the RAM 3. RAM3 corresponds to the above-mentioned Acrymulator, for example 256
×4 bit capacity, timing control circuit 4
The 4-bit information can be written or read simultaneously (in parallel) using an address signal from the memory, and up to 256 sets of 4 bits can be stored. Here, the memory map of RAM3 is configured as shown in Figure 3, and there are multiple channels, for example, 16 channels CH ₀ ~
For CH ₁₅ , each channel occupies 16 addresses, and among them, the first to tenth addresses are actually used. For example, for channel CH ₀ , only addresses 00 to 09 are used, and the remaining addresses 0A to 0F are not used, and the same goes for other channels. Furthermore, each channel is divided into a predetermined number of words, e.g.
Each word is divided into words W ₀ to _{W 4} and two adjacent addresses are assigned to each word. For example, for channel CH ₀ , address 00 and 01 are assigned to word W ₀ , and addresses 02 and 03 are assigned to word W ₁ .
etc. Then, the above-mentioned addend is stored in the first address of the two addresses occupied by each word, and the addend to which the above-mentioned addend is added is stored in the second address. For example, addend 0 is stored in the first address 00 of word W ₀ of channel CH ₀ , and addend 0 is stored in the second address 01. FIG. 4 shows the relationship between the channels and words arranged in the RAM 3 and the sampling clock frequency. That is, assuming that the sampling clock frequency generated by the timing control circuit 4 is 50 kHz, the sampling period is 20 μs as shown in FIG. 4A, so within one period of 20 μs, the sampling clock frequency as shown in FIG. The calculation process is performed on 16 channels from 0 to 15, and the time required for each channel is 1.25 μs. Furthermore, each channel is divided into five words and processed as described above. This state is shown in FIG. 4C, where five words 0 to 4 are each processed in 0.25 μs. Words 0 to 4 to be divided are shown in Figure 4D.
As shown in the figure, each time slot is processed sequentially in four time slots, namely T ₁ , T ₂ , T ₃ and T ₄ , and the processing time required for one time slot is 62.5 ms.
It is. In other words, RAM3 is timing control circuit 4
In response to an address signal from T1, the addend stored in the first half address of a certain word is read in the first time slot _T1 , and
At _T2 , the addend of that word is written to the vacant address from setting circuit 2, and the third time slot is
At _T3 , the summand stored at the second half address of the word is read, and at the fourth time slot _T4 , the result of the summand and the summand added by the adding circuit 5 is added to the second half address above. write to. This operation is repeated in the second word of channel CH ₀ in Figure 3.
In detail for _W1 , RAM3 reads the addend 1 stored at address 02 in the first time slot _T1 , writes the addend 1 stored in address ₀₂ in the second time slot T2, and writes the addend 1 stored in the address 02 in the second time slot T2. Addend 1 stored at address 03 in time slot T ₃ of
is read and the result of addition of addend 1 and summand 1 is written to address 03 in the fourth time slot _T4 . The timing relationship between the signal R/W representing the read/write operation of the RAM 3 and the address signal Ad from the timing control circuit 4 is shown in FIG. 4E. That is, when the address signal _A0 is "0", the RAM3 reads the addend with the R/W signal "1",
Write the addend with “0” and address signal A ₀ is “1”
When the R/W signal is “1”, read the summand,
Write the result of adding the addend and summand with “0”. Then, the RAM 3 repeats the above-described operation for each word of all channels. The summand and summand thus read and written by the RAM 3 are each latched as 4-bit information in the latch circuits 6 and 7. The summand for each word of , the summand of the two uppermost words of the addend, and the addend are latched. That is, in the case of channel CH ₀ , the summands 3 and 4 of words W ₃ and W ₄ are latched in the latch circuit 6, and the words W ₃ and
Addends 3 and 4 of W ₄ are latched in the latch circuit 7. The summand latched by the latch circuit 6 is an address signal A ₀ as shown in FIG. 2 for instantaneously specifying the address of the ROM 8 in which a plurality of waveform data having a predetermined band limit are stored. ~Used as _A7 . As is clear from FIG. 2, these address signals A ₀ to A ₇ are D ₀ handled by RAM 3.
~ _D19 are configured to correspond to the upper bits of the bit configuration, respectively. The above ROM 8 contains, for example, an 8-bit 256-bit analog signal containing harmonic components from a sine wave signal sampled at 50KHz.
Since 8 types of word digital data are stored, the addresses of the 256 words are specified using the address signals A ₀ to _{A 7} . On the other hand, the addend latched by the latch circuit 7 is supplied to a priority encoder 9 for preventing aliasing errors, which will be described later, and this priority encoder 9 is supplied from the latch circuit 7 as shown in FIG. The upper 8-bit addend data is converted into a 3-bit address signal, and eight types of waveform data stored in the ROM 8 are selected. By the way, in the fixed clock system, as mentioned above, if the sampling clock frequency _c is greater than c/N and the generation frequency is greater than _c /N, there is a possibility that a skip may occur in addressing the ROM 8 and an aliasing error may occur. . To prevent this from happening
The waveform data in the ROM 8 can be switched from a waveform containing harmonics to a waveform close to a sine wave according to the addend (3 bits) (bandwidth limitation). Therefore, in the present invention, a plurality of (eight, for example) data banks each having a predetermined band limit are provided in the ROM 8, and these banks are designated by the priority encoder 9. For example, in the accurator bit configuration of D ₀ to _{D 19} as shown in Figure 2, when the sampling clock frequency is 50 kHz, the number of data samples is 128, and the number of data banks is 8, the frequency range for each data bank is It can be set as shown in the table below.

[Table] Therefore, the priority encoder 9 selects whether the most significant bit, which is "1", of the addend supplied from the latch circuit 7 is stored in the ROM 8 by any one of _D12 to _D18 .
The eight data banks are switched every octave. Here, aliasing errors occur above 400 Hz, but data banks 0 and 1 are separated to provide a difference in sound quality. In other words, the ROM 8 uses the output of the latch circuit 6 as an address signal to instantaneously read the waveform data in a predetermined data bank. Tei encoder 9
The data bank is switched to a desired data bank in which no aliasing error occurs by a bank designation signal from the data bank, and the waveform data in that data bank is read out. The waveform data read out from the ROM 8 in this manner is latched for a predetermined period of time by the next-stage latch circuit 10, and after being timed by the clock signal from the timing control circuit 4, is sent to an external circuit. FIG. 5 shows a specific circuit configuration of a digital waveform generating circuit according to the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals and will be explained. In Figure 5, 11 is the above according to the frequency of occurrence.
A gate circuit in which the addend n determined by equation (1) is set; 12 is a comparator for setting each word W in one channel and a plurality of channels CH as 4-bit information, This comparator 12 operates to open the gate of the gate circuit 11 via the OR circuit 13 when a word address signal and a channel address signal from an address counter, which will be described later, match the respectively set word and channel information. At this time, when the word and channel information is set in the comparator 12, that state is represented by the activation signal EN, and when these data are input to the gate circuit 11, this is indicated by the response signal RQ. expressed. Gate circuit 11, comparator 12 and OR circuit 13 correspond to constant setting circuit 2 in FIG. RAM3 has the functions described above and the terminal WE
When the level of the terminal OE is "0", data is written to the position corresponding to the address signal, and when the terminal OE is "0", the recorded data is read. For example, 14 is an oscillator for generating a 4MHz system clock, 15 is a decimal counter, and 16 is a hexadecimal (4-bit) counter.
6 constitutes an address counter. The output of the counter 15 is an address signal for each word in one channel, and the output of the counter 16 is an address signal for a plurality of channels, for example, 16 channels. 17 and 18 are an AND circuit and an OR circuit, respectively, and the AND circuit 17 logically processes the output of the comparator 12 and the output obtained by inverting the output of the counter 15 by the inverter 19, and the output is "0".
When the terminal WE of RAM3 is connected via the OR circuit 18,
is set to 0, and the data from the gate circuit 11, that is, the set addend n, is written into the RAM 3. 20 is a latch circuit for latching the addend corresponding to a predetermined word read when terminal OE of RAM3 is "0"; 21 is a latch circuit for latching the addend corresponding to a predetermined word read when terminal OE of RAM3 is "0";
3 is an addend for adding the summand of the predetermined word read from the addend latched in the latch circuit 20; 22 is a D-type flip-flop circuit for carry saving; The carry signal is fed back to the adder 21 via the flip-flop circuit 22 as a carry signal from the lower order. Adder 21, flip-flop circuit 2
2. Latch circuits 20 and 24 correspond to adder circuit 5 in FIG. 23 is flip-flop 2
This is a NAND circuit for generating two clock pulses, and is generated by logically processing the outputs of the oscillator 14 and counter 15. Reference numeral 24 denotes a latch circuit for latching the result added by the adder 21, and a D-type flip-flop circuit, for example, is used. The result of latch circuit 24 is supplied to a plurality of latch circuits 25, 26, 27 and 28, and is returned to RAM 3 to be written to the address location of the summand of the read word. Latch circuits 25 and 26 correspond to latch circuit 8 of FIG. 1, and latch circuits 27 and 28 correspond to latch circuit 9 of FIG. Therefore, latch circuits 25 and 26 are looking at the summand data, and latch circuits 27 and 28 are looking at the addend data. Reference numeral 29 denotes a decoder for timing whether or not to take in the data of the summand and the addend into the latch circuits 25 to 28 in response to the address signal of the counter 15. In this case, for example, the latch circuit 25 Third
When the address signal corresponds to address 07 of RAM 3 shown in the figure, the summand 3 of word W ₃ is taken in, and when the address signal corresponds to address 09, the latch circuit 26 takes in the summand 4 of word W ₄ and latches it. The circuit 27 receives the addend ₃ of the word W3 when the address signal corresponds to address 06, and the latch circuit 2
8 serves to capture the addend 4 of word W ₄ when the address signal corresponds to address 08. That is, latch circuits 25 and 26 latch the addend of the corresponding word when the address signal corresponds to an odd address, and latch circuits 27 and 28 latch the addend of the corresponding word when the address signal corresponds to an even address. Work as you would. The oscillator 14, decimal counter 15, hexadecimal counter 16, decoder 29 and other logic gates correspond to the timing control circuit 4 of FIG. Next, the operation of the digital waveform generating circuit according to the present invention will be explained in detail with reference to FIGS. 3 and 4. Assuming that RAM3 is operated with the memory map shown in Figure 3, first the channel
The addend 0 of word W ₀ of CH ₀ responds to the address signal from the address counter and sets the address of RAM3.
00 to the first time slot _T1 as shown in FIG. 4D and latched into the latch circuit 20. When the address signal from the address counter matches the word and channel information set in the comparator 12, that is, in this case, when channel CH ₀ matches the word W ₀ information, the second time slot shown in FIG. At T ₂ , the addend 0 of the word W ₀ passes through the gate circuit 11 to the address of RAM 3.
Written to position 00. Next, in the third time slot _T3 of _FIG . The adder 21 adds the addend 0 of the word W ₀ latched in the latch circuit 20 and the summand 0 of the subsequently read word W ₀ , and latches this result in the latch circuit 24 at the next stage. . The result stored in the latch circuit 24 is determined by the timing signal from the oscillator 14.
It is written again to address 01 of word W ₀ of RAM3. This operation is repeated for each word of channel CH ₀ in turn. Further, the output of the latch circuit 24 is output from the latch circuit 25.
~28 and latch circuits 25 and 26
latches the summand of the upper word of each channel by the address signal of the upper bit decoded by the decoder 29. In FIG. 5, the latch circuit 25
shows the case where the summand 3 of word W ₃ is latched, and the latch circuit 26 latches the summand 4 of word W ₄ . On the other hand, latch circuits 27 and 28 look at the addend of each word, and use the address signal from decoder 29 to latch the addend of the upper word of each channel. In FIG. 5, latch circuit 27 latches the addend of word _W3 , and latch circuit 28 latches the addend 4 of word _W4 . The outputs of the latch circuits 25 and 26 are sequentially used as instantaneous addresses for reading waveform data stored in advance in multiple data banks of the ROM 8.
The outputs of latch circuits 27 and 28 are supplied to a priority encoder 9 for producing signals for specifying each data bank of ROM8. Priority encoder 9
The data bank of the ROM 8 is switched depending on whether the most significant bit, which is "1", of the addends supplied from the latch circuits 27 and 28 is, for example, one of _D12 to _D18 in the above table, and an aliasing error occurs. Make sure there is no such thing. As a result, the waveform data of the designated data bank is read out from the ROM 8, and then sent out to the outside with timing set by the latch circuit 10. The waveform data read in this way is D/A
After conversion, it may be processed using an analog voltage controlled amplifier (VCA), an envelope generator (EG), etc., or it may be used for an all-digital electronic musical instrument. Note that the waveform data preset in the ROM 8 may be a triangular wave, a sawtooth wave, etc., or a quantized one-cycle portion of an actually recorded musical instrument sound may be used. Further, this waveform data may be only a sine wave, and each channel frequency may be set to a harmonic frequency to provide a sine wave synthesis type sound source device.
In that case, it is possible to include anharmonicity in the harmonics, and to give each harmonic an independent envelope, making it possible to synthesize more natural and diverse tones. As described above, according to the digital waveform generation circuit according to the present invention, a plurality of waveform data banks with a predetermined band limit are provided in advance, and the harmonic components of the generated frequency become high, which may cause address skips and aliasing errors. Since the configuration is configured such that if there is a bank designation signal from the priority encoder, the data is switched to the desired data, aliasing errors can be quickly and reliably prevented, and the configuration can be simplified. The present invention is also useful when it is desired to change the sound quality not only according to the aliasing error but also according to the sound range. Furthermore, since a priority encoder is used, octave detection of the generated frequency and bank switching can be easily performed, and since the switching speed is high, it can sufficiently follow multi-channel multiplexing systems. In the above embodiment, the case where ROM was used for waveform data memory was explained, but it is also possible to use RAM instead of ROM and store its contents separately.
By changing the spectrum over time using CPU control, etc., it is possible to create temporal changes in the generated spectrum. Further, in the above-described embodiment, each bank of waveform data has the same size, but the number of data samples can be reduced in a band-limited bank. In addition, the number of channels of the waveform generator can be further increased if it is possible to increase the calculation speed.
Moreover, since the frequency settings of each channel can be interfaced at low speed, it is possible to design a generator assigner, that is, a circuit that allocates frequencies to a waveform generator using a microprocessor or the like.

[Brief explanation of drawings]

1 to 5 show one embodiment of the present invention, FIG. 1 is a block diagram showing its basic configuration, and FIGS. 2 to 4 are schematic lines for explaining its operation. 5 are block diagrams showing the specific circuit configuration thereof. 2 is a constant setting circuit, 3 is a random access memory (RAM), 4 is a timing control circuit, 5 is an adder circuit, 6, 7, and 10 are latch circuits, 8 is a read-only memory (ROM), and 9 is a priority encoder. be.

Claims (1)

[Claims] 1. The first time slot of the timing control means reads out the addend for frequency setting stored in the first half address, and the second time slot sets the addend to the vacant address. The addend stored in the second half address is read in the third time slot, the summand is added to the summand read out in the fourth time slot, and the addition result is stored in the second half of the address. a second memory having a plurality of waveform data banks with a predetermined band limit; and latching means for latching, which determines the addend of the latching means and switches between a plurality of waveform data banks having different orders of harmonic content in the second memory for each predetermined frequency range, and also switches between a plurality of waveform data banks having different orders of harmonic content in the second memory according to the summand. 1. A digital waveform generation circuit characterized in that waveform data is read by specifying an address in a memory.