JPS63253270A - Reliability evaluating method for semiconductor device - Google Patents
Reliability evaluating method for semiconductor deviceInfo
- Publication number
- JPS63253270A JPS63253270A JP8945087A JP8945087A JPS63253270A JP S63253270 A JPS63253270 A JP S63253270A JP 8945087 A JP8945087 A JP 8945087A JP 8945087 A JP8945087 A JP 8945087A JP S63253270 A JPS63253270 A JP S63253270A
- Authority
- JP
- Japan
- Prior art keywords
- deterioration
- voltage
- drain
- gate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 4
- 238000000034 method Methods 0.000 title description 9
- 230000006866 deterioration Effects 0.000 claims abstract description 34
- 238000011156 evaluation Methods 0.000 claims abstract description 11
- 230000005669 field effect Effects 0.000 claims description 5
- 230000032683 aging Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000012360 testing method Methods 0.000 abstract description 6
- 230000001133 acceleration Effects 0.000 abstract description 3
- 230000035882 stress Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭＯ３型電界効果トランジスタの実動作によ
り近い状態での経時劣化を加速評価するための新規な信
頼性評価方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel reliability evaluation method for accelerated evaluation of aging deterioration of an MO3 field effect transistor in a state closer to actual operation.
従来の技術
ＭＯ３型電界効果トランジスタ（ＭＯＳＦＥＴ）は、素
子の微細化により高密度・高集積化される反面、信頼性
上の様々な問題を生ずる。中でも動作時におけるドレイ
ン近傍の高電界領域で加速され高エネルギーを得たホッ
トキャリアにより引き起こされるホットキャリア劣化は
、素子の微細化を進める上で非常に重要な問題となって
いる。Conventional MO3 type field effect transistors (MOSFETs) have become highly dense and highly integrated due to miniaturization of elements, but on the other hand, various reliability problems arise. Among these, hot carrier deterioration caused by hot carriers that are accelerated and have high energy in the high electric field region near the drain during operation has become a very important problem in advancing the miniaturization of devices.
従来このホットキャリアの評価には、ドレイン電圧一定
のもとてゲートに基板電流が最大となるようなドレイン
電圧の約半分の電圧（例えばドレイン電圧を７Ｖとした
時ゲート電圧は３．５Ｖ）を印加して評価を行っていた
。この方法による試験回路を第５図に示す。ストレスは
、試験に供せられたｎ−ｃｈＭＯＳＦＥＴ１のゲート５
とドレイン４にそれぞれ前述の所定のＤＣ電圧を印加し
て行う。劣化の評価はこの様なストレス印加とその前後
に行うデバイスの特性の測定とを繰り返すことにより特
性の経時劣化を評価する。Conventionally, to evaluate hot carriers, a voltage that is about half the drain voltage (for example, when the drain voltage is 7V, the gate voltage is 3.5V) is used to maximize the substrate current to the gate with the drain voltage constant. was applied and evaluated. A test circuit using this method is shown in FIG. The stress is applied to the gate 5 of the n-ch MOSFET 1 subjected to the test.
This is done by applying the aforementioned predetermined DC voltage to the drain 4 and the drain 4, respectively. Deterioration is evaluated by repeating such application of stress and measurement of device characteristics before and after the application of stress, thereby evaluating the deterioration of characteristics over time.
しかし実際の集積回路ではこの様にゲート電圧がドレイ
ン電圧の約半分の状態は、過渡時において一瞬存在する
だけで実動作時の劣化と同一とは言えない。実際に第６
図に示したようなＣＭＯＳインバータ回路のゲート８に
立ち上がりの異なるパルスを印加してｎ−ｃｈＭＯＳＦ
ＥＴ １の劣化を評価したところ、基板電流の総発生
量が同一になる点でＤＣストレスと比較すると第７図に
示すようにＤＣストレスに比ベパルスを印加した方が劣
化が大きくなる。またこの差はパルスの立ち上がりが急
峻なほど顕著となる。However, in an actual integrated circuit, such a state where the gate voltage is approximately half the drain voltage only exists momentarily during a transient period, and cannot be said to be the same as deterioration during actual operation. Actually the 6th
By applying pulses with different rises to the gate 8 of the CMOS inverter circuit as shown in the figure, the n-chMOSF
When the deterioration of ET 1 was evaluated, when compared with DC stress in that the total amount of substrate current generated was the same, the deterioration was greater when a comparative pulse was applied to DC stress as shown in FIG. Moreover, this difference becomes more pronounced as the rise of the pulse becomes steeper.
発明が解決しようとする問題点
以上述べたように従来のホットキャリア劣化評価法では
ドレイン電圧一定のもとて劣化が最も顕著であるような
ゲート電圧を印加することにより経時劣化の評価を行う
ため実動作での劣化と異なるという問題があった。Problems to be Solved by the Invention As mentioned above, in the conventional hot carrier deterioration evaluation method, aging deterioration is evaluated by applying a gate voltage at which the deterioration is most noticeable while keeping the drain voltage constant. There was a problem that the deterioration was different from that in actual operation.
問題点を解決するための手段
本発明は、上記問題点を解決するためドレインに一定の
電圧を印加した状態で、ゲートに２８１Ｉ類以上の異な
る電圧をステップ的に繰り返し印加することによってホ
ットキャリア劣化の評価を行う。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention solves hot carrier deterioration by repeatedly applying different voltages of 281I class or higher to the gate in a stepwise manner while applying a constant voltage to the drain. Evaluate.
作用
本発明は、上記した方法により実動作に近い状態でＭＯ
Ｓ型電界効果トランジスタのホットキャリア劣化の加速
評価を行うことができる。Effect of the present invention is to perform MO in a state close to actual operation by the method described above.
Accelerated evaluation of hot carrier deterioration of S-type field effect transistors can be performed.
実施例
本発明にもとすく具体的な実施例を図面を用いて説明す
る。第１図は本発明の方法により、ｎ−ｃｈＭＯＳＦＥ
Ｔのホットキャリア評価を行うための回路図を示す。試
験に供せられるｎ−ｃｈＭ ＯＳ Ｆ ＥＴｌのソース
電極２及び基板電極３はグランドに接続し、ドレイン電
極４には外部ＤＣ電源６により例えば７ｖのドレイン電
圧（Ｖｄ）を印加する。ゲート電極５にはプログラマブ
ル電源７により第２図に示したような例えば一方が１．
５Ｖ。Embodiments A specific embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an n-ch MOSFE fabricated by the method of the present invention.
A circuit diagram for performing hot carrier evaluation of T is shown. A source electrode 2 and a substrate electrode 3 of the n-ch MOSFETl to be tested are connected to the ground, and a drain voltage (Vd) of, for example, 7V is applied to the drain electrode 4 by an external DC power supply 6. The gate electrode 5 is connected to a programmable power supply 7 such that, for example, one side is 1.
5V.
他の一つが７ｖのパルスを繰り返し印加する。本実施例
では、ｎ−ｃｈＭＯＳＦＥＴとしてチャンネル長１．Ｏ
ｕｍｓチャンネル幅２０ ｕ ｍ ｓゲート電極はポリ
Ｓｉｓ表面保護膜としてプラズマ窒化膜を用いたトラン
ジスタを使用した。この２種類の興なるゲート電圧は第
３図に示すようにゲート電流として最も大きな正孔（ｈ
ｏｌｅ）電流及び電子（ｅｌｅｃｔｒｏｎ）電流が観測
される２つの電圧として選んだ。これは、実動作ストレ
スの劣化が同一の総基板電流で比較した時ＤＣストレス
に比べ劣化が顕著に現れるのが正孔と電子の注入の繰り
返しがお互いに各々の電荷による劣化を加速させる相乗
効果をもたらすと考えられるからである。The other one repeatedly applies a 7v pulse. In this embodiment, as an n-ch MOSFET, the channel length is 1. O
ums channel width: 20 um s A transistor using a plasma nitride film as a poly-Sis surface protection film was used for the gate electrode. As shown in Figure 3, these two types of gate voltages are the largest hole (h) as the gate current.
ole current and electron current were selected as the two voltages observed. This is due to the synergistic effect of repeated injection of holes and electrons, which accelerates the deterioration caused by each charge. This is because it is thought to bring about
この方法により評価したデバイスの劣化前後のサブスレ
ッシュホールド特性を第４図（ａ）に示す。同図（ｂ）
はドレインに７ｖゲートに３．５Ｖを印加したときの結
果、同図（Ｃ）はＣＭＯＳインバータ回路を構成し立ち
上がり５０ｎｓのパルスストレスを印加したときの結果
である。いずれの結果も基板電流総発生量が同じ点での
劣化を示している。本発明の方法による劣化と（ｃ）の
パルスストレスの劣化とは共にサブスレッシュホールド
スウィングＳの劣化がみられよく似た劣化を示している
ことがわかる。従って本発明の方法が実動作と非常に近
い劣化モードで劣化が引き起こっていると考えられる。The subthreshold characteristics of the device evaluated by this method before and after deterioration are shown in FIG. 4(a). Same figure (b)
(C) is the result when a CMOS inverter circuit is configured and a pulse stress with a rise time of 50 ns is applied. Both results show deterioration at the point where the total amount of substrate current generation is the same. It can be seen that both the deterioration caused by the method of the present invention and the deterioration caused by the pulse stress shown in (c) show similar deterioration, as deterioration of the subthreshold swing S is observed. Therefore, it is considered that the method of the present invention causes deterioration in a deterioration mode that is very similar to the actual operation.
また閾値電圧変動の経時変化を従来のＤＣストレスによ
る試験と比較したとき、本方法のゲート電圧をステップ
的に変化させた方がＤＣストレスに比べ１桁程度劣化が
大きい。Furthermore, when comparing the change in threshold voltage fluctuation over time with a conventional test using DC stress, the stepwise change in gate voltage according to the present method causes about an order of magnitude greater deterioration than the DC stress test.
発明の効果
以上述べたように、本発明特許請求の範囲の方法によれ
ば、従来行われていたＤＣストレスによるホットキャリ
ア劣化に比ベゲート電圧をステップ的に変化させて試験
することにより次のような効果が得られる。Effects of the Invention As described above, according to the method claimed in the present invention, hot carrier deterioration due to DC stress, which has been conventionally performed, can be tested by changing the gate voltage in steps, thereby achieving the following effects. You can get the following effect.
■実動作と非常に近い劣化モードでの経時劣化評価が可
能となる。■It is possible to evaluate deterioration over time in a deterioration mode that is very similar to actual operation.
■ＤＣストレスに比べ同じドレイン電圧のもとでは劣化
の加速性が１桁程度大きくなる。■Compared to DC stress, the acceleration of deterioration is about one order of magnitude greater under the same drain voltage.
第１図は本発明による実施例のホットキャリア評価装置
の構成図、第２図は本発明の実施例のゲートに印加する
ステップ状に変化する電圧波形を示す図、第３図はゲー
ト電圧をゲート電流の関係図、第４図はサブスレッシュ
ホールド特性を示す図、第５図は従来のホットキャリア
評価装置の構成図、第６図はＣＭＯＳインバータ回路に
パルスを印加してホットキャリア評価を行うための回路
図、第７図は第６図の回路に立ち上がりの異なるパルス
を印加したときの基板電流総発生量と劣化量の関係を示
した図である。
１・・・・・・試験に供せられたｎ−ｃｈＭＯ３ＦＥＴ
１６・・・・・・外部電源、７・・・・・・プログラマ
ブル電源代理人の氏名 弁理士 中尾敏男 ほか１名第
１図
ＶｅＣＶ）
第３図
テート電圧、ＶｅＣＶノ
第４図
ケート電圧（Ｖノ
テート電圧 （Ｖ〕
第５図
■
ソ負Ｔｒ容量
第７図FIG. 1 is a block diagram of a hot carrier evaluation device according to an embodiment of the present invention, FIG. 2 is a diagram showing a stepwise changing voltage waveform applied to the gate of an embodiment of the present invention, and FIG. Relationship diagram of gate current, Figure 4 is a diagram showing subthreshold characteristics, Figure 5 is a configuration diagram of a conventional hot carrier evaluation device, and Figure 6 is a diagram showing hot carrier evaluation by applying a pulse to a CMOS inverter circuit. FIG. 7 is a diagram showing the relationship between the total amount of substrate current generated and the amount of deterioration when pulses with different rising edges are applied to the circuit of FIG. 6. 1... n-ch MO3FET used for testing
16... External power supply, 7... Name of programmable power supply agent Patent attorney Toshio Nakao and one other person (Figure 1 VeCV) Figure 3 Tate voltage, VeCV Figure 4 Kate voltage (V Annotated voltage (V) Fig. 5 ■ Solenoid Tr capacity Fig. 7
Claims (2)
特性の経時劣化の評価において、ドレイン電極に一定の
電圧を印加した状態で、ゲート電極に二種類以上の異な
る電圧の間をステップ的に変化する電圧を印加すること
により半導体装置の経時劣化を評価することを特徴とす
る半導体装置の信頼性評価方法。(1) In evaluating the aging deterioration of characteristics during operation of a MOS field effect transistor, a voltage is applied to the gate electrode that changes stepwise between two or more different voltages while a constant voltage is applied to the drain electrode. 1. A reliability evaluation method for a semiconductor device, comprising evaluating the aging deterioration of the semiconductor device by applying .
ドレイン電圧をＶｄ、閾値電圧をＶｔｈとした時、ゲー
ト電極に印加する２種類以上の異なる電圧の内のひとつ
がＶｔｈ〜１／２・Ｖｄ、他のひとつがおよそＶｄであ
ることを特徴とする特許請求の範囲第１項に記載の半導
体装置の信頼性評価方法。(2) In evaluating n-type MOS field effect transistors,
When the drain voltage is Vd and the threshold voltage is Vth, one of two or more different voltages applied to the gate electrode is Vth ~ 1/2 · Vd, and the other one is approximately Vd. A reliability evaluation method for a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8945087A JPH0785098B2 (en) | 1987-04-10 | 1987-04-10 | Semiconductor device reliability evaluation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8945087A JPH0785098B2 (en) | 1987-04-10 | 1987-04-10 | Semiconductor device reliability evaluation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63253270A true JPS63253270A (en) | 1988-10-20 |
| JPH0785098B2 JPH0785098B2 (en) | 1995-09-13 |
Family
ID=13971021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8945087A Expired - Fee Related JPH0785098B2 (en) | 1987-04-10 | 1987-04-10 | Semiconductor device reliability evaluation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0785098B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877419A (en) * | 1996-03-14 | 1999-03-02 | Siemens Aktiengesellschaft | Method for estimating the service life of a power semiconductor component |
| US6628134B1 (en) | 1999-06-30 | 2003-09-30 | Hyundai Electronics Industries Co., Ltd. | DC stress supply circuit |
| JP2011145202A (en) * | 2010-01-15 | 2011-07-28 | Oki Semiconductor Co Ltd | Method of storing test result, method of displaying test result, and test result display device |
| CN105242189A (en) * | 2015-10-13 | 2016-01-13 | 中国人民解放军海军工程大学 | IGBT health state monitoring method based on saturation voltage drop of emitter collector and voidage of solder layer |
-
1987
- 1987-04-10 JP JP8945087A patent/JPH0785098B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877419A (en) * | 1996-03-14 | 1999-03-02 | Siemens Aktiengesellschaft | Method for estimating the service life of a power semiconductor component |
| US6628134B1 (en) | 1999-06-30 | 2003-09-30 | Hyundai Electronics Industries Co., Ltd. | DC stress supply circuit |
| JP2011145202A (en) * | 2010-01-15 | 2011-07-28 | Oki Semiconductor Co Ltd | Method of storing test result, method of displaying test result, and test result display device |
| CN105242189A (en) * | 2015-10-13 | 2016-01-13 | 中国人民解放军海军工程大学 | IGBT health state monitoring method based on saturation voltage drop of emitter collector and voidage of solder layer |
| CN105242189B (en) * | 2015-10-13 | 2018-10-19 | 中国人民解放军海军工程大学 | IGBT health status monitoring methods based on collection emitter-base bandgap grading saturation voltage drop and solder layer voidage |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0785098B2 (en) | 1995-09-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |