JPH0785098B2 - Semiconductor device reliability evaluation method - Google Patents
Semiconductor device reliability evaluation methodInfo
- Publication number
- JPH0785098B2 JPH0785098B2 JP8945087A JP8945087A JPH0785098B2 JP H0785098 B2 JPH0785098 B2 JP H0785098B2 JP 8945087 A JP8945087 A JP 8945087A JP 8945087 A JP8945087 A JP 8945087A JP H0785098 B2 JPH0785098 B2 JP H0785098B2
- Authority
- JP
- Japan
- Prior art keywords
- deterioration
- voltage
- gate
- semiconductor device
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、MOS型電界効果トランジスタの実動作により
近い状態での経時劣化を加速評価するための新規な信頼
性評価方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel reliability evaluation method for accelerated evaluation of deterioration over time in a state closer to actual operation of a MOS field effect transistor.
従来の技術 MOS型電界効果トランジスタ（MOSFET）は、素子の微細
化により高密度・高集積化される反面、信頼性上の様々
な問題を生ずる。中でも動作時におけるドレイン近傍の
高電界領域で加速され高エネルギーを得たホットキャリ
アにより引き起こされるホットキャリア劣化は、素子の
微細化を進める上で非常に重要な問題となっている。2. Description of the Related Art MOS type field effect transistors (MOSFETs) are highly dense and highly integrated due to the miniaturization of elements, but they also cause various reliability problems. In particular, hot carrier deterioration caused by hot carriers accelerated in a high electric field region near the drain during operation to obtain high energy is a very important problem in promoting device miniaturization.
従来このホットキャリアの評価には、ドレイン電圧一定
のもとでゲートに基板電流が最大となるようなドレイン
電圧の約半分の電圧（例えばドレイン電圧を7Vとした時
ゲート電圧は3.5V）を印加して評価を行っていた。この
方法による試験回路を第５図に示す。ストレスは、試験
に供せられたｎ−chMOSFET1のゲート５とドレイン４に
それぞれ前述の所定のDC電圧を印加して行う。劣化の評
価はこの様なストレス印加とその前後に行うデバイスの
特性の測定とを繰り返すことにより特性の経時劣化を評
価する。Conventionally, for evaluation of this hot carrier, a voltage that is about half the drain voltage (for example, the gate voltage is 3.5V when the drain voltage is 7V) is applied so that the substrate current is maximized at the gate under a constant drain voltage. I was doing an evaluation. A test circuit according to this method is shown in FIG. The stress is applied by applying the above-mentioned predetermined DC voltage to the gate 5 and the drain 4 of the n-ch MOSFET 1 used for the test. The deterioration is evaluated by repeating the stress application and the device property measurement before and after the stress application to evaluate the property deterioration over time.
しかし実際の集積回路ではこの様にゲート電圧がドレイ
ン電圧の約半分の状態は、過渡時において一瞬存在する
だけで実動作時の劣化と同一とは言えない。実際に第６
図に示したようなCMOSインバータ回路のゲート８に立ち
上がりの異なるパルスを印加してｎ−chMOSFET1の劣化
を評価したところ、基板電流の総発生量が同一になる点
でDCストレスと比較すると第７図に示すようにDCストレ
スに比べパルスを印加した方が劣化が大きくなる。また
この差はパルスの立ち上がりが急峻なほど顕著となる。However, in an actual integrated circuit, such a state in which the gate voltage is about half of the drain voltage only exists for a moment during the transition, and cannot be said to be the same as the deterioration during actual operation. Actually the 6th
When the deterioration of the n-ch MOSFET 1 was evaluated by applying different rising pulses to the gate 8 of the CMOS inverter circuit as shown in the figure, the total amount of substrate current generated was the same. As shown in the figure, deterioration is greater when a pulse is applied than when DC stress is applied. Further, this difference becomes more remarkable as the rising edge of the pulse becomes steeper.
発明が解決しようとする問題点 以上述べたように従来のホットキャリア劣化評価法では
ドレンイン電圧一定のもとで劣化が最も顕著であるよう
なゲート電圧を印加することにより経時劣化の評価を行
うため実動作での劣化と異なるという問題があった。Problems to be Solved by the Invention As described above, in the conventional hot carrier deterioration evaluation method, the deterioration over time is evaluated by applying the gate voltage at which the deterioration is most remarkable under the constant drain-in voltage. There was a problem that it was different from the deterioration in actual operation.
問題点を解決するための手段 本発明は、上記問題点を解決するためドレインに一定の
電圧を印加した状態で、ゲートに２種類以上の異なる電
圧をステップ的に繰り返し印加することによってホット
キャリア劣化の評価を行う。Means for Solving the Problems In order to solve the above problems, the present invention applies a constant voltage to the drain and repeatedly applies two or more different voltages to the gate in a stepwise manner to degrade hot carriers. Evaluate.
作用 本発明は、上記した方法により実動作に近い状態でMOS
型電界効果トランジスタのホットキャリア劣化の加速評
価を行うことができる。Action The present invention uses the above-described method to perform MOS operation in a state close to actual operation.
Evaluation of hot carrier deterioration of a field effect transistor can be performed.
実施例 本発明にもとずく具体的な実施例を図面を用いて説明す
る。第１図は本発明の方法により、ｎ−chMOSFETのホッ
トキャリア評価を行うための回路図を示す。試験に供せ
られるｎ−chMOSFET1のソース電極２及び基板電極３は
グランドに接続し、ドレイン電極４には外部DC電源６に
より例えば7Vのドレイン電圧（Vd）を印加する。ゲート
電極５にはプログラマブル電源７により第２図に示した
ような例えば一方が1.5V、他の一つが7Vのパルスを繰り
返し印加する。本実施例では、ｎ−chMOSFETとしてチャ
ンネル長1.0um、チャンネル幅20um、ゲート電極はポリS
i、表面保護膜としてプラズマ窒化膜を用いたトランジ
スタを使用した。この２種類の異なるゲート電圧は第３
図よりゲート電流としても最も大きな正孔（hole）電流
が観測された1.5V及び最も大きな電子（electron）電流
が観測されたVdの２つの電圧を選んだ。これらの電圧の
範囲として、正孔電流についてはMOSFETのソース／ドレ
イン間に電流が流れ始める閾値電圧Vthから基板電流が
最大となる1/2・Vdの範囲にあり、電子電流については
ドレイン電流ができるだけ大きく且つドレイン／ゲート
間の電界がVg＞VdであるおおよそVdの近傍に見られる。
これは、実動作ストレスの劣化が同一の総基板電流で比
較した時DCストレスに比べ劣化が顕著に現れるのが正孔
と電子の注入の繰り返しがお互いに各々の電荷による劣
化を加速させる相乗効果をもたらすと考えられるからで
ある。EXAMPLES Specific examples according to the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram for performing hot carrier evaluation of an n-ch MOSFET by the method of the present invention. The source electrode 2 and the substrate electrode 3 of the n-ch MOSFET 1 used for the test are connected to the ground, and a drain voltage (Vd) of, for example, 7V is applied to the drain electrode 4 by the external DC power supply 6. A pulse of, for example, 1.5 V for one side and 7 V for the other one as shown in FIG. 2 is repeatedly applied to the gate electrode 5 by the programmable power supply 7. In this embodiment, the n-ch MOSFET has a channel length of 1.0 μm, a channel width of 20 μm, and a gate electrode made of poly-S.
i, A transistor using a plasma nitride film as the surface protection film was used. The two different gate voltages are the third
From the figure, we also selected two gate currents: 1.5V, where the largest hole current was observed, and Vd, where the largest electron current was observed. The range of these voltages is from the threshold voltage Vth at which the current starts to flow between the source and drain of the MOSFET for hole current to the range of 1/2 Vd at which the substrate current becomes maximum, and for electron current the drain current is The largest possible electric field between the drain and gate is found near Vd, where Vg> Vd.
This is because the deterioration of actual operating stress is more remarkable than that of DC stress when the same total substrate current is compared. The repeated injection of holes and electrons accelerates the deterioration due to each electric charge. Because it is thought to bring.
この方法により評価したデバイスの劣化前後のサブスレ
ッシュホールド特性を第４図（ａ）に示す。同図（ｂ）
はドレインに7Vゲートに3.5Vを印加したときの結果、同
図（ｃ）はCMOSインバータ回路を構成し立ち上がり50ns
のパルスストレスを印加したときの結果である。いずれ
の結果も基板電流総発生量が同じ点での劣化を示してい
る。本発明の方法による劣化と（ｃ）のパルスストレス
の劣化とは共にサブスレッシュホールドスウィングＳの
劣化がみられよく似た劣化を示していることがわかる。
従って本発明の方法が実動作と非常に近い劣化モードで
劣化が引き起こっていると考えられる。Subthreshold characteristics before and after the deterioration of the device evaluated by this method are shown in FIG. The same figure (b)
Shows the result when 7V is applied to the drain and 3.5V is applied to the gate.
It is a result when the pulse stress of is applied. All the results show the deterioration at the same point of the total substrate current generation amount. It can be seen that the deterioration by the method of the present invention and the deterioration of the pulse stress in (c) both show the deterioration of the sub-threshold swing S and show similar deterioration.
Therefore, it is considered that the method of the present invention causes deterioration in a deterioration mode very close to the actual operation.
また閾値電圧変動の経時変化を従来のDCストレスによる
試験と比較したとき、本方法のゲート電圧をステップ的
に変化させた方がDCストレスに比べ１桁程度劣化が大き
い。Also, when comparing the change over time of the threshold voltage fluctuation with the conventional test by DC stress, when the gate voltage of this method is changed stepwise, the deterioration by about one digit is larger than that by DC stress.
発明の効果 以上述べたように、本発明特許請求の範囲の方法によれ
ば、従来行われていたDCストレスによるホットキャリア
劣化に比べゲート電圧をステップ的に変化させて試験す
ることにより次のような効果が得られる。EFFECTS OF THE INVENTION As described above, according to the method claimed in the present invention, by performing the test by changing the gate voltage stepwise as compared with the hot carrier deterioration caused by the conventional DC stress, the following is obtained. Can be obtained.
実動作と非常に近い劣化モードでの経時劣化評価が可
能となる。It is possible to evaluate deterioration over time in a deterioration mode very close to actual operation.
DCストレスに比べ同じドレイン電圧のもとでは劣化の
加速性が１桁程度大きくなる。Under the same drain voltage, the acceleration of deterioration is about an order of magnitude greater than DC stress.
第１図は本発明による実施例のホットキャリア評価装置
の構成図、第２図は本発明の実施例のゲートに印加する
ステップ状に変化する電圧波形を示す図、第３図はゲー
ト電圧をゲート電流の関係図、第４図はサブスレッシュ
ホールド特性を示す図、第５図は従来のホットキャリア
評価装置の構成図、第６図はCMOSインバータ回路にパル
スを印加してホットキャリア評価を行うための回路図、
第７図は第６図の回路に立ち上がりの異なるパルスを印
加したときの基板電流総発生量と劣化量の関係を示した
図である。 １……試験に供せられたｎ−chMOSFET、６……外部電
源、７……プログラマブル電源FIG. 1 is a configuration diagram of a hot carrier evaluation apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing a voltage waveform which changes stepwise applied to a gate according to an embodiment of the present invention, and FIG. 3 is a gate voltage. Relationship diagram of gate current, FIG. 4 is a diagram showing subthreshold characteristics, FIG. 5 is a configuration diagram of a conventional hot carrier evaluation device, and FIG. 6 is a hot carrier evaluation by applying a pulse to a CMOS inverter circuit. Circuit diagram for,
FIG. 7 is a diagram showing the relationship between the total substrate current generation amount and the deterioration amount when pulses with different rising edges are applied to the circuit of FIG. 1 ... n-ch MOSFET used for test, 6 ... external power supply, 7 ... programmable power supply
Claims (1)
ける特性の経時劣化の評価において、前記MOS型電界効
果トランジスタの閾値電圧をVthとし、ドレイン電極に
一定の電圧Vdを印加した時、前記MOS型電界効果トラン
ジスタのゲート電極に、少なくともひとつがVth〜1/2・
Vdであり、もうひとつがVd付近である二種類以上の異な
る電圧の間をステップ的に変化する電圧を印加すること
により半導体装置の経時劣化を評価することを特徴とす
る半導体装置の信頼性評価方法。1. A method for evaluating deterioration of characteristics of a MOS type field effect transistor during operation, wherein the threshold voltage of the MOS type field effect transistor is Vth, and a constant voltage Vd is applied to a drain electrode of the MOS type field effect transistor. At least one of Vth ~ 1/2
Vd, the other is the reliability evaluation of the semiconductor device characterized by evaluating the deterioration with time of the semiconductor device by applying a voltage that changes stepwise between two or more different voltages near Vd. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8945087A JPH0785098B2 (en) | 1987-04-10 | 1987-04-10 | Semiconductor device reliability evaluation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8945087A JPH0785098B2 (en) | 1987-04-10 | 1987-04-10 | Semiconductor device reliability evaluation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63253270A JPS63253270A (en) | 1988-10-20 |
| JPH0785098B2 true JPH0785098B2 (en) | 1995-09-13 |
Family
ID=13971021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8945087A Expired - Fee Related JPH0785098B2 (en) | 1987-04-10 | 1987-04-10 | Semiconductor device reliability evaluation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0785098B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19610065A1 (en) * | 1996-03-14 | 1997-09-18 | Siemens Ag | Method for estimating the lifetime of a power semiconductor device |
| KR100372661B1 (en) | 1999-06-30 | 2003-02-17 | 주식회사 하이닉스반도체 | DC stress circuit for measuring degradation of the device and semiconductor circuit using that |
| JP5394943B2 (en) * | 2010-01-15 | 2014-01-22 | ラピスセミコンダクタ株式会社 | Test result storage method, test result display method, and test result display device |
| CN105242189B (en) * | 2015-10-13 | 2018-10-19 | 中国人民解放军海军工程大学 | IGBT health status monitoring methods based on collection emitter-base bandgap grading saturation voltage drop and solder layer voidage |
-
1987
- 1987-04-10 JP JP8945087A patent/JPH0785098B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| 「ホットキャリア効果」（昭和６２年１２月１５日発行）日経マグロウヒル社Ｗ．Ｗｅｂｅｒ，ＩＥＥＥｅｂｃｔｒｏｍＤｅｖｉｃｅＬｅｔｔｅｒｓ，Ｖｏｌ．ＥＤＬ−５，Ｐ．５１８，１９８４． |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63253270A (en) | 1988-10-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |