JPS63251996A - Timer circuit - Google Patents

Abstract

PURPOSE:To sufficiently largely set a setting time in an allowable scope by connecting a prescribed number of cells for timing having the essentially same capacity structure as the cell capacity for storing the data in the memory cell of a dynamic RAM and forming a capacity for timing. CONSTITUTION:The titled circuit is equipped with a capacity C for timing and a precharging circuit 12 to precharge the capacity C for the timing. Since the capacity C for the timing is formed by using a cell for timing having the essentially same capacity structure as the cell capacity for storing the data in an actual memory cell 20 of a dynamic RAM, the minimum refreshing period requested by the actual memory cell 20 is changed by the temperature change and then, the discharging time constant of the capacity C for the timing at a timer circuit side is changed in the same way as this. Thus, the problem of the refreshing faulty due to the difference in both temperature characteristics does not occur and the setting time of the timer circuit can be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timer circuit for generating a dynamic RAM refresh request signal.
This invention relates to a technique for appropriately setting the set time of a timer circuit.

(Prior art) As is well known, dynamic RAM (hereinafter referred to as rDRA)
I'll call you MJ. ) is a semiconductor memory suitable for a-integration because one memory cell can be configured with one transistor and one capacitor. On the other hand, D.R.A.
In M, it is necessary to refresh the memory words of each memory cell within a predetermined period, and for this purpose, a timer circuit that automatically generates a refresh request signal at predetermined intervals is installed in D.
It is located in RAM.

FIG. 8 is a diagram showing a conventional example of such a timer circuit. In the figure, this circuit has an oscillator 1 composed of a ring oscillator or the like, and this oscillator 1
is the clock pulse φ. is starting to occur. This clock pulse φ. Ha yong f! It is applied to one electrode of IC■. The other electrode of this capacitance C□ is N
Channel type MOS transistor (hereinafter referred to as rNMO8T
Call it J. )2.3. These N.M.O.
3T2.3 functions as a charge pump transistor, as will be understood from the description below.

Among these, the source of NMO8T2 is grounded. On the other hand, the source of NMO8T3 is the timing capacitor ff1CS
□ and NMO8T4, which is used when precharging this capacitor C8□, is connected to a node N8□.

The series connection of this NMO8T4 and the capacitor rIiCS□ is inserted between the power supply line 5 (potential V..) and the ground level, and the gate of NMO8T4 is connected to “ Precharge control signal φ becomes H” level. is given. Furthermore, the above node N
The potential of 3□ is detected by the level detector 6.

Next, the operation of the circuit shown in FIG. 8 will be explained. First, at the time when the previous refresh was started, the precharge control signal φ
. becomes “H” in a pulsed manner, which causes NMO8T
4 is turned on. As a result, the capacity ωC8 from the power line,
A current flows to the capacitor cs■, thereby precharging the capacitance cs■, and the node Ns■ goes to the "H" level. The period until this precharge is completed is determined in advance, and the precharge control signal φ returns to L'' around the time this period elapses.Therefore, from then on, the power supply line 5 and the capacitor ff1c3. It becomes a state of separation.

On the other hand, the clock pulse φ from the oscillator 1. NMO8T3 turns on every time clock pulse φ goes to "L" level. Therefore, every time clock pulse φ goes to "L" level, NMO8T3 turns on. As a result, the potential of the node Ns■ gradually decreases from the "H" level to the ground level.
When the potential of ST becomes equal to or less than a predetermined threshold value set in the level detector 6, the level detector 6 outputs a refresh request signal RQ. This refresh request signal RQ is applied to a refresh control circuit (not shown), thereby executing the next refresh of each memory cell of the desired DRAM. Further, in response to this refresh request signal RQ, a precharge control signal φ is generated. becomes "H" again, and the operation for generating the next refresh request signal is started.

In this way, the refresh request signal RQ is generated periodically, and the generation time interval, that is, the 8th
The set time T of the timer circuit shown in the figure is determined by the discharge time constant of the timekeeping capacitor CS□. This discharge time constant is equal to the clock pulse φ. Node N8□ per cycle of
The amount of potential decrease ΔV and the clock pulse φ. The cycle rate can be adjusted by. Specifically, for example, the capacitance ratio (C3□/C□) is about 40, and the clock pulse φ. If the cycle rate fC of is 4MH2,
The set time T has a value as shown in the ninth factor as a function of temperature. As can be seen from FIG. 9, the set time T in this example is about 10 to 12 μsec at a temperature range of 25° C. to 75° C.

On the other hand, in the case of 64 DRAM, 128 cycles/
The refresh specification is 2 mSec, and during standby, it is necessary to refresh one cycle at a cycle of 16 μsec or less. Based on this condition, the circuit shown in FIG. 8 has a sufficiently small set time T.

However, the memory retention characteristics of DRAMs have greatly improved due to improvements in process technology, reaching 100 m5 ec or more even at high temperatures (approximately 70° C.) and several sec or more at room temperature. Therefore, in refreshing DRAMs in recent years, it is no longer necessary to refresh at a cycle of 16 μsec or less as in the above specifications. In other words, it is not necessary to refresh at the refresh cycle required by the specifications, and it is sufficient to refresh at a longer cycle.

From this point of view, it is possible to lengthen the set time T in the timer circuit shown in Figure 8, and in this way, the power consumption required for refresh operation can be reduced, which is a considerable advantage. Become.

[Problem that the invention seeks to solve]

However, when the set time T of the timer circuit is set to a large value, temperature characteristics become a problem. That is, if the set time T is set to a small value, even if the set time T changes depending on the temperature, there is no fear that the set time T will become longer than the required minimum refresh cycle. On the other hand, if the set time T is set to a large value, the relationship between the set time T and the minimum refresh cycle required by the DRAM memory cell side will be disrupted due to temperature rise, resulting in refresh failure. There is a possibility that it will happen.

For this reason, the conventional timer circuit has a problem in that the set time of the timer circuit cannot be set sufficiently large within the permissible limit due to temperature characteristics.

In addition, in the conventional timer circuit, since the clocking capacitor ff1C8□ is formed by the MO8 capacitor, the clocking capacitor c8.
Another problem was that it required a large area to form.

This invention has been made to solve the above-mentioned problems in the prior art, and is caused by refresh failures caused by the difference in temperature characteristics between the minimum refresh cycle required by the memory cell side of DRAM and the set time of the timer circuit. It is an object of the present invention to provide a timer circuit which can eliminate the possibility of setting a sufficiently large set time within an allowable range, and can reduce the occupied area required for circuit formation. .

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a timer that includes a predetermined timekeeping capacitor, measures time based on the discharge of the timekeeping capacitor, and generates a dynamic RAM refresh request signal when the timekeeping is completed. In the circuit, the time-measuring capacitor is formed by connecting a predetermined number of time-measuring cells having substantially the same capacitance structure as the data storage cell capacitance in the memory cell of the dynamic RAM.

[Effect]

In this invention, since the timekeeping capacitor is formed using a timekeeping cell having substantially the same capacitance structure as the data storage cell capacity in the actual memory cell of the DRAM, the actual memory cell is When the minimum refresh period changes due to temperature changes, the discharge time constant of the timer capacitor on the timer circuit side changes in the same way.

Therefore, the problem of refresh failure due to the difference in temperature characteristics between the two does not occur, and the timer circuit can be set for a long time.

Furthermore, when the timekeeping capacitor is formed as described above, the occupied area is also reduced.

〔Example〕

A. - Circuit configuration and general operation of embodiment FIG. 1 is a circuit diagram of a timer circuit which is an embodiment of the present invention. In the figure, this timer circuit includes a time-measuring capacitor C having an internal structure as described later, and a precharge circuit 12 for precharging this time-measuring capacitor C. Furthermore, this timer circuit has a node N
A CMOS inverter 15 is provided as a level detection circuit that detects the potential level of the memory, compares it with a predetermined threshold value, and generates a refresh request signal RQ according to the comparison result.

Of these, the precharge circuit 12 has a timekeeping capacitor C
It has a P-channel type MOS transistor (hereinafter referred to as rPMO8TJ) 11 inserted between one electrode of the power supply line 5 and the power supply line 5, and has a precharge control signal φ at its gate. is given. In addition, the timekeeping capacity C
The other electrode of is grounded.

The CMOS inverter 15 has PMO8T13 and NMO8
It is formed by interposing a series connection with T14 between the power supply line 5 and the ground level. And P
The potential of the node N between MO8TI1 and the timekeeping capacitor C is input, and the refresh request signal RQ is taken out from the node N1 between PMO8T13 and NMO8T14.

Therefore, a strobe signal (not shown) [:xt.

A precharge control signal φ is generated every time RAS operates. but"
When LIT is reached, PMO8T12 is turned on and the timekeeping capacitor C is charged. After that, the precharge control signal φ. returns to “H91,” the timekeeping capacitor C is connected to the power supply line 5.
electrically isolated from the

However, as will be described later, there is a leakage current in the timekeeping capacitor ff1c, and as a result, the charge accumulated in the timekeeping capacitor C is gradually discharged. Then, when the potential of the node N gradually decreases from the "H" level (#vco) immediately after precharging and becomes below the inversion threshold of the CMOS inverter 15, the PMO3T13 turns from off to on, and the NMO8T14 turns on. Changes from on to off. As a result, the potential of node N1 changes from "L" to "H",
Refresh request signal RQ rises and issues a refresh request to a refresh control circuit (not shown). In response to the generation of this refresh request signal RQ, the DRAM is refreshed, and the precharge control signal φ is again set to "L".

B. Structure and characteristics of timekeeping capacitor C Next, the structure and characteristics of the timekeeping capacitor C will be explained.

The timekeeping case IiC in Fig. 1 is based on the characteristics of this
It is formed using substantially the same structure as the data storage cell capacity in the DRAM memory cell to be refreshed. Therefore, first of all, the DR assumed in this example
The AM memory cell structure will be explained. However, since this structure itself is publicly known, an outline will be provided within the scope necessary to explain the correspondence relationship with the timekeeping capacitor C.

FIG. 2 is a partial schematic plan view of the DRAM to be refreshed, and FIG. 3 is an enlarged cross-sectional view taken along the line 2--2 in FIG. In these figures, memory cell 2 of this DRAM
0 is a P-shaped S, M plate 21 (FIG. 3) on the main surface.
+ region 22 and N+ region 23,24. A gate oxide film 25 made of SiO2 is provided on the upper surface of these, and a capacitor gate 26 made of polysilicon and a word line W are provided in this gate oxide film 25.
, W2 are embedded. In the memory cell 20 shown in the right half of FIG. 3, the word line W1 functions as a transformer 77 gate.

Further, the capacitor gate 26 is, for example, (vcc/2
) is held at a potential of

Further, the N+ region 1i123 is connected to the A obit IiB via the contact hole 27 of the S i O 2125. Therefore, by selecting the word line W1 at the time of 1-setting, the region 28 in this memory cell 20 becomes a channel, and the bit #! The charge applied to B moves to N+ region 24. And data storage cell capacity 29
Memory retention is performed by This data storage cell chamber ω29 is formed by both the junction capacitance between the N+ region 24 and the P-type substrate 21, and the capacitance between the N+ region 24 and the capacitor gate 26. In other words, this memory cell 20 performs memory retention using a so-called Hi-C structure.

On the other hand, for such a memory cell, the time measurement capacitor ff1C shown in FIG. 1 is formed by connecting a predetermined number of time measurement cells 30 in parallel via A1 wires 32, as shown in FIG. The number of connected cells is arbitrary, for example about several hundred cells, but in FIG. 4 (and FIG. 6, which will be described later), only four time measurement cells 30 are shown for convenience of illustration.

Further, the above-mentioned AI line 32 corresponds to the first node N in the figure. Roughly speaking, this time measurement capacitor C is provided on the same substrate as the DRAM memory array.

As shown in FIG. 5, which is a cross-sectional view taken along the line v-■ in FIG. 4, each timing cell 30 is formed on the same substrate as the P-type substrate 21 in FIG. 26
and a gate oxide film 25 are provided in the same positional relationship as the memory cell 20 of FIG. However, since the clock cell 30 in FIG. 5 is not used as a memory, the memory cell 20 in FIG. 3 does not have the transfer transistor required. Specifically, the word lines W and W2 in FIG. 3 do not exist, and the region 2 that should be a channel
Since there is no need to provide 8, the N+ region 23.2 in FIG.
4 are connected to form an N+ region 31.

Therefore, although the entire timing cell 30 in FIG. 5 is not completely the same as the memory cell 20 in FIG. 3, the capacitance structure of the cell capacitor 33 included in the timing cell 30 is This means that the capacitance structure is substantially the same as that of the cell capacitor 29.

That is, the cell capacitance 33 in FIG. 5 performs a charge retention function by ■ junction capacitance between the N+ region 31 and P+ region 22, and ■ capacitance between the N1 region 31 and the capacitor gate 26. . Note that the same potential as the capacitor gate 26 in the memory cell 20 is applied to the capacitor gate 26 in the clock cell 30.

Therefore, even if the memory retention time (therefore, the minimum refresh period) of the memory cell 20 changes due to a temperature change, the same change occurs in the timekeeping capacitor C. Specifically, ■ the speed at which the charge held in the data storage cell capacitor 29 is gradually lost due to junction leakage, punch-through, tail current, etc., and ■ the timekeeping capacitor flC.
The speed at which the charge held in the cell capacitor 33 contained in the cell capacitance 33 is lost due to similar causes is the same regardless of the temperature. This is because the degree of miniaturization, applied voltage conditions, and structural stress are all the same. As a result, for example, when the memory retention time of the memory cell 20 becomes shorter, the rate of potential drop at the node N in FIG.
will be output.

Therefore, with this timer circuit, it is possible to set the set time T to be sufficiently large within the allowable limits. This set time T depends on the number of time measurement cells 30 to be connected and C
The threshold value may be set by appropriately selecting the threshold value of the MOS inverter (level detection circuit) 15.

Furthermore, since the area occupied by the memory cell 20 is small, the area occupied by the timekeeping capacitor C as a set of timekeeping cells 30 formed correspondingly is also small.

By the way, 1. In this embodiment, as shown in FIG. 4, a predetermined number of time-measuring cells 30 forming a time-measuring capacitor C are surrounded by auxiliary cells 40 having the same structure. Of these auxiliary cells 40, N+ in FIG.
In the area corresponding to area 31, AI line 41.4 in FIG.
A ground potential is applied via 2. By doing this, the timekeeping cell 30 that goes to "H" level during precharging is surrounded by the accompanying cells 40 that go to "HIGH" level, and discharge (leakage current, etc.) from the timekeeping cell 30 is prevented. be accelerated. In other words, the timing cell 30
is considered to be the worst bias condition. As a result, the refresh request signal RQ is generated in accordance with the memory retention characteristic of the cell with the shortest memory retention time among the memory cells 20, making it possible to further prevent refresh failures from occurring.

Further, as described above, the clock cell 30 and the memory cell 20
is formed on the same chip as PMO8 in FIG.
T11,13 and NMO8TI4 are also formed on this chip. And preferably these PMOs
8T11.13 and NMO8T14 are timing cell 3
Set near 0. By doing so, each of these cells and each MOS transistor will undergo the same temperature change, and the commonality of characteristic changes will become more pronounced.

Next, the threshold value of the CMOS inverter 15 (level detection circuit) shown in FIG. 1 will be explained. As is well known, the data read from the memory cell 20 is detected and amplified by a sense amplifier (not shown), whereas the level drop due to the discharge of the timekeeping capacitor C is detected and amplified by the CMOS inverter 15.
detected by. Therefore, if the sensitivity of the CMOS inverter 15 is made higher than the sensitivity of the sense amplifier,
This means that the refresh request signal RQ can be generated without fail before the potential held in the memory cell 20 becomes below the detection limit of the sense amplifier.

Therefore, in this embodiment, when the minimum refresh period required by the memory cell 20 is 18 eC, the set time T of the timer circuit is 2Q Q m5ec~500
Make it m5ec. Specifically, node N
PMO8T13 and N M depending on the voltage drop characteristics of
The transistor size of the OS T1'4 is appropriately selected, and the threshold value is set so that the above-mentioned set time T can be obtained.

Fig. 6 is a partial schematic diagram showing an example in which another structure is used for the timekeeping term ff1c in Fig. 1, and Fig. 7 is an enlarged sectional view taken along the line -■. In this embodiment, a predetermined number of time measurement cells 50 are arranged and connected by an AI line 52, and this AI line 52 is defined as a node N, but no accompanying cells are provided. The structure of the timing cell 50 is the same as that shown in FIG. 5, and the cell capacity shown in FIG. 7! I51 corresponds to the cell capacity 33 in FIG.

Thus, even without imposing worst-case bias conditions,
The effects of this invention can be obtained.

Note that in each of the above embodiments, the number of time measurement cells 30, 50 connected is arbitrary, but the memory cell 2
When there is a large variation in the minimum refresh period required by each of the clock cells 30.5, a relatively large number of clock cells 30.5
By connecting 0, these minimum refresh periods can be monitored more accurately. Conversely, when the variation in the minimum refresh period is small, it is sufficient to connect a relatively small number of time measurement cells 30.50.

In addition, although the above embodiment assumes a DRAM using a one-transistor cell as a DRAM, other DRAMs such as a DRAM using a three-transistor cell or a four-transistor cell may also be used.
The timer circuit of the present invention can also be used in M. The structure of the cell capacitor may also be other than the Hi-C structure as in the above embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, the temperature change in the characteristics of the timekeeping capacitor in the timer circuit is the same as the temperature change in the characteristics of the data storage cell capacitor in the memory cell. The set time can be set sufficiently large within the allowable range without causing refresh failure due to the difference in temperature characteristics between the minimum refresh period and the set time of the timer circuit.

Further, by using a timekeeping cell having a capacitance structure that is substantially the same as the data storage cell capacitance in the memory cell, the area required for circuit formation is also reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a partial schematic diagram showing the structure of a memory cell corresponding to the embodiment, FIG. 3 is an enlarged sectional view taken along line III-III in FIG. 2, and FIG. 5 is a partial schematic diagram showing the structure of the timekeeping capacitor used in the example.
The figures are an enlarged sectional view taken along the line v-■ in FIG. The figure is a circuit diagram of a conventional timer circuit, and FIG. 9 is a diagram showing the temperature characteristics of the set time of the conventional timer circuit. In the figure, C is a timekeeping capacitor, 12 is a precharge circuit, 15 is a CMOS inverter (level detection circuit), and 20
is a memory cell, 30.50 is a clock cell, and RQ is a refresh request signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A timer circuit that includes a predetermined timekeeping capacitor, performs timekeeping based on discharge of the timekeeping capacitor, and generates a refresh request signal for the dynamic RAM when the timekeeping is completed, the timer circuit comprising: 1. A timer circuit characterized in that the timekeeping capacitor is formed by connecting a predetermined number of timekeeping cells having substantially the same capacitance structure as a data storage cell capacitance in a memory cell. (2) Ancillary cells having the same structure are provided around a predetermined number of timekeeping cells forming a timekeeping capacitor,
Claim 1, characterized in that a potential for accelerating the discharge of the time-measuring cell is applied to the auxiliary cell.
Timer circuit described in section.