JPS63250832A - Wire bonding - Google Patents
Wire bondingInfo
- Publication number
- JPS63250832A JPS63250832A JP62087407A JP8740787A JPS63250832A JP S63250832 A JPS63250832 A JP S63250832A JP 62087407 A JP62087407 A JP 62087407A JP 8740787 A JP8740787 A JP 8740787A JP S63250832 A JPS63250832 A JP S63250832A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- wire bonding
- time
- bonding method
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000003822 epoxy resin Substances 0.000 claims abstract description 4
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 4
- 239000002861 polymer material Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229920002050 silicone resin Polymers 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 9
- 229920005989 resin Polymers 0.000 abstract description 9
- 230000002950 deficient Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000007789 sealing Methods 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000007598 dipping method Methods 0.000 abstract description 2
- 230000005764 inhibitory process Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000012423 maintenance Methods 0.000 abstract 1
- 238000009718 spray deposition Methods 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/4569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の組立工程で用いるワイヤボンデ
ィング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wire bonding method used in the assembly process of semiconductor devices.
従来、この種のワイヤボンディング方法に用いる半導体
集積回路用金属細線としてのワイヤは、第２図（ａ）お
よび（ｂ）に符号Ｙで示すように構成されており、金、
アルミニウム、銅あるいはこれらの材料に微量の金属元
素を添加したものが知られている。このワイヤＹの線径
ｄは２５μ〜５０μの寸法に設定されている。Conventionally, wires used as thin metal wires for semiconductor integrated circuits used in this type of wire bonding method have been constructed as shown by the symbol Y in FIGS. 2(a) and 2(b).
Aluminum, copper, or materials in which trace amounts of metal elements are added to these materials are known. The wire diameter d of this wire Y is set to a size of 25μ to 50μ.
このようなワイヤによって第３図に示すようにワイヤボ
ンディングを行うことができる。Wire bonding can be performed using such a wire as shown in FIG.
次に、この種のワイヤポンディングによる半導体装置の
組立方法について説明する。Next, a method for assembling a semiconductor device using this type of wire bonding will be described.
先ず、リードフレーム１のアイランド２上に半導体チッ
プ３を接合する。次に、この半導体チップ３の電極４と
リードフレーム１のインナーリード５とを例えばＡｕ等
のワイヤ６によって接続する。そして、パッケージ（図
示せず）によって半導体チップ３．インナーリード５お
よびワイヤ６を樹脂封止する。First, the semiconductor chip 3 is bonded onto the island 2 of the lead frame 1. Next, the electrodes 4 of this semiconductor chip 3 and the inner leads 5 of the lead frame 1 are connected by wires 6 made of, for example, Au. Then, the semiconductor chip 3. Inner leads 5 and wires 6 are sealed with resin.
このようにして、半導体装置を組み立てることができる
。In this way, a semiconductor device can be assembled.
Ｃ声望が解決しようとする問題点〕
ところで、従来のワイヤボンディング方法においては、
ワイヤ６が導体のみによって構成されているため、第４
図（ａ）および（ｂ）に矢印Ａ、Ｂで示すようにワイヤ
ボンディング時にワイヤ自体がもつ苛撓性によって、ま
た樹脂封止時に樹脂の粘性や流速によってワイヤ６が揺
れ他のワイヤ６あるいは半導体チップ３に接触してしま
い、半導体装置の不良品発生率が高くなるという問題が
あった。By the way, in the conventional wire bonding method,
Since the wire 6 is composed of only a conductor, the fourth
As shown by arrows A and B in Figures (a) and (b), the wire 6 sways due to the flexibility of the wire itself during wire bonding, and due to the viscosity and flow velocity of the resin during resin sealing, causing the wire 6 to sway and cause damage to other wires 6 or semiconductors. There was a problem in that the chip 3 came into contact with the chip 3 and the incidence of defective products in the semiconductor device increased.
また、ワイヤ６が導体のみであることは、ワイヤ６が酸
化等によって変質し易く、長期間に亘り動作上の信頼性
を維持することができないという問題もあった。Further, since the wire 6 is only a conductor, there is a problem that the wire 6 is easily deteriorated by oxidation or the like, and operational reliability cannot be maintained for a long period of time.
本発明はこのような事情に鑑みなされたもので、半導体
装置の不良品発生率を抑制することができると共に、長
期間に亘り動作上の信頼性を維持することができるワイ
ヤボンディング方法を提供するものである。The present invention has been made in view of these circumstances, and provides a wire bonding method that can suppress the incidence of defective products in semiconductor devices and maintain operational reliability over a long period of time. It is something.
本発明に係るワイヤボンディング方法は、半導体集積回
路用ワイヤを溶断することにより先端部を球状に形成し
た後、これら両球状部をリードフレームのインナーリー
ドとアイランド上の半４体チップに接続するワイヤボン
ディング方法であって、予めワイヤを高絶縁性高分子材
料で被覆するものである。In the wire bonding method according to the present invention, a wire for a semiconductor integrated circuit is melt-cut to form a tip portion into a spherical shape, and then both of these spherical portions are connected to an inner lead of a lead frame and a half-quad chip on an island using a wire. This is a bonding method in which the wire is coated in advance with a highly insulating polymeric material.
本発明においては、ワイヤの非接続部分の表面を電気的
に絶縁することができる。In the present invention, the surface of the unconnected portion of the wire can be electrically insulated.
第１図（ａ）、 （ｂｌは本発明に係るワイヤボンディ
ング方法に用いるワイヤを示す平面図と断面図で、同図
以下において第２図〜第４図と同一の部材については同
一の符号を付し、詳細な説明は省略する。同図において
、符号１）で示すものは前記半導体チップ３の電極４と
前記リードフレーム１のインナーリード５とを接続する
ワイヤで、前記ワイヤ６と同様金、アルミニウム、ある
いは銅等の金属細線からなり、このうち非接続部分ｔｔ
ａがエポキシ樹脂等の高絶縁性高分子材料１２で被覆さ
れている。FIGS. 1(a) and (bl) are a plan view and a sectional view showing a wire used in the wire bonding method according to the present invention, and in the following figures, the same members as in FIGS. 2 to 4 are designated by the same reference numerals. 1) is a wire that connects the electrode 4 of the semiconductor chip 3 and the inner lead 5 of the lead frame 1, and like the wire 6, it is made of gold. , aluminum, or copper, etc., and the unconnected portion tt
a is coated with a highly insulating polymeric material 12 such as epoxy resin.
このように構成されたワイヤを用いるワイヤボンディン
グは次に示す工程を経て行われる。Wire bonding using the wire configured as described above is performed through the following steps.
先ず、ワイヤー１を浸漬や吹き付は蒸着によってエポキ
シ樹脂からなる高絶縁性高分子材料１２で被覆する。次
いで、ワイヤー１を溶断することにより先端部を球状に
形成する。このとき、ワイヤ１）の球状部には高絶縁性
高分子材料１２が消失して導電部が露呈しており、本発
明はこのところに着目したのである。しかる後、これら
両法状′一
部をリードフレーム１のインナーリード５とアイランド
２上の半導体チップ３に接続する。First, the wire 1 is coated with a highly insulating polymeric material 12 made of epoxy resin by dipping, spraying, or vapor deposition. Next, the wire 1 is cut by melting to form the tip into a spherical shape. At this time, the highly insulating polymeric material 12 disappears from the spherical part of the wire 1) and the conductive part is exposed, and this is the point of focus of the present invention. Thereafter, a portion of both of these curves is connected to the inner leads 5 of the lead frame 1 and the semiconductor chip 3 on the island 2.
このようにして、ワイヤボンディングを確実に行うこと
ができる。In this way, wire bonding can be performed reliably.
この際、本実施例においては、予めワイヤー１を高絶縁
性高分子材料１２で被覆するから、ワイヤ１）の非接続
部分１）ａの表面を電気的に絶縁することができ、ワイ
ヤボンディング時にワイヤ自体がもつ可撓性によって、
また樹脂封止時に樹脂の粘度や流速によってワイヤ１）
が揺れて他のワイヤ１）あるいは半導体チップ３に接触
しても、半導体チップ３とワイヤ１）間２両ワイヤ１）
間の短絡を防止することができる。At this time, in this embodiment, since the wire 1 is coated with a highly insulating polymer material 12 in advance, the surface of the unconnected part 1) a of the wire 1) can be electrically insulated, and during wire bonding Due to the flexibility of the wire itself,
Also, depending on the viscosity and flow rate of the resin during resin sealing, the wire 1)
Even if the wire 1) shakes and comes into contact with another wire 1) or the semiconductor chip 3, the wire 1) between the semiconductor chip 3 and the wire 1)
This can prevent short circuits between the two.
また、ワイヤ１）の非接続部分を高絶縁性高分子材料１
２で被覆することは、導体によってのみ構成されている
ワイヤと比較してそれだけ酸化等の変質を防止すること
ができる。In addition, the unconnected part of the wire 1) is connected to the highly insulating polymer material 1.
Coating with 2 can prevent deterioration such as oxidation to a greater extent than a wire made of only a conductor.
因に、本発明におけるワイヤ６によって半導体装置を組
み立てるには、従来技術と同様にして行うことができる
。すなわち、リードフレーム１のアイランド２上に半導
体チップ３を接合し、次いでこの半導体チップ３の電極
４とリードフレーム１のインナーリード５をワイヤボン
ディングし、しかる後パッケージ（図示せず）によって
半導体チップ３．インナーリード５およびワイヤ１）を
樹脂封止するのである。Incidentally, the semiconductor device can be assembled using the wire 6 in the present invention in the same manner as in the prior art. That is, the semiconductor chip 3 is bonded onto the island 2 of the lead frame 1, then the electrodes 4 of the semiconductor chip 3 and the inner leads 5 of the lead frame 1 are wire-bonded, and then the semiconductor chip 3 is bonded to the island 2 of the lead frame 1 using a package (not shown). ．． The inner leads 5 and wires 1) are sealed with resin.
なお、本発明における高絶縁性高分子材料１２の種類は
前述した実施例に限定されず、例えばポリイミド樹脂、
フッ素樹脂でもよく、その種類は適宜変更することが自
由である。Note that the type of highly insulating polymeric material 12 in the present invention is not limited to the above-mentioned embodiments, and may include, for example, polyimide resin,
It may be a fluororesin, and its type can be changed as appropriate.
以上説明したように本発明によれば、半導体集積回路用
ワイヤを溶断することにより先端部を球状に形成した後
、これら両球状部をリードフレームのインナーリードと
アイランド上の半導体チップに接続するワイヤボンディ
ング方法であって、予めワイヤを高絶縁性高分子材料で
被覆するので、ワイヤの非接続部分の表面を電気的に絶
縁することができる。したがって、ワイヤボンディング
時にワイヤ自体がもつ可撓性によって、また樹脂封止時
に樹脂の粘度や流速によってワイヤが揺れて他のワイヤ
あるいは半導体チップに接触しても、半導体チップとワ
イヤ間９両ワイヤ間の短絡を防止することができる。ま
た、ワイヤの非接続部分を高絶縁性高分子材料で被覆す
ることは、淳体によってのみ構成されているワイヤと比
較してそれだけ酸化等の変質を防止することができ、長
期間に亘り動作上の信頼性を維持することもできる。As explained above, according to the present invention, the tip of a semiconductor integrated circuit wire is formed into a spherical shape by fusing, and then the wire is connected to the inner lead of the lead frame and the semiconductor chip on the island. In this bonding method, the wire is coated with a highly insulating polymer material in advance, so that the surface of the unconnected portion of the wire can be electrically insulated. Therefore, even if the wire sways due to the flexibility of the wire itself during wire bonding or due to the viscosity and flow velocity of the resin during resin sealing and comes into contact with other wires or semiconductor chips, the 9 wires between the semiconductor chip and the wire can prevent short circuits. In addition, coating the non-connected parts of the wire with a highly insulating polymer material can prevent deterioration such as oxidation compared to wires made only of wire, and can operate for a long time. It is also possible to maintain the above reliability.
第１図ｆａ）および（′ｂ）は本発明に係るワイヤボン
ディング方法に用いるワイヤを示す平面図と断面図、第
２図（ａｌおよび（ｂ）は従来のワイヤボンディング方
法に用いるワイヤを示す平面図と断面図、第３図はその
ワイヤを用いる半導体装置の組立方法を説明するための
斜視図、第４図（ａ）および（ｂｌは従来のワイヤの使
用によって組み立てた半導体装置の不良例を示す平面図
と断面図である。
１・・・・リードフレーム、２・・・・アイランド、３
・・・・半導体チップ、５・・・・インナーリード、１
）・・・・ワイヤ、ｌｌａ・・・・非接続部分。FIGS. 1 fa) and ('b) are a plan view and a sectional view showing the wire used in the wire bonding method according to the present invention, and FIGS. 2 (al and b) are plan views showing the wire used in the conventional wire bonding method. Fig. 3 is a perspective view for explaining the method of assembling a semiconductor device using the wire, and Fig. 4 (a) and (bl) show an example of a defective semiconductor device assembled using conventional wire. 1 is a plan view and a cross-sectional view showing 1...Lead frame, 2...Island, 3.
... Semiconductor chip, 5 ... Inner lead, 1
)...Wire, lla...Unconnected part.
Claims (4)
端部を球状に形成した後、これら両球状部をリードフレ
ームのインナーリードとアイランド上の半導体チップに
接続するワイヤボンディング方法であって、予め前記ワ
イヤを高絶縁性高分子材料で被覆することを特徴とする
ワイヤボンディング方法。(1) A wire bonding method in which a semiconductor integrated circuit wire is melt-cut to form a spherical tip, and then both spherical portions are connected to an inner lead of a lead frame and a semiconductor chip on an island. A wire bonding method characterized by coating a wire with a highly insulating polymer material.
請求の範囲第１項記載のワイヤボンディング方法。(2) The wire bonding method according to claim 1, wherein the highly insulating polymeric material is a silicone resin.
求の範囲第１項記載のワイヤボンディング方法。(3) The wire bonding method according to claim 1, wherein the highly insulating polymeric material is an epoxy resin.
の範囲第１項記載のワイヤボンディング方法。(4) The wire bonding method according to claim 1, wherein the highly insulating polymeric material is a fluororesin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62087407A JPS63250832A (en) | 1987-04-08 | 1987-04-08 | Wire bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62087407A JPS63250832A (en) | 1987-04-08 | 1987-04-08 | Wire bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63250832A true JPS63250832A (en) | 1988-10-18 |
Family
ID=13914021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62087407A Pending JPS63250832A (en) | 1987-04-08 | 1987-04-08 | Wire bonding |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63250832A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08316264A (en) * | 1996-04-05 | 1996-11-29 | Hitachi Ltd | Semiconductor device and its manufacture |
| JP2009530842A (en) * | 2006-03-23 | 2009-08-27 | 台灣積體電路製造股▲ふん▼有限公司 | Electrically reinforced wire bond package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113234A (en) * | 1980-12-29 | 1982-07-14 | Seiko Epson Corp | Structure of bonding wire |
| JPS57162438A (en) * | 1981-03-31 | 1982-10-06 | Nec Home Electronics Ltd | Bonding wire and wire bonding |
| JPS59154054A (en) * | 1983-02-23 | 1984-09-03 | Hitachi Ltd | Wire and semiconductor device using it |
-
1987
- 1987-04-08 JP JP62087407A patent/JPS63250832A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113234A (en) * | 1980-12-29 | 1982-07-14 | Seiko Epson Corp | Structure of bonding wire |
| JPS57162438A (en) * | 1981-03-31 | 1982-10-06 | Nec Home Electronics Ltd | Bonding wire and wire bonding |
| JPS59154054A (en) * | 1983-02-23 | 1984-09-03 | Hitachi Ltd | Wire and semiconductor device using it |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08316264A (en) * | 1996-04-05 | 1996-11-29 | Hitachi Ltd | Semiconductor device and its manufacture |
| JP2009530842A (en) * | 2006-03-23 | 2009-08-27 | 台灣積體電路製造股▲ふん▼有限公司 | Electrically reinforced wire bond package |
| US8203219B2 (en) | 2006-03-23 | 2012-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrically enhanced wirebond package |
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