JPS63250248A - Polyphase phase demodulator - Google Patents

Polyphase phase demodulator

Info

Publication number
JPS63250248A
JPS63250248A JP8423087A JP8423087A JPS63250248A JP S63250248 A JPS63250248 A JP S63250248A JP 8423087 A JP8423087 A JP 8423087A JP 8423087 A JP8423087 A JP 8423087A JP S63250248 A JPS63250248 A JP S63250248A
Authority
JP
Japan
Prior art keywords
signal
phase
control signal
multiplier
wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8423087A
Other languages
Japanese (ja)
Inventor
Toshiya Uchino
内野 敏哉
Hideki Nakamura
中村 日出記
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8423087A priority Critical patent/JPS63250248A/en
Publication of JPS63250248A publication Critical patent/JPS63250248A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To enhance the improvement of the S/N of a service channel (SC) signal by sampling only signal in a specified part of a control signal generated by multiplying a base band signal obtained by DC-AC detecting a polyphase phase modulated wave and adding it to a voltage controlled oscillation part. CONSTITUTION:In the case of transmitting the service channel(SC) signal such as an order signal and a monitoring signal, etc., only control signal in the specified part, that means the part of a normal phase state, of the control signal is sampled by a sampling means 4 by using a clock outputted from a multiplier 3 in order to be added to the voltage controlled oscillator 2. Therefore the C/N of the control signal can be improved. Thus, the S/N of the SC signal and the deterioration of the error rate of a main signal can be improved.

Description

【発明の詳細な説明】 〔概要〕 多相位相復調器において、多相位相変調波を直交検波し
て得られたベースバンド信号を、逓倍して生成した制御
信号のうちの所定部分の信号のみをサンプリングして電
圧制御発振部に加えることにより、該制御信号のC/N
の改善を図る様にしたものである。
[Detailed Description of the Invention] [Summary] In a polyphase phase demodulator, only a predetermined portion of a control signal generated by multiplying a baseband signal obtained by quadrature detection of a polyphase phase modulated wave is generated. By sampling and applying it to the voltage controlled oscillator, the C/N of the control signal is
The aim is to improve this.

〔産業上の利用分野〕[Industrial application field]

本発明は多相位相復調器1例えばディジタル多重無線装
置に使用する多相位相復調器の改良に関するものである
The present invention relates to an improvement of a polyphase phase demodulator 1, for example, a polyphase phase demodulator used in a digital multiplex radio device.

マイクロ波を用いたディジタル多重無線方式で打合せ信
号、監視信号などのサービスチャンネル信号(以下、S
C信号と省略する)を伝送する際には、送信側では搬送
波をSC信号で浅く周波数変調した後、更に主信号で例
えば4相位相変調して受信側に送出する。
Service channel signals (hereinafter referred to as S
When transmitting a carrier wave (abbreviated as C signal), on the transmitting side, the carrier wave is shallowly frequency modulated with the SC signal, and then further subjected to, for example, four-phase phase modulation with the main signal, and then sent to the receiving side.

受信側では、4相位相復調器で受信した4相位相変調波
(以下、4相PSK波と省略する)から主信号とSC信
号とを取り出すが、この時、 SC信号の信分封雑音比
などの改善を図る必要がある。
On the receiving side, the main signal and SC signal are extracted from the 4-phase phase modulated wave (hereinafter abbreviated as 4-phase PSK wave) received by the 4-phase phase demodulator, but at this time, the signal-to-noise ratio of the SC signal, etc. It is necessary to improve this.

C従来の技術〕 第3図は従来例のブロック図、第4図は第3図中の4逓
倍回路の構成説明図で、第4図(a)は5in2ωtの
出力を得る回路、第4図fb)はcos2ωtの出力を
得る回路を示す。尚、1は直交検波部、2は電圧制御発
振部を示す。
C. Prior Art] Fig. 3 is a block diagram of a conventional example, Fig. 4 is an explanatory diagram of the configuration of the quadrupling circuit in Fig. 3, Fig. 4(a) is a circuit that obtains an output of 5in2ωt, Fig. 4 fb) shows a circuit that obtains an output of cos2ωt. Note that 1 is a quadrature detection section and 2 is a voltage controlled oscillation section.

以下、4相位相変調の場合を例にして第4図を参照して
第3図の動作を説明する。
The operation of FIG. 3 will be described below with reference to FIG. 4, taking the case of four-phase phase modulation as an example.

入力した4相PSK波は同相ハイブリッド11で分配さ
れて同期検波器12.13に加えられるが、ここには電
圧制御発振器(以下、 VCOと省略する)22の出力
が90度ハイブリッド23を介して加えられているので
、同期検波されてIch及びQchのベースバンド信号
が取り出される。
The input 4-phase PSK wave is distributed by the in-phase hybrid 11 and applied to the synchronous detector 12.13, where the output of the voltage controlled oscillator (hereinafter abbreviated as VCO) 22 is transmitted via the 90-degree hybrid 23. Therefore, the Ich and Qch baseband signals are extracted by synchronous detection.

このベースバンド信号は低域通過形フィルタ14及び1
5を通り、一部は増幅器16.17を介して外部に、残
りの部分は4逓倍器3に加えられて4逓倍されるが、こ
の4逓倍器の構成を第4図により概略説明する。
This baseband signal is transmitted through low-pass filters 14 and 1.
5, a part of the signal is sent to the outside via amplifiers 16 and 17, and the remaining part is added to the quadruple multiplier 3 to be multiplied by four.The configuration of this quadruple multiplier will be schematically explained with reference to FIG.

今、ωt Jとすると加法定理により、5in2A= 
 ’A CCs1nA +cosA)”)  ’A C
C5jnA −cosA)”) cos2A=  (cos2八 )   (sin”A
  )の関係があるので、第4図(al、 (b)に示
す回路により入力波の2逓倍波が得られる。そして、こ
の2逓倍波を更に2逓倍回路を通すことにより5in4
Aとcos4Aの4逓倍波が得られ、位相の不確定性が
除去される。尚、絶対値回路は2乗回路として用いられ
る。
Now, if ωt J, then by the addition theorem, 5in2A=
'A CCs1nA +cosA)") 'A C
C5jnA −cosA)”) cos2A= (cos28) (sin”A
), a double wave of the input wave can be obtained by the circuit shown in Fig. 4 (al, (b)).Then, by further passing this double wave through a double multiplier circuit, a 5in4
A quadrupled wave of A and cos4A is obtained, and the phase uncertainty is removed. Note that the absolute value circuit is used as a square circuit.

即ち、4逓倍波5in4ωtミeとすると、eは5in
4(ωct−ωct′+θ、θ。+nπ/2)・・(1
)で表される。
That is, if the 4th harmonic wave is 5in4ωtmye, then e is 5in
4(ωct-ωct'+θ, θ.+nπ/2)...(1
).

ここで、 ωct+ ω、/はそれぞれの搬送波角周波数、θ、は
送信側無変調波の位相、 θ。はVCOの位相、 nπ/2は4相位相変調により変化する位相項で、nは
0.C2,3のうちのランダムな値である。
Here, ωct+ω, / is the respective carrier wave angular frequency, θ is the phase of the unmodulated wave on the transmitting side, and θ. is the phase of the VCO, nπ/2 is the phase term that changes due to four-phase phase modulation, and n is 0. It is a random value among C2 and C3.

又、fl)式の第1項、第2項は周波数差1位相差を示
す項である。
Further, the first and second terms of the formula (fl) are terms indicating a frequency difference of 1 phase difference.

尚、31は減算器、32は加算器、33〜36は絶対値
回路、37.38は差動増幅器を示す。
Note that 31 is a subtracter, 32 is an adder, 33 to 36 are absolute value circuits, and 37 and 38 are differential amplifiers.

この様にして得られた4逓倍波e(以下、制御信号と云
う)はループフィルタ21を通って、一部は増幅器24
を介してSC信号として外部に取り出されるが、残りの
部分はVCO22に加えられて(1)式の周波数差及び
位相差項が0となり、nπ/2の項のみになる様に、即
ち送信側無変調波とVCOの発振周波数が同期状態にな
る様に発振周波数が制御される。
The quadrupled wave e obtained in this way (hereinafter referred to as a control signal) passes through the loop filter 21, and a part of it passes through the amplifier 24.
However, the remaining part is added to the VCO 22 so that the frequency difference and phase difference terms in equation (1) become 0 and only the nπ/2 term remains, that is, the transmitter The oscillation frequency is controlled so that the unmodulated wave and the oscillation frequency of the VCO are synchronized.

又、微分器51.掛算器52は自動周波数制御AFCの
部分で、4逓倍器から出力されるcos4ωtを微分器
51で微分して一4ωsinωLを求め、掛算器52で
制御信号5in4ωtと掛算することにより、同期が外
れた時、入力する4相PSK波とvCOとの周波数差ω
に比例したAFC電圧を取り出し、これでVCOを制御
して同期状態に入る様にする。
Also, the differentiator 51. The multiplier 52 is part of the automatic frequency control AFC, and the cos4ωt output from the quadruple multiplier is differentiated by the differentiator 51 to obtain -4ωsinωL, which is multiplied by the control signal 5in4ωt in the multiplier 52 to eliminate synchronization. At the time, the frequency difference ω between the input 4-phase PSK wave and vCO
An AFC voltage proportional to is taken out and used to control the VCO so that it enters a synchronized state.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ここで、第5図の問題点説明図により問題点を説明する
Here, the problem will be explained with reference to the problem explanatory diagram in FIG.

先ず、第5図(alの4相PSK波の周波数スペクトラ
ム図に示す様にクロック周波数fekが高くなる程、f
、を十fckの点は中間周波数flfより離れるので周
波数スペクトラムは拡散され、単位周波数当りの電力密
度(斜線の部分)は低下するが、逆にfck  が低く
なると電力密度は高くなる。
First, as shown in the frequency spectrum diagram of the four-phase PSK wave in Figure 5 (al), the higher the clock frequency fek, the more f
, fck is away from the intermediate frequency flf, so the frequency spectrum is spread, and the power density per unit frequency (shaded area) decreases, but conversely, as fck decreases, the power density increases.

一方、第3図中(7)VCO22、直交検波器12.1
3、低域通過形フィルタ14.15.4逓倍器3.ルー
プフィルタ21で構成されるループ(以下、自動位相制
御ループと云い、 PLLと省略する)は第5図(al
の点線で示す様にfLfを中心周波数とする帯域通過形
フィルタと考えられるので、ループ内に残留する雑音成
分はfckが低い程、多くなる。
On the other hand, in Fig. 3 (7) VCO 22, quadrature detector 12.1
3. Low-pass filter 14.15.4 Multiplier 3. The loop composed of the loop filter 21 (hereinafter referred to as automatic phase control loop and abbreviated as PLL) is shown in FIG.
As shown by the dotted line, it is considered to be a band-pass filter with fLf as the center frequency, so the lower fck is, the more noise components remain in the loop.

次に、第5図(blの4相PSK波の位相遷移図に示す
様に2例えば位相へからB、BからD2 ・・と1クロ
ツクごとに遷移しているが、遷移時間は無線機の帯域幅
が無限大であれば瞬時に行われるが。
Next, as shown in the phase transition diagram of the 4-phase PSK wave in Figure 5 (bl), there is a transition every clock, for example, from phase to B, from B to D2, etc., but the transition time is the same as that of the radio. If the bandwidth was infinite, it would be instantaneous.

帯域幅が狭くなる程、長くなる。The narrower the bandwidth, the longer it will be.

ここで、無線機は他からの妨害を除去し、又。Here, the radio eliminates interference from other sources and also.

他に妨害を与えない様にする為に帯域幅が制限されてい
るので、遷移時間が長くなり、逓倍器3よりの制御信号
に遷移途中の位相状態が位相誤差信号として入る。
Since the bandwidth is limited in order to prevent interference from others, the transition time becomes long, and the phase state in the middle of the transition is input to the control signal from the multiplier 3 as a phase error signal.

即ち、制御信号中に上記のループ内に残留する雑音成分
と遷移時間が瞬時に行われない為に生じた位相誤差信号
とが含まれ、第5図(C1の時間対制御信号レベル図に
示す様に制御信号のCAMが劣化すると云う問題点があ
る。
That is, the control signal contains noise components remaining in the above loop and a phase error signal generated because the transition time is not instantaneous, and the control signal contains Similarly, there is a problem that the CAM of the control signal deteriorates.

これにともなって、SC信号のS/Nや再生搬送波のC
AMが劣化する。
Along with this, the S/N of the SC signal and the C of the regenerated carrier wave
AM deteriorates.

〔問題点を解決する為の手段〕[Means for solving problems]

上記の問題点は第1図に示す多相位相復調器により解決
される。4は逓倍器3の出力から抽出したクロックを用
いて、制御信号のうちの所定部分の信号のみをサンプリ
ングして電圧制御発振部2に送出するサンプリング手段
である。
The above problems are solved by the polyphase phase demodulator shown in FIG. Reference numeral 4 denotes a sampling means that uses the clock extracted from the output of the multiplier 3 to sample only a predetermined portion of the control signal and sends it to the voltage controlled oscillator 2.

〔作用〕[Effect]

本発明は逓倍器3より出力したクロックを用いでサンプ
リングしてvCOに加える様にして制御信号のCAMを
改善する様にした。
The present invention improves the CAM of the control signal by sampling the clock output from the multiplier 3 and adding it to vCO.

これにより、SC信号のS/N 、主信号の誤り率の劣
化も改善される。
This also improves the deterioration of the S/N ratio of the SC signal and the error rate of the main signal.

〔実施例〕〔Example〕

第2図は本発明の実施例のブロック図を示す。 FIG. 2 shows a block diagram of an embodiment of the invention.

尚、帯域通過フィルタ41.増幅器42.移相器43゜
45及びスイッチ44はサンプリング手段4の構成部分
で、1は直交検波部、2は電圧制御発振部である。又、
全図を通じて同一符号は同一対象物を示す。
Note that the bandpass filter 41. Amplifier 42. The phase shifter 43.degree. 45 and the switch 44 are constituent parts of the sampling means 4, in which 1 is a quadrature detection section and 2 is a voltage controlled oscillation section. or,
The same reference numerals indicate the same objects throughout the figures.

以下、4相PSK波の場合について、第5図(C)を参
照して第2図により本発明の詳細な説明する。
Hereinafter, the present invention will be described in detail with reference to FIG. 2 with reference to FIG. 5(C) for the case of a four-phase PSK wave.

一般に、無線装置は周波数の有効利用を図るために伝送
帯域幅は制限されているので、逓倍器3で直交検波部l
で取り出されたベースバンド信号を4逓倍すると第5図
(C)に示す制御信号が得られる。
Generally, the transmission bandwidth of wireless devices is limited in order to make effective use of frequencies, so the quadrature detection unit l is used in the multiplier 3.
By multiplying the baseband signal extracted by 4 times, the control signal shown in FIG. 5(C) is obtained.

又、逓倍器3の出力を中心周波数がクロック周波数fc
にである帯域通過形フィルタ41を通してクロック成分
を抽出し、増幅器42を用いてクロ・ツクのデユーティ
ファクタを変え、移用器43で位相を調整して、第5図
(C1のA点、B点・・の位置でこのスイッチ44がオ
ンになる様にする。
Also, the center frequency of the output of the multiplier 3 is the clock frequency fc
The clock component is extracted through a band-pass filter 41, the amplifier 42 is used to change the clock duty factor, and the shifter 43 adjusts the phase. This switch 44 is turned on at the position of point B.

そこで、第5図(C)の0クロス点付近、即ち正規の位
相状態の位置付近でのみスイッチがオンになるので、A
点を中心としてクロックの幅分の制御信号がループフィ
ルタ21で保持されてVCO22に加えられて発振周波
数が制御される。
Therefore, since the switch is turned on only near the 0 cross point in FIG. 5(C), that is, near the position of the normal phase state, A
A control signal corresponding to the width of the clock centering on the point is held by the loop filter 21 and applied to the VCO 22 to control the oscillation frequency.

この為、第5図fc)の点線の部分以外の雑音分が制御
信号に含まれないので、制御信号のCAMが改善され、
これに伴ってSC信号のS/Nの劣化や主信号の誤り率
の劣化などが改善される。
Therefore, the control signal does not contain noise other than the part indicated by the dotted line in Fig. 5 fc), so the CAM of the control signal is improved.
Along with this, the deterioration of the S/N of the SC signal and the deterioration of the error rate of the main signal are improved.

尚、スイッチ44としては入力する制御信号をディジタ
ル信号に変換し、更にアナログ信号に変換してVCOに
加える様にしてもよい。
Note that the switch 44 may be configured to convert the input control signal into a digital signal, and further convert it into an analog signal and apply it to the VCO.

この場合、A/D変換する際のクロックの立上り点で制
御電圧をサンプリングすることになるので、上記のクロ
ックの幅分の制御信号をサンプリングする場合に比して
、制御信号に含まれる雑音分が更に減少され、制御信号
のCAMが更に改善される。
In this case, since the control voltage is sampled at the rising point of the clock during A/D conversion, the noise contained in the control signal is is further reduced and the CAM of the control signal is further improved.

上記の説明は4相PSK波で説明したが、8相psに波
、16相PSK波・・に対しても遷移する位相状態が増
えるだけで、それぞれ正規の位相状態の部分の制御信号
をサンプリングすると云うことについては、4相PSK
の場合と全く同様に適用されることは云うまでもない。
The above explanation was made using a 4-phase PSK wave, but for 8-phase PS waves, 16-phase PSK waves, etc., the number of transitional phase states increases, and the control signal of each normal phase state is sampled. Regarding that, 4-phase PSK
Needless to say, it is applied in exactly the same way as in the case of .

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に本発明によれば、VCO制御信
号の劣化が改善されると云う効果がある。
As described in detail above, according to the present invention, there is an effect that deterioration of the VCO control signal is improved.

これにより、SC信号のS/Nの改善等の効果がある。This has the effect of improving the S/N of the SC signal.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理ブロック図、 第2図は本発明の実施例のブロック図、第3図は従来例
のブロック図、 第4図は第3図中の4逓倍回路の構成説明図、第5図は
問題点説明図を示す。 図において 1は直交検波部、 2は電圧制御発振部、 3は逓倍器、 4はサンプリング手段を示す。 不惑fifeQ乏頂グJ7り1y 切trgJ
Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a conventional example, and Fig. 4 is a configuration explanatory diagram of the quadrupling circuit in Fig. 3. , FIG. 5 shows an explanatory diagram of the problem. In the figure, 1 is a quadrature detection section, 2 is a voltage controlled oscillation section, 3 is a multiplier, and 4 is a sampling means. Fuwa fifeQ low top g J7ri1y cut trgJ

Claims (1)

【特許請求の範囲】[Claims] 入力した多相位相変調波を直交検波部(1)で電圧制御
発振部(2)の出力を用いて直交検波し、得られたベー
スバンド信号を出力すると共に、逓倍器(3)で逓倍し
て制御信号を生成し、該制御信号で発振周波数が送信側
無変調波と同期する様に該電圧制御発振部を制御する多
相位相復調器において、該逓倍器(3)の出力から抽出
したクロックを用いて、該制御信号のうちの所定部分の
信号のみをサンプリングして該電圧制御発振部(2)に
送出するサンプリング手段(4)を付加したことを特徴
とする多相位相復調器。
The input polyphase phase modulated wave is quadrature detected by the quadrature detection section (1) using the output of the voltage controlled oscillation section (2), and the obtained baseband signal is output and multiplied by the multiplier (3). In the polyphase phase demodulator, which generates a control signal and controls the voltage-controlled oscillator so that the oscillation frequency is synchronized with the unmodulated wave on the transmitting side, the control signal is extracted from the output of the multiplier (3). A multi-phase phase demodulator characterized in that a sampling means (4) is added that uses a clock to sample only a predetermined portion of the control signal and sends it to the voltage controlled oscillator (2).
JP8423087A 1987-04-06 1987-04-06 Polyphase phase demodulator Pending JPS63250248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8423087A JPS63250248A (en) 1987-04-06 1987-04-06 Polyphase phase demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8423087A JPS63250248A (en) 1987-04-06 1987-04-06 Polyphase phase demodulator

Publications (1)

Publication Number Publication Date
JPS63250248A true JPS63250248A (en) 1988-10-18

Family

ID=13824676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8423087A Pending JPS63250248A (en) 1987-04-06 1987-04-06 Polyphase phase demodulator

Country Status (1)

Country Link
JP (1) JPS63250248A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119853A (en) * 1976-04-01 1977-10-07 Toshiba Corp Automatic phase control circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119853A (en) * 1976-04-01 1977-10-07 Toshiba Corp Automatic phase control circuit

Similar Documents

Publication Publication Date Title
US6195400B1 (en) Two-mode demodulating apparatus
US7203466B2 (en) Transmitting and receiving unit
US4394626A (en) Phase synchronizing circuit
US4591797A (en) PSK demodulator having an AFC circuit
JP3898839B2 (en) Transmitter
JPS63250248A (en) Polyphase phase demodulator
JP3383318B2 (en) Digital modulation wave demodulator
JPH05211535A (en) Afc circuit for demodulator
JPS6225543A (en) Frequency stabilizing system for local oscillator
JPH0541717A (en) Demodulator for digital modulated wave
JPH04269041A (en) Receiver
JPH06237277A (en) Psk carrier signal regenerating device
JPH11122135A (en) Receiver
JPS60218952A (en) Automatic frequency control system
JPH0351125B2 (en)
JP2837915B2 (en) AFC device
JPH0260263A (en) Frequency stabilization circuit for local oscillator used in radio equipment
JPH0654013A (en) Frequency conversion circuit for receiver
JPH066397A (en) Delay detector
JPH0332933B2 (en)
EP0865182A2 (en) Method and apparatus for orthogonal frequency conversion
JPS6330805B2 (en)
JPH06105881B2 (en) Wireless repeater
JPS60200656A (en) Automatic frequency control system
JPH06120992A (en) Demodulation circuit for digital modulation wave