JPS6324838U - - Google Patents

Info

Publication number
JPS6324838U
JPS6324838U JP1986118453U JP11845386U JPS6324838U JP S6324838 U JPS6324838 U JP S6324838U JP 1986118453 U JP1986118453 U JP 1986118453U JP 11845386 U JP11845386 U JP 11845386U JP S6324838 U JPS6324838 U JP S6324838U
Authority
JP
Japan
Prior art keywords
chip component
recess
carrier
mounting structure
component mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986118453U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0438522Y2 (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986118453U priority Critical patent/JPH0438522Y2/ja
Publication of JPS6324838U publication Critical patent/JPS6324838U/ja
Application granted granted Critical
Publication of JPH0438522Y2 publication Critical patent/JPH0438522Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1986118453U 1986-08-01 1986-08-01 Expired JPH0438522Y2 (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986118453U JPH0438522Y2 (en:Method) 1986-08-01 1986-08-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986118453U JPH0438522Y2 (en:Method) 1986-08-01 1986-08-01

Publications (2)

Publication Number Publication Date
JPS6324838U true JPS6324838U (en:Method) 1988-02-18
JPH0438522Y2 JPH0438522Y2 (en:Method) 1992-09-09

Family

ID=31004918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986118453U Expired JPH0438522Y2 (en:Method) 1986-08-01 1986-08-01

Country Status (1)

Country Link
JP (1) JPH0438522Y2 (en:Method)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994029887A1 (fr) * 1993-06-14 1994-12-22 Poripurasuchikkusu Co., Ltd. Piece electrique moulee et sa fabrication
EP3542398A4 (en) * 2016-11-21 2020-12-02 3M Innovative Properties Company AUTOMATIC REGISTRATION BETWEEN CIRCUIT CHIPS AND INTERCONNECTIONS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994029887A1 (fr) * 1993-06-14 1994-12-22 Poripurasuchikkusu Co., Ltd. Piece electrique moulee et sa fabrication
EP3542398A4 (en) * 2016-11-21 2020-12-02 3M Innovative Properties Company AUTOMATIC REGISTRATION BETWEEN CIRCUIT CHIPS AND INTERCONNECTIONS
US10971468B2 (en) 2016-11-21 2021-04-06 3M Innovative Properties Company Automatic registration between circuit dies and interconnects

Also Published As

Publication number Publication date
JPH0438522Y2 (en:Method) 1992-09-09

Similar Documents

Publication Publication Date Title
JPS6324838U (en:Method)
JPS6346844U (en:Method)
JPS6413137U (en:Method)
JPS6379628U (en:Method)
JPH01139418U (en:Method)
JPS6186973U (en:Method)
JPH0327068U (en:Method)
JPS61158955U (en:Method)
JPS63140646U (en:Method)
JPS6429885U (en:Method)
JPS63128737U (en:Method)
JPH0337779U (en:Method)
JPH0165175U (en:Method)
JPH0166763U (en:Method)
JPH02146452U (en:Method)
JPS62135440U (en:Method)
JPH0282127U (en:Method)
JPS6455593U (en:Method)
JPH0317637U (en:Method)
JPH0392086U (en:Method)
JPH0369870U (en:Method)
JPS6350456U (en:Method)
JPS6166973U (en:Method)
JPS62128666U (en:Method)
JPS6170262U (en:Method)