JPS63245111A - Output circuit for automatic fine tuning signal - Google Patents

Abstract

PURPOSE:To enable only one wire enough to be used for giving an automatic fine tuning signal to a microcomputer by outputting the automatic fine tuning signal including an UP signal, a DOWN signal and a horizontal synchronizing detection pulse while being superimposed on a signal. CONSTITUTION:A video intermediate frequency signal outputted from an antenna 1, a tuner 2 and a video intermediate frequency amplifier circuit 3 is inputted to an AFT video circuit 6 on one hand and inputted to a video detection circuit 4 on the other hand. An S-shaped curve detection signal is outputted from the AFT detection circuit 6, compared and collated with prescribed threshold voltages VTH1, VTH2 by a window comparator 7, an UP signal 101 and a DOWN signal 102 are generated and fed to a superimposing circuit 8. A center (fo) area pulse is generated from the UP signal 101 and the DOWN signal 102 inputted from the window comparator 7 by the superimposing circuit 8, outputted as the automatic fine tuning signal 104 and fed to the microcomputer 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an automatic fine tuning signal output circuit, and particularly to an automatic fine tuning signal output circuit for digital tuning in the field of image use including televisions, VTRs, etc. Regarding.

[Conventional technology]

In general, the digital channel selection function used in the field of image utilization such as televisions and VTRs includes, for example, a function that automatically sweeps the local oscillation frequency of a television receiver and detects the frequency (corresponding to the channel) where a broadcast signal is present. , or automatic fine tuning (A) to automatically receive broadcast signals present at pre-offset frequencies.
automaticFine Tuning:hereinafter referred to as AF
(abbreviated as T) function is required.

Conventionally, the AFT function is achieved by detecting two signals: a predetermined S-curve characteristic signal and a horizontal synchronization signal. Since a microcomputer is usually used as a means for detecting these two signals, the two signals mentioned above need to be converted into direct current and input to the microcomputer.

What is shown in FIG. 4 is PLL (Phase L
ockLoop) is a block diagram showing a main part of a video receiving device provided with a conventional AFT function using a channel selection method.

In FIG. 4, a broadcast signal received by an antenna 12 is frequency-converted by a tuner 13 and sent to a video intermediate frequency amplification circuit 14 as a predetermined video signal. The tuner 13 is provided with three predetermined local oscillation circuits, the oscillation frequency of which is controlled and adjusted by a frequency control signal sent from the microcomputer 16. The video signal is amplified in a video intermediate frequency amplification circuit 14, and its output is detected on one side in a video detection circuit 15, and the detected output is outputted via a terminal 54 and sent to a synchronous separation circuit 18. , and the other one is sent to the AFT circuit 17.

In the AFT circuit 17, the video intermediate frequency amplification circuit 14
The video signal inputted from the second
S corresponding to the figure-eight curve characteristic as shown in Figure (a)
A curve detection signal is output. In FIG. 2(a), when the level of the S-curve detection signal is at a level corresponding to area A, it is confirmed that the frequency of the video signal corresponds to the center frequency (fo) area of the broadcast signal. The width of the frequency range is generally 100 to 20
A frequency range of approximately 0 KHz is set.

Further, when the level of the S-curve detection signal is at a level corresponding to region B or region C, the frequency of the video signal corresponds to a higher frequency region or a lower frequency region, respectively. It means.

The S-curve detection signal is A-D converted via a window comparator, output as a pair of binarized level signals, and sent to a microcomputer. Second
Figures (b), (c) and (d) show level signals corresponding to the B region, C region and A region obtained by comparison with the threshold voltages VTHI and V7H2, respectively, in the window comparator. In area B, tJP signal = H level, DOWN
The signal is output as L level, and in C area, U
The P signal is output as L level and the DOWN signal is output as H level.

In addition, as for the horizontal synchronization signal, it passes through the synchronization separation circuit 18 and becomes an unstable signal due to the broadcast signal of a weak electric valve or external noise, so it is logically summed with a stable synchronization signal output from a flyback transformer, etc. , the logical sum signal is converted into a DC signal by an integrator and output as a horizontal synchronization detection pulse.

UP signal and D corresponding to the above S-curve detection signal
The level signal including the OWN signal and the horizontal synchronization detection pulse are each sent to the microcomputer 16 via separate wiring. In the microcomputer 16, the UP signal, DOUN signal and horizontal synchronization detection pulse are processed, automatic fine tuning is performed on the tuner 13, and predetermined digital tuning is executed.

[Problem that the invention seeks to solve]

The above-mentioned conventional circuit for outputting automatic fine-tuning signals of this type requires the UP signal,
It has the disadvantage of requiring three wires for the DOWN signal and the horizontal synchronization detection pulse, and it also requires arithmetic processing of the above three signals within the microcomputer, which reduces the number of terminals on the microcomputer and the complexity of processing. Therefore, there is a drawback that a large amount of built-in ROM must be used.

[Means for solving problems]

The automatic fine tuning signal output circuit of the present invention is used in a video receiving device that receives and demodulates a predetermined video broadcast signal and reproduces video, by inputting a predetermined video intermediate frequency signal and relatively centering the video broadcast signal. Detecting the frequency shift of the video intermediate frequency signal compared to the frequency, the UP signal and the DOWN signal are detected.
means for outputting a level signal including a signal, etc., and means for inputting a video signal generated by detection of the video intermediate frequency signal and a predetermined synchronization pulse supplied from the outside, and outputting a predetermined horizontal synchronization detection pulse. and means for generating and outputting an automatic fine tuning signal for digital tuning by superimposing the level signal and the horizontal synchronization detection pulse.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a video receiving apparatus to which an embodiment of the present invention is applied. As shown in FIG. 1, the automatic fine tuning signal output circuit 11 of this embodiment has an AFT detection circuit corresponding to an antenna 1, a tuner 2, a video intermediate frequency amplifier 3, a video detection circuit 4, and a microcomputer 5. 6, a window comparator 7, a superimposing circuit 8, a synchronization separation circuit 9, and a horizontal synchronization detection circuit 10.

In FIG. 1, one of the video intermediate frequency signals outputted via the antenna 1, tuner 2, and video intermediate frequency amplification circuit 3 is input to the AFT detection circuit 6, and the other is input to the video detection circuit 4. .

In the AFT detection circuit 6, quadrature phase detection is performed as in the conventional example, and an S-curve detection signal is output (see FIG. 2(a)). This S-curve detection signal is sent to the window comparator. 7, is compared with predetermined threshold voltages V7H1 and V7H2, and the second
UP signal 101 shown in Figure (b) and Figure 2 (c)
A DOWN signal 102 shown in is generated, and the superimposition circuit 8
sent to.

On the other hand, in the video detection circuit 4, the input video intermediate frequency signal is detected and a predetermined video signal is sent to the terminal 5.
1 and input to the synchronization separation circuit 9. In the synchronization separation circuit 9, the horizontal synchronization signal is separated from the video signal and output from the terminal 52, and is also input to the horizontal synchronization detection circuit 10. In the horizontal synchronization detection circuit 10, the horizontal synchronization signal and the flyback pulse inputted through the terminal 53 are logically summed, and a horizontal synchronization detection pulse 103 shown in FIG. 2(e) is obtained.
is generated and sent to the superimposition circuit 8.

In the superimposition circuit 8, a center (fo) region pulse shown in FIG. 2(d) is generated from the UP signal 101 and DOWN signal 102 inputted from the window comparator 7, and The horizontal synchronization detection pulse is superimposed and output as an automatic fine tuning signal 104 shown in FIG. 2(f). This automatic fine tuning signal 104 is sent to the microcomputer 5, where it is compared and verified through two threshold voltages VTH3 and VTH4 shown in FIG. A pulse and a horizontal sync detection pulse are detected. These centers (
The fO) area pulse and the horizontal synchronization detection pulse are processed by the microcomputer 5, automatic fine tuning is performed on the tuner 2, and predetermined digital tuning is executed.

〔Effect of the invention〕

As explained above, the present invention provides an automatic fine tuning signal including an UP signal, a DOWN signal, and a horizontal synchronization detection pulse.
By superimposing and outputting the automatic fine tuning signal on one signal, the number of wires for transmitting the automatic fine tuning signal to the microcomputer can be reduced to one, thereby contributing to saving the terminals of the microcomputer and simplifying arithmetic processing. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of a video receiving device to which an embodiment of the present invention is applied, and FIG. 2(a). (b), (c), (d), (e) and (f) are main signal waveform diagrams of each part, and Figure 3 shows the main parts of a conventional video receiving device equipped with an automatic fine tuning function. It is a block diagram. In the figure, 1.12...antenna, 2,13...
Tuner, 3, 14... video intermediate frequency amplification circuit, 4.
15... Video detection circuit, 5, 16... Microcomputer, 6, 17... AFT circuit, 7... Window comparator, 8... Superimposition circuit, 9, 18... Synchronization separation circuit, 10...Horizontal synchronization detection circuit, 11...
Automatic fine tuning signal output circuit. Ki1 Fertilization v-2 times 12A〉 Ana half, Figure 5

Claims (1)

[Claims] In a video receiving device that receives and demodulates a predetermined video broadcast signal to reproduce video, a predetermined video intermediate frequency signal is input, and the video intermediate frequency signal is relatively compared to the center frequency of the video transmission signal. a means for detecting a frequency shift of the signal and outputting a level signal including an UP signal and a DOWN signal, and inputting a video signal generated by detection of the video intermediate frequency signal and a predetermined synchronization pulse supplied from the outside. means for outputting a predetermined horizontal synchronization detection pulse;
An automatic fine tuning signal output circuit comprising: means for generating and outputting an automatic fine tuning signal for digital channel selection by superimposing the level signal and the horizontal synchronization detection pulse.