JPS63244488A - Static type random access memory - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing an electric potential moving circuit for moving the electric potential of a data signal to a high sensitive region of a sense amplifier under the connection between a bit line and the sense amplifier. CONSTITUTION:The electric potential moving circuit 7 is inserted and connected between a write-read circuit 6 and the sense amplifier 8. This electric potential moving circuit 7 keeps the bit line pair 2 and -2 at a high electric potential and input lines 25 and -25 of the sense amplifier at a low electric potential. The reason is that an electric potential of the input lines 25 and -25 of the sense amplifier is suppressed down by more than a threshold voltage of N- channel MOS-FET N31 and N32 by the electric potential moving circuit 7 at the time of read operation, thus keeping a high electric potential of the bit line pair 2 and -2 and a low electric potential of the input lines 25 and -25 of the sensor amplifier. By this method, electric current consumption is hence lessened in the sense amplifier 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a static random access memory.

(Prior Art) FIG. 6 shows a part of a conventional SRAM (static random access memory). As shown in the figure, a large number of static type memory cells 1 are arranged in a matrix. Among these memory cells 1, those arranged in the column direction are connected between respective bit line pairs 2.degree.2 for exchanging data with these memory cells 1. Among the memory cells 1, those arranged in the row direction are connected to each word line 3 for selecting a memory cell.

One end of each bit line pair 2, 2 is precharged. Each bit line pair 2. The other end of 2 is connected to each write/read circuit 6.
and a data input/output terminal 10 via each sense amplifier 8.
The data input/output circuit 9 is connected to the data input/output circuit 9. The write/read circuit 6, the sense amplifier 8, and the data input/output circuit 9 include a control circuit 11 having a control signal input terminal 12.
is connected.

Each word line 3 is connected to a row decoder 14 that selects the word line 3, and the row decoder 14 is connected to an address input circuit 15 having an address input terminal 16. The address input circuit 15 includes bit line pairs 2. A column decoder 17 for selecting 100 is connected, and this column decoder 17
is connected to a write/read circuit 6, and is also connected to a sense amplifier 8 via the write/read circuit 6.

In the SRAM, one of the word lines 3 is selectively driven by the output of the row decoder 14.

The output of the column decoder 17 selectively drives one of the bit line pairs 2, 2 and the sense amplifier 8, respectively. Data input/output is performed between the outside, the write/read circuit 6, and the bit line pair 2, 2 via the data input/output terminal 10. Write/read circuit 6, sense amplifier 8
The data input/output circuit 9 is controlled by the control signal input terminal 1.
This is performed by the control circuit 11 based on the control signal input from the control circuit 2.

Next, the read operation of the SRAM will be explained.

First, in response to a signal from the control signal input terminal 12, the control circuit 11 puts the write/read circuit 6 into a read mode and also puts the sense amplifier 8 into an operating state. The address signal is input to the address input circuit 1 via the address input terminal 16.
Enter 5. From address input circuit 15, a row address signal is output to row decoder 14, and a column address signal is output to column decoder 17. A specific word line 3 is selected by the decoded output of the row decoder 14. A plurality of memory cells 1 in the same row connected to the selected word line 3 are selected. Data in each selected memory cell 1 causes a potential difference between each bit line pair 2.2. Each potential difference is amplified by each sense amplifier 8. Then, bit line pair 2. 2 is selected, and the data of the selected column is outputted to the data input/output terminal 10 by the data input/output circuit 9.

(Problems to be Solved by the Invention) In the conventional SRAM mentioned above, if the potential of bit line pair 2 and 100 is low, the data written in memory cell 1 will be destroyed, so the precharge circuit Bit line pair 2. The battery is kept at a high potential. On the other hand, the sense amplifier 8 connects the sense amplifier input lines 21 . Since the lower the potential of the shore, the better the sensitivity, there is a means for lowering the potential.

That is, the potential of the sense amplifier input lines 211 is set low by a potential moving body (see Figure 2, P-channel MO3 type FETP P5, P6) provided between the bit line pair 2.2 and the ground. . However, if the potential of the sense amplifier input line 21°7 is set to a sufficiently low potential, various problems may occur, for example, the potential of the bit line pair 2, 2 may drop too much and the data written in the memory cell 1 may be destroyed. This also causes problems such as an increase in the amount of current consumed in the potential moving body via the power supply terminal 5, the bit line pair 2.degree.i, and the sense amplifier input lines 25, 2.5.

An object of the present invention is to provide an SRA that can maintain a high bit line potential and maintain a low input potential to a sense amplifier.
The goal is to provide M.

[Structure of the invention]

(Means for Solving the Problems) The SRAM of the present invention includes a plurality of static memory cells for storing data, a bit line for exchanging data between these memory cells, and a plurality of static memory cells on the bit line. a sense amplifier that amplifies data in the memory cell that has appeared; a write/read circuit that writes and reads data to and from the memory cell via the bit line; a word line that selects the memory cell; and a word line that selects the memory cell. In a static random access memory comprising a row decoder for selecting the bit line, a column decoder for selecting the bit line, and an address input circuit for supplying address signals to the row decoder and the column decoder, the bit line and the sense The sensor is configured to include a potential shift circuit connected between the sense amplifier and the potential of the data signal to move the potential of the data signal to a high sensitivity region of the sense amplifier.

(Operation) The read operation is performed as follows. In the read state of the write/read circuit, address signals from the address input circuit are output to the row decoder and column decoder. A word line is selected by the output from the row decoder. A memory cell is selected by the selected word line. The data of the selected memory cell appears on the bit line. The bit line is selected by the output from the column decoder. The potential of the data signal on the selected bit line is
The potential is moved to the high sensitivity region of the sense amplifier by the potential shift circuit. The data signal whose potential has shifted is amplified by a sense amplifier and then read out.

(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

The SRAM shown in FIG. 1 differs from the SRAM shown in FIG.
The point is that a potential transfer circuit 7 is inserted and connected between the two. This potential shift circuit 7 maintains the bit line pair 2, 2 at a high potential,
This is to keep the 211 sense amplifier input lines at a low potential. In FIG. 1, the other configurations are the same as in FIG. 6. Components that are the same as those in FIG. 6 are given the same reference numerals, and their explanation will be omitted.

The operation of the SRAM shown in FIG. 1 is almost the same as the conventional SRAM shown in FIG. The difference between the two operations is that during a read operation, the potential shift circuit 7 changes the potential of the sense amplifier input line 25.25 to the N-channel MOS.
Type FETN31. The advantage is that the threshold voltage of N32 can be suppressed to two levels. bit line pair 2. The potential of 100 is high, and the potential of sense input line 25.25 is kept low.

Since the potential of the 252 sense amplifier input lines is kept low, the current consumed within the sense amplifier 8 is also reduced.

FIG. 2 shows details of the portion surrounded by the chain line in FIG. 1.

As shown in the figure, the precharge circuit 4 includes a power supply terminal 5
and bit line pair 2. A pair of P-channel MO8 type FETs P, , P2 are connected between the gates of the MO8 type FETs P2 and P2, and their gates are both grounded. FETP
1 and P2 transmit the potential of the power supply terminal 5 to the bit line pair 2.degree.2 during a read operation.

The memory cell 1 includes a flip-flop FF and an inversion N-channel MO8 type FET N31N4. The flip-flop FF is an N-channel MO8 type FET N1. N2
and a high resistance load R1°R. Reverse FETN
3. One end of N4 is connected to either bit line pair 2, 2, and their gates are connected to word line 3.

The write/read circuit 6 includes an N-channel MO3 type FET N3. whose source is connected to the bit line pair 2, 2. N6.
Equipped with P-channel MO8 type FETP P3°P4. FE
TN3. Write signal lines 22 and 22 of the control circuit 11 are connected to the drain of N6. FETN3. The output line 23 of the column decoder 17 and the inverter ■ are connected to the gate of N6.
1 is connected. The output line of inverter 11 is FET
P3. Connected to the gate of P4. These FETs
P3. The input line 24 of the potential transfer circuit 7 is connected to the drain of P4.
．． 24 are connected.

The potential transfer circuit 7 is an N-channel MO3 type FET N31"
32. FETN31. The source and gate of N32 are connected to the input lines 24 and 24 of the potential shift circuit 7, and the drain is connected to the sense amplifier input line 25.25. This makes FETN5L.

N32 functions to suppress the potential of the sense amplifier input line 25.25.

The sense amplifier 8 is a P-channel MO3 type FETP for further lowering the potential of the sense amplifier input line 25°25.
5. Equipped with P6.

FETP5. The source of R6 is the sense amplifier power line 25.
25, and its gate and drain are grounded.

Also, the P channel M whose source is connected to the power supply VDD
O3 type FETP7. Equipped with R8. The drain of FETP7 is FETP7. It is connected to the gate of R8 and the source of N-channel MO3 type FET N7. The drain of the P-channel MO3 type FET P8 is connected to the data input/output circuit 9.
sense amplifier output line 26 and N-channel MO3 type F
It is connected to the source of ETN3. FETNr,
Ng functions as an input transistor. N
The gate of the channel MO3 type FET N7°Ng is connected to the sense amplifier input line 25.25. FETN7
．． The drain of Ng is an N-channel MO8 type FET N9. as a sense amplifier control transistor. It is connected to the source of N, . FETN9. The gate of N1o is connected to the sense amplifier control line 27 from the control circuit 11. FETN9. Between the drain of N1o and the ground, there is an N-channel MO3 type FET whose gate is connected to the power supply.
The source and drain of N11 are connected.

In FIG. 2, during the read operation of the write/read circuit 6, when the word line 3 is selected by the row decoder 14, the N-channel MO3 type FET N3. The data signal stored in the flip-flop FF via N4 is transferred to the bit line pair 2. Appears in f. This data signal is obtained as a high potential signal by the precharge circuit 4. The high potential data signal appearing on the bit line pair 2.2 is transferred to the input line 24 of the potential shift circuit 7 via the write/read circuit 6.
．． It will be reported on 24th. This high potential data signal is sent to the N-channel MO3 type FE T N 31. of the potential shift circuit 7.
N32 appears on the sense-up input line 25.25 as a low potential. Sense up input line 25.2
5 is the P channel MO8 type F in the sense amplifier 8.
ETP5. Since R6 is connected, these P
Channel MO8 type FETP5. The potential is further reduced by R6. As a result, the potential of the sense amplifier input line 25°25 is set to N-channel MO3 type FET N7°Ng.
The threshold voltage of the device is kept low. A control signal from the control circuit 11 is input to the sense amplifier control line 27.
The channel MO8 type FET N9°NIo puts the sense amplifier 8 into the operating state. As a result, data is sent from the sense amplifier output line 26 to the data input/output circuit 9.

In this way, during the read operation, the potential shift circuit 7
As a result, the potential of the bit line pair 2, 2 is held high, and the potential of the sense amplifier input lines 25, 25 is obtained as a low potential. Since the potential of the sense amplifier input line 25.25 is low, the P channel MO8 type F in the sense amplifier 8
The current consumed in ETP5°R6 is small.

3 to 5 show different examples of potential shift circuits.

The potential shift circuit 117 shown in FIG. 3 is configured to include resistors R3 and R4. Potential transfer circuit 127 in FIG.
are P-channel MO8 type FET P ta , P
1o, P channel MOS type FETP9. Pl
The source of the voltage transfer circuit 7 is connected to the input line 13-24.24, and the gate and drain are connected to the sense amplifier input line 25.25. The potential shift circuit 137 in FIG. 5 is configured as a combination of the potential shift circuit 7 in FIG. 2 and the potential shift circuit 127 in FIG. 4. The potential shift circuit 117 shown in FIGS. 3 to 5 above,
127 and 137 function similarly to the potential shift circuit 7 of FIG.

〔Effect of the invention〕

According to the present invention, it is possible to move the human power potential to the sense amplifier to the high sensitivity region of the sense amplifier while maintaining the data of the memory cell appearing on the bit line at a high potential by the potential shift circuit. Read operations can be performed faster and more stably without increasing power consumption.

[Brief explanation of drawings]

Fig. 1 is an overall configuration diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of the details of the chain line portion, and Figs. 3 to 5 show different configuration examples of the potential transfer circuit. The circuit diagram shown in FIG. 6 is an overall configuration diagram of a conventional SRAM'. 1...Memory cell, 2,2...Bit line pair, 3...
・Word line, 6...Writing/reading circuit, 7...
Potential transfer circuit, 8... Sense amplifier, 14... Row decoder, 15... Address input circuit, 17... Column decoder, 117... Potential transfer circuit, 127... Potential transfer circuit, 137 ...Potential transfer circuit.

Claims (1)

[Claims] A plurality of static memory cells for data storage, a bit line for exchanging data with these memory cells, a sense amplifier for amplifying the data of the memory cell appearing on the bit line, and the bit line. a write/read circuit that writes and reads data to and from the memory cell via a line, a word line that selects the memory cell, a row decoder that selects the word line, and a column decoder that selects the bit line; A static random access memory comprising an address input circuit that provides an address signal to the row decoder and the column decoder, the static random access memory being connected between the bit line and the sense amplifier to input the potential of the data signal to the sense amplifier. A static random access memory characterized by having a potential shifting circuit that moves the potential to a high sensitivity area.