JPS63244396A - Word line driving circuit for dynamic ram - Google Patents

Word line driving circuit for dynamic ram

Info

Publication number
JPS63244396A
JPS63244396A JP62079120A JP7912087A JPS63244396A JP S63244396 A JPS63244396 A JP S63244396A JP 62079120 A JP62079120 A JP 62079120A JP 7912087 A JP7912087 A JP 7912087A JP S63244396 A JPS63244396 A JP S63244396A
Authority
JP
Japan
Prior art keywords
word line
boosting
transistor
level
line drive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62079120A
Other languages
Japanese (ja)
Inventor
Kazuyasu Fujishima
一康 藤島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62079120A priority Critical patent/JPS63244396A/en
Publication of JPS63244396A publication Critical patent/JPS63244396A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To eliminate a terminal in which a voltage is doubly boosted up to nearly twice as much as a supply voltage and to boost a word line to a level more than [supply voltage + threshold voltage of transistor (TR)] by providing in each word line a boosting capacity which is directly connected with the word line. CONSTITUTION:Each word line is provided with a word line boosting circuit 7 consisting of the boosting capacitor 8 which is directly connected with the word line WL, and the TR 9 which is connected with the boosting capacity 8 in serial through a terminal N3 and whose gate is connected to the word line WL and to which a boosting signal phiB is impressed on the drain. Thus, the high level of a word line driving signal is set to a supply voltage level, and the boosting level of the gate of a word line driving transistor 3 can be stopped at a level avoiding a duplex boosting.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、ワード線を電源電圧レベル以上に昇圧する
１トランジスタ型ダイナミックＲＡＭのワード線駆動回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a word line drive circuit for a one-transistor type dynamic RAM that boosts a word line to a power supply voltage level or higher.

［従来の技術］ 第３図は、従来の行デコーダおよびワード線駆動回路を
示す図である。[Prior Art] FIG. 3 is a diagram showing a conventional row decoder and word line drive circuit.

第３図において、１はＮＯＲ回路で構成されたデコーダ
回路で、″Ａ″′７ｉは入力アドレスがＡ、〜Ａｎまで
あった場合、Δ、またはτ５．Ａ２またはＴ２．・・・
、ＡｎまたはＱｎが入力されることを示している。In FIG. 3, 1 is a decoder circuit composed of a NOR circuit, and "A"'7i is Δ or τ5.7i when the input addresses are A to An. A2 or T2. ...
, An or Qn is input.

２はデコーダ出力端子Ｎ、とワード線駆動トランジスタ
３のゲート端子Ｎ２との間に挿入されたデカップルトラ
ンジスタ、３はドレインがワード線駆動信号φＸに、ゲ
ートがデカップルトランジスタ２に、ソースがワード線
ＷＬに接続されたワード線駆動トランジスタ、４はゲー
トにワード線信号が印加されるアクセストランジスタ５
とメモリ容量６とで構成された１トランジスタ型メモリ
セルである。2 is a decoupled transistor inserted between the decoder output terminal N and the gate terminal N2 of the word line drive transistor 3; 3 has its drain connected to the word line drive signal φX; its gate connected to the decoupled transistor 2; and its source connected to the word line WL A word line drive transistor 4 is connected to an access transistor 5 to which a word line signal is applied to the gate.
This is a one-transistor type memory cell composed of a memory capacitor 6 and a memory capacitor 6.

次に、第４図の波形図をもとに、第３図に示す回路の動
作について説明をする。なお、説明を簡単にするために
、ここでは電源電圧ＶＣＣを５Ｖ１トランジスタのしき
い値電圧ＶＴを１■とする。Next, the operation of the circuit shown in FIG. 3 will be explained based on the waveform diagram of FIG. 4. In order to simplify the explanation, it is assumed here that the power supply voltage VCC is 5V1 and the threshold voltage VT of the transistor is 1.

行アドレスＡｎが入力されると°、すべてのアドレス入
力の組合わせがすべて低レベル（ＯＶ）である選択デコ
ーダを除いて、他のすべての非選択デコーダの出力端子
Ｎ、が低レベル（Ｏｖ）に遷移し、それを受けて端子Ｎ
２も低レベル（ＯＶ）に遷移するので、非選択ワード線
にかかわるワード線駆動トランジスタ３は非導通状態と
なる。When a row address An is input, the output terminals N, of all other non-selected decoders, except for the selected decoder whose combination of all address inputs are all low level (OV), are low level (Ov). In response to this, the terminal N
2 also transitions to a low level (OV), so the word line drive transistor 3 associated with the unselected word line becomes non-conductive.

一方、選択されたデコーダではすべてのアドレス入力が
低レベル（ＯＶ）であり、デコーダ出力端子Ｎ４．は高
レベル〈ここではＶＣＣ−Ｖ、ｒとして４ｖとする）を
保ち、それを受けて端子Ｎ２も４Ｖを保つので、選択ワ
ード線にかかわるワード線駆動トランジスタ３は導通状
態となる。On the other hand, all address inputs of the selected decoder are at low level (OV), and decoder output terminals N4. maintains a high level (here VCC-V, r is assumed to be 4V), and in response, the terminal N2 also maintains 4V, so the word line drive transistor 3 associated with the selected word line becomes conductive.

ワード線駆動信号φ×がＯＶから５■に立ち上がると、
導通しているワード線駆動トランジスタ３において、ゲ
ート端子Ｎ２とソース、ドレイン間の容量の容量結合で
、端子Ｎ２は４Ｖからほぼ８Ｖ　（４Ｖ＋５ＶＸ０．８
　：Ｑ、８はワード線駆動トランジスタ３のゲート置型
と端子Ｎ２の浮遊客層との比）まで昇圧され、ワード線
に５■が伝達される。When the word line drive signal φ× rises from OV to 5■,
In the word line drive transistor 3 which is conducting, the voltage at the terminal N2 changes from 4V to approximately 8V (4V+5VX0.8
:Q, 8 is boosted to the ratio of the gate type of the word line driving transistor 3 to the floating customer level of the terminal N2), and 5■ is transmitted to the word line.

トランジスタのしきい値によるロスをなくして、メモリ
容量に電源電圧の５■を−込むために、ワード線駆動信
号φＸ　ヲＶＣＣ＋Ｖｒ　　（５Ｖ＋　Ｉ　Ｖ）以上の
電圧、たとえば７ｖに昇圧すると、既に昇圧されていた
端子Ｎ２の電位は二重に昇圧され、はＧｆ９．６Ｖ　（
８Ｖ＋２ＶｘＯ，８）、！：、はぼ電ａ２１圧の２倍の
レベルにまで達し、その結果、ワード線ＷＬに７ｖが伝
達されることになる。In order to eliminate the loss due to the threshold voltage of the transistor and input 5cm of the power supply voltage into the memory capacity, when the word line drive signal φX is boosted to a voltage higher than VCC+Vr (5V+IV), for example 7V, the voltage has already been boosted. The potential of terminal N2, which had been in
8V+2VxO, 8),! :, the voltage reaches twice the level of the voltage a21, and as a result, 7V is transmitted to the word line WL.

［発明が解決しようとする問題点］ 従来のワード線駆動回路は、以上のよ・うに構成されて
いるので、ワード線をｖＣｃ＋Ｖｒ以上のレベルに昇圧
しようとした場合、ワード線駆動１−ランジスタのゲー
ト電圧が二重に昇圧され、はぼ電源電圧Ｖｃｃの２倍の
レベルにまで達し、信頼性を低下させるという問題点が
あった。[Problems to be Solved by the Invention] Since the conventional word line drive circuit is configured as described above, when an attempt is made to boost the word line to a level higher than vCc+Vr, the voltage of the word line drive 1-transistor is increased. There is a problem in that the gate voltage is doubled and reaches a level twice the power supply voltage Vcc, which reduces reliability.

この発明は、上記のような問題点を解消するためになさ
れたもので、ワード線駆動用トランジスタのゲート端子
Ｎ２のごとく二重に昇圧される端子をなくしながら、ワ
ード線をｖＣＣ＋ＶＴ　（電源電圧＋トランジスタのし
きい値電圧）以上のレベルに昇圧することのできるワー
ド線駆動回路を得ることを目的とする。This invention was made to solve the above-mentioned problems, and eliminates a terminal that is doubly boosted, such as the gate terminal N2 of the word line driving transistor, and increases the word line voltage to vCC+VT (power supply voltage + An object of the present invention is to obtain a word line drive circuit capable of boosting the voltage to a level higher than (the threshold voltage of a transistor).

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るワード線駆動回路は、ワード線１本ごと
に昇圧用容量を設けたものである。The word line drive circuit according to the present invention is provided with a boosting capacitor for each word line.

［作用］ ワード線駆動信号φＸの高レベルを電源電圧ＶＣＣレベ
ルにし、ワード線駆動トランジスタのゲートの昇圧レベ
ルを、二重昇圧を避けたレベルに留める。[Operation] The high level of the word line drive signal φX is set to the power supply voltage VCC level, and the boost level of the gate of the word line drive transistor is kept at a level that avoids double boost.

［発明の実施例コ 以下、この発明の一実価例を図について説明をする。[Embodiments of the invention] Hereinafter, one practical example of this invention will be explained with reference to the drawings.

第１図は、この発明の一実施例に係る行デコーダおよび
ワード線駆動回路を示す図である。FIG. 1 is a diagram showing a row decoder and word line drive circuit according to an embodiment of the present invention.

第１図において、１はＮＯＲ回路で構成されたデコーダ
回路、２はデコーダ出力端子Ｎ、とワード線駆動トラン
ジスタ３のゲート端子Ｎ２との間に挿入され、ゲートに
信号φ丁が印加されるデカップルトランジスタ、３はド
レインがワード線駆動信号φＸに、ゲートがデカップル
トランジスタ２に、ソースがワード線に接続されたワー
ド線駆動トランジスタ、４はゲートにワード線信号が印
加されるアクセストランジスタ５とメモリ容量６とで構
成された１トランジスタ型メモリセルである。In FIG. 1, 1 is a decoder circuit composed of a NOR circuit, 2 is a decoupler inserted between the decoder output terminal N and the gate terminal N2 of the word line driving transistor 3, and a signal φd is applied to the gate. Transistor 3 is a word line drive transistor whose drain is connected to the word line drive signal φX, whose gate is connected to the decoupled transistor 2, and whose source is connected to the word line; 4 is an access transistor 5 whose gate is applied with the word line signal, and a memory capacitor. This is a one-transistor type memory cell composed of 6 and 6.

７は、この実施例の特徴である、ワード線１本ごとに設
けられた、ワード線ＷＬと直接結合する昇圧容量８と、
該昇圧容量８に端子Ｎ、を介して直列に接続され、その
ゲートがワード線につながり、そのドレインに昇圧信号
φＢが印加されるトランジスタ９とで構成されたワード
線昇圧回路である。7 is a boosting capacitor 8 provided for each word line and directly coupled to the word line WL, which is a feature of this embodiment;
This is a word line boosting circuit composed of a transistor 9 which is connected in series to the boosting capacitor 8 via a terminal N, whose gate is connected to the word line, and whose drain is applied with a boost signal φB.

以下、第２図の波形図をもとに、第１図に示すこの発明
の一実施例のワード線駆動回路の動作を説明する。なお
、ここで−シ、１シ明を簡単にするために、電源電圧＼
Ｌ／　ｃｃ＝　５　Ｖ、トランジスタのしきい値ｖＴを
１Ｖとｐる。The operation of the word line drive circuit according to the embodiment of the present invention shown in FIG. 1 will be explained below based on the waveform diagram shown in FIG. In addition, here, in order to simplify the explanation, the power supply voltage ＼
L/cc=5 V, and the threshold voltage vT of the transistor is set to 1 V.

行アドレスが入力された後、ワード線駆動信号φＸがＯ
ｖから５Ｖに立ち上がるまでの動作は、従来の回路で説
明したものと同じである。この時点で、端子Ｎ、は４Ｖ
、端子Ｎ２は８Ｖ、ワード線ＷＬは５Ｖに達している。After the row address is input, the word line drive signal φX goes to O.
The operation from V to 5V is the same as that described for the conventional circuit. At this point, terminal N is 4V
, terminal N2 has reached 8V, and word line WL has reached 5V.

続いて、信号φ丁を７Ｖ１．：昇圧すると、非導通であ
ったデカップルトランジスタ２が導通し、端子Ｎ、とＮ
２ｐレベルはほぼ５Ｖに等化する。この値は、端子Ｎ、
とＮ２との浮遊容量の比によって変わるが、通常、デコ
ーダ出力端子Ｎ、の容量はトランジスタのゲート端子Ｎ
２に比べて１０倍以上はあり、等化機の電圧は５Ｖ以下
となる。この時点で、それまで導通していたワード線駆
動トランジスタ３は非導通となる。Next, the signal φd is set to 7V1. : When the voltage is boosted, decoupled transistor 2, which was non-conductive, becomes conductive, and terminals N and N
The 2p level equals approximately 5V. This value is the terminal N,
Normally, the capacitance of the decoder output terminal N is the same as the transistor gate terminal N
2, and the voltage of the equalizer is 5V or less. At this point, the word line drive transistor 3, which had been conductive until then, becomes non-conductive.

ワード線昇圧回路７においては、選択されたワード線に
かかるものだけが、昇圧容量８に５Ｖが充電され、スイ
ッチトランジスタ９が導通している。In the word line booster circuit 7, the booster capacitor 8 is charged with 5V and the switch transistor 9 is conductive only for the selected word line.

続いて、昇圧信号φａがＯｖから５ｖに遷移すると、端
子Ｎ、が高レベルになり、昇圧容Ｉ８の容量結合でワー
ド線ＷＬレベルが５Ｖから５Ｖ以上に昇圧される。Subsequently, when the boost signal φa transitions from Ov to 5V, the terminal N becomes high level, and the word line WL level is boosted from 5V to 5V or more due to the capacitive coupling of the boost capacitor I8.

昇圧容１８の大きさをワード線ＷＬの容量に対して、た
とえば、４０％程度に選ぶことで、ワード線昇圧Ｌ／べ
／Ｌ、、！：ＬＴ７Ｖ　（５Ｖ＋５ＶＸ０．４）が得ら
れ、端子Ｎ、は５Ｖに達する。By selecting the size of the boost capacitor 18 to be, for example, about 40% of the capacitance of the word line WL, the word line boost L/B/L,...! :LT7V (5V+5VX0.4) is obtained, and terminal N reaches 5V.

なお、昇圧容量８の大きさを、ワード線ＷＬの容量に対
して１０％〜６０％の範囲内で任意の大きさに選べば、
この発明の一実施例は好ましい動作を行ない得る。Note that if the size of the boost capacitor 8 is selected to be any size within the range of 10% to 60% of the capacitance of the word line WL,
One embodiment of the invention may perform the preferred operation.

なお、上記実施例では、デコーダにＮＯＲ回路を用いた
が、これに限らず、たとえば、ＮＡＮＤ回路とインバー
タ回路とで構成してもよく、デコーダの構成が、上記の
ものに限定されるわけではない。In addition, in the above embodiment, a NOR circuit is used as a decoder, but the decoder is not limited to this, and may be configured with, for example, a NAND circuit and an inverter circuit, and the configuration of the decoder is not limited to the above. do not have.

［発明の効果］ 以上のように、この発明によれば、ワード線１本ごとに
、ワード線に直接結合した昇圧容量を設置ノだので、電
源電圧の２倍近くまで二重に昇圧される端子をなくしな
がら、ワード線をｖＣＣ＋　Ｖ　Ｔ（電源電圧士トラン
ジスタのしきい値電圧）以上のレベルに昇圧することが
川面となり、信頼性の高いタイナミックＲＡＭが得られ
る効果がある。[Effects of the Invention] As described above, according to the present invention, since a boosting capacitor directly coupled to each word line is installed for each word line, the voltage is doubled to nearly twice the power supply voltage. The key is to boost the voltage of the word line to a level equal to or higher than vCC+VT (the threshold voltage of the power supply voltage transistor) while eliminating the terminal, and it is effective to obtain a highly reliable dynamic RAM.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、この発明の一実施例に係る行デコーダａ３よ
びワード線駆動回路を示す図である。第２図は、第１図
に示Ｊ゛ワード線駆動回路の動作を説明するための波形
図である。第３図は、従来の行デコーダおよびワード線
駆動回路を示す図である。 第４図は、第３図に示す従来のワード線駆動回路の動作
を説明するための波形図である。 図において、１はデコーダ、２はデカップルトランジス
タ、３はワード線駆動トランジスタ、４はメモリセル、
７はワード線昇圧回路、８は昇圧容量、９はトランジス
タを示す。FIG. 1 is a diagram showing a row decoder a3 and a word line drive circuit according to an embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation of the J word line drive circuit shown in FIG. 1. FIG. 3 is a diagram showing a conventional row decoder and word line drive circuit. FIG. 4 is a waveform diagram for explaining the operation of the conventional word line drive circuit shown in FIG. 3. In the figure, 1 is a decoder, 2 is a decoupled transistor, 3 is a word line drive transistor, 4 is a memory cell,
7 is a word line booster circuit, 8 is a booster capacitor, and 9 is a transistor.

Claims (4)

【特許請求の範囲】[Claims] （１）ワード線を電源電圧レベル以上に昇圧する１トラ
ンジスタ型ダイナミックＲＡＭにおいて、 前記ワード線１本ごとに、昇圧用容量を直接結合したこ
とを特徴とする、ダイナミックＲＡＭのワード線駆動回
路。(1) A word line drive circuit for a dynamic RAM, characterized in that in a one-transistor type dynamic RAM that boosts a word line to a power supply voltage level or higher, a boosting capacitor is directly coupled to each word line. （２）前記ワード線に直接結合した昇圧用容量が、前記
ワード線容量の１０％〜６０％の大きさであることを特
徴とする、特許請求の範囲第１項記載のダイナミックＲ
ＡＭのワード線駆動回路。(2) The dynamic R according to claim 1, wherein the boosting capacitance directly coupled to the word line has a size of 10% to 60% of the word line capacitance.
AM word line drive circuit. （３）ワード線を電源電圧レベル以上に昇圧する１トラ
ンジスタ型ダイナミックＲＡＭにおいて、 前記ワード線１本ごとに、前記ワード線と直接結合した
昇圧用容量と、ソースが前記昇圧用容量に直列接続され
、ゲートがワード線信号に接続され、ドレインが昇圧信
号に接続されたワード線昇圧トランジスタとを含む昇圧
回路を設けたことを特徴とする、ダイナミックＲＡＭの
ワード線駆動回路。(3) In a one-transistor dynamic RAM that boosts a word line to a power supply voltage level or higher, each word line has a boosting capacitor directly coupled to the word line, and a source connected in series with the boosting capacitor. A word line drive circuit for a dynamic RAM, comprising: a boost circuit including a word line boost transistor whose gate is connected to a word line signal and whose drain is connected to a boost signal. （４）前記昇圧用容量が、前記ワード線容量の１０％〜
６０％の大きさであることを特徴とする、特許請求の範
囲第３項記載のワード線駆動回路。(4) The boosting capacitance is 10% or more of the word line capacitance.
4. The word line drive circuit according to claim 3, wherein the word line drive circuit has a size of 60%.
JP62079120A 1987-03-30 1987-03-30 Word line driving circuit for dynamic ram Pending JPS63244396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62079120A JPS63244396A (en) 1987-03-30 1987-03-30 Word line driving circuit for dynamic ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62079120A JPS63244396A (en) 1987-03-30 1987-03-30 Word line driving circuit for dynamic ram

Publications (1)

Publication Number Publication Date
JPS63244396A true JPS63244396A (en) 1988-10-11

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ID=13681064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62079120A Pending JPS63244396A (en) 1987-03-30 1987-03-30 Word line driving circuit for dynamic ram

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0389202A2 (en) * 1989-03-20 1990-09-26 Fujitsu Limited Dynamic random access memory having improved word line control
EP0798736A2 (en) * 1996-03-28 1997-10-01 Ramtron International Corporation Bootstrapping circuit utilizing a ferroelectric capacitor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0389202A2 (en) * 1989-03-20 1990-09-26 Fujitsu Limited Dynamic random access memory having improved word line control
EP0798736A2 (en) * 1996-03-28 1997-10-01 Ramtron International Corporation Bootstrapping circuit utilizing a ferroelectric capacitor
EP0798736A3 (en) * 1996-03-28 1999-06-09 Ramtron International Corporation Bootstrapping circuit utilizing a ferroelectric capacitor

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