JPS63241787A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain high density, by constituting a memory cell of the one having selective transistors of a P-channel and an N-channel, and operating each memory cell is a prescribed reange of voltage. CONSTITUTION:Each memory cell is constituted by arranging the selective transistor (Tr) of the P-channel and the one of N-channel alternately in a direction of word line. When the readout of a P-type memory cell AP1 is performed, only the word line WL1 is dropped from a Vcc/2 to a low voltage side. Then, only the selective Rrs of the memory cell AP1 and A CP1 are turned ON. At this time, an adjacent N-type memory cell BN1 and the selective Tr remain at OFF state. The information in the AP1 appears on a bit line BL1, and BL2 to a sense amplifier, the information in the AP1 appears on the BL1, then, a small potential difference is generated, and the BL2 remains at original potential. This is used for the reference of the sense amplifer. Following that, the latch operation of the sense amplifier is performed, then, a prescribed readout operation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Field of Application The present invention is applicable to, for example, a DRAM (Dyna
+lic Randos Access Memory
) and other semiconductor memory devices.

B0 Summary of the Invention The present invention provides a semiconductor memory device in which a plurality of memory cells each consisting of a selection transistor and a capacitor are arranged.
By configuring the memory cell using a memory cell having a P-channel selection transistor and a memory cell having an N-channel selection transistor, the density of the semiconductor memory device can be increased.

C9 Conventional Technology Selection As an example of a semiconductor memory device in which a plurality of memory cells each consisting of a transistor and a capacitor are arranged, a semiconductor memory device as shown schematically in FIG. 2 is known.

This figure 2 shows a hold bit line type DRA.
An example of M is an area A1 indicated by diagonal lines in FIG.
+ A2 + As, B 1. B2.

B3. C1, C2, C3, Di, D! , Ds, etc. are regions in which capacitors for accumulating charges exist, and although not shown in the drawings, an element bone W1 head region is formed in each of these regions A1, etc. When a field oxide film is formed by selective oxidation, for example, the element isolation wI3ti occupies approximately 50% of the area. The regions A1, etc. in which these capacitors exist are formed by forming two regions, respectively, and are connected to each bit line BLI, BL2 . BL3. In FIG. 2, a region connected to BL4 and in which a contact hole is formed is shown as a region CH with a cross line.

For such a memory array, each word line WLI, WL2°WL3 . WL4
．． WL5. WL6. WL7 is arranged so as to be orthogonal to the bit line BLI, etc., and each of these word lines WL
I, etc. function as the gate electrodes of the selection transistors arranged at positions between the above-mentioned areas C)I and areas A1, etc.

Here, to briefly explain the operation of a conventional semiconductor memory device having such a structure, the area A is
When reading 1 information, first, word line WLI is selected by a signal from the row decoder, and the potential of this word line WLI rises. Then, the area A1 . Each selection transistor in the tJ region C1 is turned on. On the other hand, on the column decoder side, based on the address signal, bit line BLI and bit line BL2 are selected because the hold bit line system is used. With this selection, the bit line BLI and bit line B
L2 is connected to the sense amplifier, and predetermined information is read from the capacitor in the area A1 to the sense amplifier via the bit line BLI while the bit line BL2 is used as a dummy.

D1 Problems to be Solved by the Invention However, in the conventional semiconductor memory device as described above, since the area occupied by the element bone Mfil region in the memory cell is large, it is difficult to obtain sufficient capacity when the element density is increased. Therefore, it becomes difficult to securely retain information, and the load on the sense amplifier increases.

In addition, the semiconductor memory device using the held bit line method described above has the advantage of being able to balance out noise, etc. compared to the open bit line method, but it also has the advantage of being able to balance out noise, etc. compared to the open bit line method. Because of this, the number of word lines is twice that of the oven bit line method, which is disadvantageous for increasing the density of memory devices.

Furthermore, charging and discharging power associated with read operations and the like is also required to perform the above-mentioned operations, and it is desired to reduce the power consumption.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention aims to provide a memory device that effectively achieves higher density.

Means for Solving the Problem The present invention provides a semiconductor memory device in which a plurality of memory cells each consisting of a selection transistor and a capacitor are arranged.
The memory cell includes a memory cell having a P-channel selection transistor and a memory cell having an N-channel selection transistor, and the memory cell having the P-channel selection transistor is operated in a voltage range lower than an intermediate potential. The above problem is solved by a semiconductor memory device characterized in that a memory cell having the N-channel selection transistor is operated in a voltage range higher than an intermediate potential.

For example, by forming the selection transistor of the F0 effect memory cell not only with an N-channel transistor but with both a P-channel transistor and an N-channel transistor, the threshold voltage vth of the selection transistor can be made different from that of a P-channel transistor and that of an N-channel transistor. Two types of things will be formed.

For example, when a word line potential is operated in three levels, a memory cell having a P-channel selection transistor is selected in a voltage range from a certain intermediate potential to a low level; A memory cell having an N-channel selection transistor is selected in a high level voltage range. This means that
If we consider memory arrays using the hold bit line method, we can see that different word lines are used as references during sensing operations and are used to deselect adjacent memory cells. Due to the difference in threshold voltage vth, it is possible to integrate them into one word line. Therefore, even when attempting to increase the density of the semiconductor memory device, the pitch of the formed word lines can be increased, resulting in a structure particularly advantageous for increasing the density.

Further, in the semiconductor memory device of the present invention, the memory cell is P
Memory cell with channel selection transistor and N
The memory cell having the P-channel selection transistor is operated in a voltage range lower than an intermediate potential, and the memory cell having the N-channel selection transistor is arranged in combination with a memory cell having a channel selection transistor. When the memory cells are operated in a voltage range higher than the intermediate potential, the memory cells are reverse biased.

Then, the depletion layer expands in the PN junction, and elements can be isolated without forming an element isolation region. Therefore, it becomes possible to reduce the area of the region where the element isolation region is formed, and it becomes possible to realize higher density of the semiconductor memory device.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing an example of the layout of a part of the memory array of the semiconductor memory device of this embodiment. First, the structure will be explained with reference to FIG.

In the semiconductor memory device of this embodiment, the memory array is P
P consisting of channel selection transistor and capacitor
The memory cell is composed of a P-type memory cell and a P-type memory cell consisting of an N-channel selection transistor and a capacitor. As shown in FIG. 1, pairs of memory cells having selection transistors of the same conductivity type (with common bit line contacts) are arranged alternately, and further in the bit line direction. In the X direction in the figure and in the Y direction in the figure, which is the word line direction, a pair of memory cells each having a selection transistor of an opposite conductivity type is arranged.

That is, the arrangement of the memory cells will be explained as follows: P-type memory cells AP1. Adjacent to the group AP2 in the word line direction is an N-type memory cell BNI.

A set of BN2 is arranged. A pair of P-type memory cells CPI and CP2 is arranged adjacent to the pair of N-type memory cells BNI and BN2 in the word line direction. This pair of P-type memory cells CPI and CP2
A pair of N-type memory cells D are adjacent to each other in the word line direction.
NI and DN2 sisters are assigned. Although not shown, such memory cells of different conductivity types are alternately arranged in the word line direction.

Furthermore, the pair of P-type memory cells APL.

Adjacent to AP2 in the bit line direction, a pair of N-type memory cells AN3. A group of AN4 is provided.

Further, a pair of P-type memory cells BP3 is adjacent to the pair of N-type memory cells BNI and BN2 in the bit line direction.
．． A set of BP4 is arranged. Further, adjacent to the pair of P-type memory cells CPI and CP2 in the bit line direction, a pair of N-type memory cells CN3. A set of CN4 is provided. and the pair of N-type memory cells DNI,
A pair of P-type memory cells DP3.DN2 are adjacent to each other in the bit line direction. A set of DP4 is provided. Although not disclosed, such memory cells of different conductivity types are also arranged alternately in the bit line direction.

Here, as described above, each memory cell is provided with a selection transistor of each conductivity type, and has a structure in which a capacitor for holding information in the form of charge is formed. Since each of these memory cells operates within a predetermined voltage range as will be described later, the PN junction is in a reverse bias state. Therefore, it is not necessary to provide an element isolation region, and it is possible to increase the density of elements. Note that memory cells of the same conductivity type are continuous in the diagonal direction,
An element isolation region may be provided only in that portion, and even in this case, the structure is advantageous for increasing the density of elements.

Next, in the semiconductor memory device of this embodiment in which a pair of P-type memory cells and a pair of N-type memory cells are arranged alternately, word lines WLI to WL4 are formed in the Y direction in the figure. , a bit line BLO-BL4 is formed in the X direction in the figure.

First, each word line WLI to WL4 functions as a gate electrode of a selection transistor in each memory cell. In particular, since the word lines WLI-WL4 of this embodiment perform a ternary operation as described later, even in the hold bit line method, adjacent memory cells can be used as non-selected, and the word line The number can be reduced to half compared to the conventional method. The word line WLI serves as the gate electrode of the selection transistor of the P-type memory cells API, CPI and the N-type memory cells BNI, DNI, and the word line 1llWL2 serves as the gate electrode of the selection transistor of the P-type memory cells API, CPI and the N-type memory cells BNI, DNI. CP2 and N-type memory cell BN2. DN2
This becomes the gate electrode of the selection transistor. Further, the word line WL3 is connected to the N-type memory cell AN3. CN3 and P
Memory cell BP3. The word line WL4 serves as the gate electrode of the selection transistor of DP3, and the word line WL4 serves as the gate electrode of the selection transistor of DP3. CN4 and P-type memory cell BP4゜DP4
This becomes the gate electrode of the selection transistor.

Note that these word lines are each connected to a row decoder or the like.

Next, the bit lines BLO to BL4 are used when reading and writing data, and in this embodiment, the focus lines BLI and BL2 form a pair, and the bit lines BL3 and BL4 form a pair for sensing. be exposed. Here, to explain the connection relationship of the bit lines, the bit line BLO is connected to the N type memory cell AN3. AN4
are connected to each NMO3) transistor through a contact hole C)I. Further, the bit line BLI is connected to the above P
PMOS transistors of type memory cells API, AP2 and P type memory cells BP3. It is connected to each PMO3 transistor of BP4 through each contact hole CH. Further, the bit line BL2 is connected to each NMO3) transistor of the N-type memory cell BN1°BN2 and the N-type memory cell CN3. It is connected to each NMOS transistor of CN4 through each contact hole CH. Further, the bit line BL3 is connected to the P-type memory cells C, P1 . Each PMOS transistor of CP2 and a P-type memory cell DP3. The bit line BL4 is connected to each PMO3) transistor of the N-type memory cells DNI and DN2 through a contact hole CH. Due to such a connection relationship and the operation described below, the semiconductor memory device of this embodiment can reduce the number of word lines to half even if the hold bit line method is adopted, and the number of word lines can be reduced to one half even if the semiconductor memory device employs the hold bit line method. Each word line can be arranged at intervals similar to the above.

Next, the operation of the semiconductor memory device of this embodiment will be explained.

The semiconductor memory device of this embodiment adopts the hold bit line method, and sensing is performed between adjacent cell columns, but as described above, each memory cell is aligned in the word line direction (Y direction in the figure). P-channel selection transistor and N
Since the channel selection transistors are arranged alternately, selection can be made according to the level by operating the word line in three values.

First, as an example of the operation of this embodiment, a case will be described in which, for example, information stored in a capacitor of a P-type memory cell API is read out.

Initially, each word line WLI-WL4 is all controlled to a voltage of Vcc/2, which is an intermediate potential. Here, Vcc is a power supply voltage, and the intermediate potential is not particularly limited to the voltage of Vcc/2, but can be set to other values in consideration of the dark value voltage vth of each transistor, etc.

Next, when reading from the P-type memory cell API, only the word line WLI is lowered from Vcc/2 to the low level side. Then, from the relationship of the threshold (l! voltage vth), only the selection transistors of the P-type memory cell API and the P-type memory cell CPI in the figure are turned on.At this time, the adjacent N-type memory cell The selection transistor of BNI remains in the off state.Then, information on the P-type memory cell API appears on the bit line BLI, and information on the N-type memory cell BNI appears on the bit line BL.
It does not appear in 2.

In this state, the bit line BLI and bit line BL2, which form a bit pair, are connected to the sense amplifier. At this time, bit line B
Information from the P-type memory cell API appears in LI, and a slight potential difference is generated.

At the same time, since information from the memory cell BNI that is unselected due to the dark value voltage vth does not appear on the bit line, the bit line BL2 remains at its original potential. This is used for reference of the sense amplifier.

Subsequently, a latch operation of the sense amplifier is performed, and predetermined reading is performed.

Next, as another example of the operation of this embodiment, a case will be described in which, for example, information stored in the capacitor of an N-type memory cell BNI is read out. 2, and word line WLI is now boosted from Vcc/2 to the higher level power supply voltage Vcc during the selection operation. Then, among the memory cells forming the bit pair, only the N type memory cell BNI is connected to the bit line BL2 due to the difference in the dark value voltage vth of the selection transistor, and the P type memory cell API is connected to the bit line %91BL1 and the non-bit line BL1. considered to be a connection. Then, sensing is performed by the sense amplifier in the same manner.

Note that the level of the word line at the time of selection can be lower than the ground voltage or higher than the power supply voltage Vcc, if necessary.

Next, the operation of the bit line will be explained. Since no element isolation region is formed in each memory cell as described above, each bit line is operated in a voltage range that does not forward bias the boundary of the memory cell.

In other words, the bit line BLI connected to the P-type memory cell
, BL3 is operated in a voltage range from OV to Vcc/2,
Bit lines BLO, BL2 . connected to N-type memory cells.
BL4 is operated in a voltage range from Vcc/2 to power supply voltage VCC. Then, a reverse bias state is created between the memory cells of opposite conductivity types arranged alternately, a depletion layer is formed, and elements are isolated. This eliminates the need for elemental jil regions such as field oxide films, and increases the area occupied by capacitors and the like. In other words, it is possible to realize higher density of elements.

Regarding the operation of the bit line, during a sense operation, when there is data on the high level side for a P-type memory cell, and when there is data on the low level side for an N-type memory cell, the bit line goes to an intermediate potential. A latch may be used to secure it. Also, when there is data on the low level side for a P type memory cell, and when there is data on the high level side for an N type memory cell, the O
It is also possible to latch to V or the power supply voltage Vcc side.

As described above, the semiconductor memory device of this embodiment forms both a P-type memory cell and an N-type memory cell, and operates the word line in three values based on the difference in the dark value voltage vth. Accordingly, adjacent memory cells in the hold bit line type memory array can be deselected. Therefore, the number of bit lines is halved compared to the conventional one, and the word line pitch can be increased, resulting in a structure particularly advantageous for high density.

Further, in the semiconductor memory device of this embodiment, a P-type memory cell and an N-type memory cell are formed without providing an element isolation region, and the P-type memory cell is operated in a voltage range lower than an intermediate potential. The N-type memory cell is operated in a voltage range higher than the intermediate potential. For this reason, the PN junction between each memory cell is reverse biased, and the depletion layer thereof expands, making it possible to isolate the elements. Therefore, it becomes possible to reduce the area of the region where the element isolation region is formed, and it becomes possible to easily realize higher density of the semiconductor memory device.

Further, depending on the method of operation, the semiconductor memory device of this embodiment can reduce the charging/discharging current by about 50%, and can also reduce power consumption.

H6 Effects of the Invention The semiconductor memory device of the present invention can be used even in the hold bit line method by arranging memory cells having selection transistors of two conductivity types and operating the word line in a predetermined voltage range as described above. The number of word lines can be the same as in the open bit line method, which is advantageous for increasing the density of the semiconductor memory device. Further, due to the voltage range as described above between the memory cells, the PN junction is in a reverse bias state, so that the element jll wI region is unnecessary, and a high density arrangement of elements can be realized.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing the layout of an example of a semiconductor memory device of the present invention, and FIG. 2 is a schematic plan view showing the layout of an example of a conventional semiconductor memory device. API, AP2. BF2. BF2. CPI, CF2, D
P3. DP4...P-type memory cell AN3. AN4.
BNI, BN2. CN3. CN4, DNI, D
N2...N-type memory cells WLI to WL4...Word lines BLO to BL4...Bit line Patent Applicant: Sony Corporation Representative Patent Attorney Kobuwa Mikai Sakae Tamura

Claims (1)

[Scope of Claims] A semiconductor memory device comprising a plurality of memory cells each consisting of a selection transistor and a capacitor arranged, wherein the memory cells include a memory cell having a P-channel selection transistor and a memory cell having an N-channel selection transistor. and operating the memory cell having the P-channel selection transistor in a voltage range lower than an intermediate potential, and operating the memory cell having the N-channel selection transistor in a voltage range higher than the intermediate potential. A semiconductor memory device characterized by: