JPS63239964A - Heat conductive substrate - Google Patents
Heat conductive substrateInfo
- Publication number
- JPS63239964A JPS63239964A JP7168587A JP7168587A JPS63239964A JP S63239964 A JPS63239964 A JP S63239964A JP 7168587 A JP7168587 A JP 7168587A JP 7168587 A JP7168587 A JP 7168587A JP S63239964 A JPS63239964 A JP S63239964A
- Authority
- JP
- Japan
- Prior art keywords
- copper circuit
- holes
- plate
- conductive substrate
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052802 copper Inorganic materials 0.000 claims abstract description 42
- 239000010949 copper Substances 0.000 claims abstract description 42
- 239000000919 ceramic Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 230000008961 swelling Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000012805 post-processing Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000009760 electrical discharge machining Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052575 non-oxide ceramic Inorganic materials 0.000 description 1
- 239000011225 non-oxide ceramic Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は半導体装基板として有用な熱伝導性基板に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a thermally conductive substrate useful as a semiconductor packaging substrate.
（従来の技術）
最近、パワートランスモジュール用基板やスイッチング
電源モジュール用基板等の回路基板として、セラミック
ス基板上に銅板等の金属板を接合させたものがよく用い
られている。(Prior Art) Recently, as circuit boards such as power transformer module boards and switching power supply module boards, circuit boards in which a metal plate such as a copper plate is bonded to a ceramic board are often used.
従来から、このようなセラミックス回路基板を製造する
には、セラミックス基板の表面にモリブデンペースト等
を塗布、焼結することによりメタライズして、その上に
金属板をろう付けして接合することにより行われてきた
が、近年所定形状に打ち抜かれた銅回路板を、例えば酸
化アルミニウム焼結体や窒化アルミニウム焼結体からな
るセラミックス基板上に接触配置させて加熱し、直接セ
ラミックス基板と銅回路板を接合させる、いわゆるＤＢ
Ｃ法（ダイレクト・ボンディング・カッパー法）により
行われてきている。Traditionally, to manufacture such ceramic circuit boards, the surface of the ceramic substrate is coated with molybdenum paste, etc., metallized by sintering, and then a metal plate is bonded to the surface by brazing. However, in recent years, a copper circuit board punched into a predetermined shape is placed in contact with a ceramic substrate made of aluminum oxide sintered body or aluminum nitride sintered body and heated, and the ceramic substrate and copper circuit board are directly bonded. Joining, so-called DB
This has been carried out using the C method (direct bonding copper method).
このＤＢＣ法により形成されたセラミックス回路基板は
、セラミックス基板と銅回路板との接合強度が強く、単
純構造なので小型高実装化が可能であり、また作業工程
も短縮できる等の長所を有している。The ceramic circuit board formed by this DBC method has strong bonding strength between the ceramic board and the copper circuit board, has a simple structure, allows for small size and high packaging, and has the advantages of shortening the work process. There is.
（発明が解決しようとする問題点）
ところで、このような従来のＤＢＣ法においては、銅回
路板の接合面を平板状のままでセラミックス基板上に接
触配置させて加熱し接合すると、使用する銅回路板が特
に形状が複雑であったり、大きかったりするとその加工
工程中に歪みを受けているために加熱時に変形しやすく
、直接接合であるためその変形部に加熱炉中の雰囲気ガ
スを巻込みやすく、接合後の銅回路板に部分的な接合不
良、いわゆる「ふくれ」が生じやすくなる。これにより
半導体素子等の実装に際して、傾斜してマウントされた
りする等の実装不良を生じるという問題があった。また
、接合部に介在しているガスによって熱抵抗が大きくな
り、すなわち放熱性が低下するという問題もあった。(Problems to be Solved by the Invention) By the way, in such a conventional DBC method, when the bonding surface of a copper circuit board is placed in contact with a ceramic substrate as a flat plate and heated and bonded, the copper used is If the circuit board has a particularly complex shape or is large, it will be easily deformed during heating because it is distorted during the processing process, and since it is directly bonded, the deformed part will entrain the atmospheric gas in the heating furnace. This tends to cause local bonding failures, or so-called "blisters," on copper circuit boards after bonding. As a result, when mounting semiconductor elements, etc., there is a problem in that mounting defects such as mounting at an angle occur. Further, there was also a problem in that the gas present in the joint portion increased the thermal resistance, that is, the heat dissipation performance decreased.
このような問題に対して、従来、銅回路板の接合面に溝
を設けることによって、接合部のふくれを防止していた
。To solve this problem, conventionally, a groove is provided in the joint surface of the copper circuit board to prevent the joint from blistering.
しかしながらこのような対策は、ふくれに対しては効果
があっったものの、半導体素子等のマウント時や配線領
域の形成時等に使用する液状材料が溝内にしみ込み、後
処理に手間がかかったり、特性を劣化させる等の問題が
あった。However, although these measures were effective against blisters, the liquid material used when mounting semiconductor elements or forming wiring areas seeped into the grooves, making post-processing time-consuming. There were problems such as deterioration of characteristics and deterioration of characteristics.
本発明はこのような問題点を解消するためになされたも
ので、ＤＢＣ法の接合時に生じるふくれを熱抵抗に影響
をおよぼさないように最少限におさえ、かつ後工程にお
ける問題もなく、放熱性に優れた熱伝導性基板を提供す
ることを目的とする。The present invention was made to solve these problems, and it minimizes the blisters that occur during bonding using the DBC method so as not to affect the thermal resistance, and also eliminates problems in post-processing. The purpose is to provide a thermally conductive substrate with excellent heat dissipation.
［発明の構成コ
（問題点を解決するための手段）
本発明の熱伝導性基板は、セラミックス基板上に所定の
形状の銅回路板を接触配置し加熱接合させてなる熱伝導
性基板において、前記銅回路板に貫通孔を設けてなるこ
とを特徴としている。[Configuration of the Invention (Means for Solving Problems) The thermally conductive substrate of the present invention is a thermally conductive substrate formed by placing a copper circuit board of a predetermined shape in contact with a ceramic substrate and heat-bonding the substrate. The copper circuit board is characterized in that a through hole is provided in the copper circuit board.
本発明の銅回路板に設ける貫通孔としては、その径が１
０μｍ〜２１１の範囲が適しており、貫通孔間の最大間
隔は１０１ｎ以下が適していて、径を小さくするときは
最大間隔を狭く、径を大きくするときは最大間隔を広く
するように適宜選択することが好ましい６貫通孔の径が
１０μｍ未満であると本発明の効果が十分に得られず、
２ｎｎを超えると半導体素子等をマウントする際、ハン
ダ層内に巣が発生する恐れが高くなり、これにより熱抵
抗が大きくなる。また、この貫通孔間の最大間隔が生じ
る可能性のあるふくれの径の最大値となるなめ、最大間
隔が１０１１を超えると本発明の効果が十分に得られな
くなる。また、貫通孔の総開口面積が銅回路板の面積の
１０％以下の範囲であることが好ましい。The diameter of the through hole provided in the copper circuit board of the present invention is 1
A range of 0 μm to 211 is suitable, and a maximum spacing between through holes of 101 nm or less is suitable, and when decreasing the diameter, the maximum spacing is narrower, and when increasing the diameter, the maximum spacing is selected as appropriate. If the diameter of the through hole is preferably less than 10 μm, the effects of the present invention cannot be sufficiently obtained,
If it exceeds 2 nn, there is a high possibility that cavities will occur in the solder layer when mounting a semiconductor element, etc., and this will increase the thermal resistance. Furthermore, since the maximum distance between the through holes is the maximum value of the diameter of a bulge that may occur, if the maximum distance exceeds 1011, the effects of the present invention will not be sufficiently obtained. Further, it is preferable that the total opening area of the through holes is in a range of 10% or less of the area of the copper circuit board.
また、貫通孔の形成方法としては、銅回路板を所定形状
に加工する際に同時にプレス加工によって形成してもよ
いし、またエツチング加工、レーザ加工または放電加工
等によって形成してもよい。The through-holes may be formed by press working simultaneously when processing the copper circuit board into a predetermined shape, or may be formed by etching, laser processing, electrical discharge machining, or the like.
本発明に使用するセラミックス基板としては、アルミナ
、ベリリア等の酸化物系のセラミックス焼結体や窒化ア
ルミニウム、窒化ケイ素、窒化チタン、炭化ケイ素等の
非酸化物系のセラミックス焼結体等からなるセラミック
ス基板が挙げられる。Ceramic substrates used in the present invention include sintered ceramics of oxides such as alumina and beryllia, and sintered ceramics of non-oxides such as aluminum nitride, silicon nitride, titanium nitride, and silicon carbide. Examples include substrates.
なお、非酸化物系のセラミックス基板を使用する場合に
は、あらかじめ接合表面を酸化処理してから使用するこ
とが好ましい。Note that when using a non-oxide ceramic substrate, it is preferable to oxidize the bonding surface in advance before use.
本発明に使用する銅回路板を形成するための銅板として
は、タフピッチ電解銅のような酸素を１００〜３０００
ｐｐｎの割合で含有する銅を圧延してなるものが好まし
い、また銅回路板め厚さは、０．１５〜０．５閾の範囲
が好ましい。As a copper plate for forming a copper circuit board used in the present invention, an oxygen content of 100 to 3000, such as tough pitch electrolytic copper, is used.
It is preferable that the copper circuit board is formed by rolling copper containing a ppn ratio, and the thickness of the copper circuit board is preferably in the range of 0.15 to 0.5 threshold.
本発明の熱伝導性基板は、あらかじめ前述の範囲内で貫
通孔を形成した所定の形状の銅回路板をセラミックス基
板上に接触配置させ、加熱することにより得られる。こ
の加熱温度は、銅の融点＜ １０８３℃）以下で銅と酸
化銅の共晶温度（１０６５℃）以上である。また、酸素
を含有する銅板を使用する場合は、不活性ガス雰囲気中
で加熱を行うことが好ましく、酸素を含有しない銅板を
使用する場合は、８０〜３９００１Ｅ）ＩＩの雰囲気中
で加熱を行うことが好ましい。The thermally conductive substrate of the present invention is obtained by placing a copper circuit board of a predetermined shape in which through-holes are previously formed within the above-mentioned range in contact with a ceramic substrate and heating the board. This heating temperature is below the melting point of copper (<1083°C) and above the eutectic temperature of copper and copper oxide (1065°C). In addition, when using a copper plate containing oxygen, it is preferable to perform heating in an inert gas atmosphere, and when using a copper plate not containing oxygen, heating should be performed in an atmosphere of 80 to 39001E) II. is preferred.
（作 用）
本発明の熱伝導性基板において、貫通孔を形成した銅回
路板を使用してセラミックス基板と加熱接合しているの
で、加熱時に加熱炉内の雰囲気ガスを巻込んでも、この
貫通孔より排出されてふくれを生じる可能性が著しく減
少し、かりにふくれが生じても、貫通孔間の最大間隔が
ふくれの最大値となるため、実装時や熱抵抗に影響をお
よぼさない。また、貫通孔は半導体素子等の実装時のろ
う付けによりふさがれてしまうので、後工程において問
題を生じることもない。(Function) In the thermally conductive substrate of the present invention, since the copper circuit board in which through holes are formed is heat-bonded to the ceramic substrate, even if atmospheric gas in the heating furnace is involved during heating, the The possibility of blistering caused by discharge from the holes is significantly reduced, and even if blistering occurs, the maximum distance between through holes is the maximum value of the blistering, so it will not affect mounting or thermal resistance. Moreover, since the through-holes are closed by brazing during mounting of semiconductor elements, no problems occur in subsequent processes.
（実施例） 次に本発明の一実施例について説明する。(Example) Next, one embodiment of the present invention will be described.
実施例
まず、厚さ０．３ｎｎで酸素含有量が３００ｐｐｌの銅
板を使用して、所定の形状への打抜き加工時に同時に径
０．２ｕの貫通孔をピッチ２ｕ（最大間隔的２．６ｕ）
で全面に設けて（貫通孔の総開口面積比的０．３％）銅
回路板を形成した。Example First, using a copper plate with a thickness of 0.3 nn and an oxygen content of 300 ppl, through-holes with a diameter of 0.2 u were punched at a pitch of 2 u (maximum spacing of 2.6 u) at the same time when punching into a predetermined shape.
(0.3% relative to the total opening area of the through holes) to form a copper circuit board.
このように形成した銅回路板を５０ｎｎｘ ２５１１ｘ
Ｏ，６３５Ｉｎのアルミナを主成分（９６％、他に４％
の焼結助剤を含む）とするセラミックス基板の上に接触
配置し、窒素ガス雰囲気中で１０７０℃の温度で１０分
間加熱し接合させた。The copper circuit board formed in this way is 50nnx 2511x
Main component is O,635In alumina (96%, other 4%
(containing a sintering aid) was placed in contact with the ceramic substrate, and was bonded by heating at a temperature of 1070° C. for 10 minutes in a nitrogen gas atmosphere.
このようにして得た熱伝導性基板の外観を観察したとこ
ろ、接合時のふくれは認められなかった。When the appearance of the thermally conductive substrate thus obtained was observed, no blisters were observed during bonding.
また本発明との比較のために、銅回路板に貫通孔を形成
しない以外は実施例と同一条件で熱伝導性基板を形成し
た。この熱伝導性基板の外観を観察したところ径が４〜
８ｍｎ＋のふくれが数個点在していた。Further, for comparison with the present invention, a thermally conductive substrate was formed under the same conditions as in the example except that no through holes were formed in the copper circuit board. When we observed the appearance of this thermally conductive substrate, the diameter was 4 to 4.
Several 8mm+ blisters were scattered.
［発明の効果］
以上説明したように本発明の熱伝導性基板によれば、貫
通孔を形成した銅回路板を使用してセラミックス基板と
加熱接合しているので、接合時に生しるふくれの著しく
少ないものが得られ、またふくれが生じても半導体素子
等のマウントの際や熱抵抗に影響をおよぼさないもので
あり、かつ後工程における問題もなく、放熱性に優れた
ものとなる。[Effects of the Invention] As explained above, according to the thermally conductive substrate of the present invention, since the copper circuit board with through holes is used to heat-bond it to the ceramic substrate, the blistering that occurs during bonding can be avoided. Even if blistering occurs, it will not affect the mounting of semiconductor devices or thermal resistance, and there will be no problems in post-processing, resulting in excellent heat dissipation. .
Claims (4)
触配置し加熱接合させてなる熱伝導性基板において、前
記銅回路板に貫通孔を設けてなることを特徴とする熱伝
導性基板。(1) A thermally conductive substrate formed by placing a copper circuit board of a predetermined shape in contact with a ceramic substrate and heat-bonding the same, characterized in that the copper circuit board is provided with a through hole.
請求の範囲第１項記載の熱伝導性基板。(2) The thermally conductive substrate according to claim 1, wherein the diameter of the through hole is in the range of 10 μm to 2 mm.
求の範囲第１項または第２項記載の熱伝導性基板。(3) The thermally conductive substrate according to claim 1 or 2, wherein the maximum distance between through holes is 10 mm or less.
０％以下の範囲である特許請求の範囲第１項ないし第３
項のいずれか１項記載の熱伝導性基板。(4) The total opening area of the through holes is 1 to the area of the copper circuit board.
Claims 1 to 3 that are within the range of 0% or less
The thermally conductive substrate according to any one of Items 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7168587A JPH0787222B2 (en) | 1987-03-27 | 1987-03-27 | Thermal conductive substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7168587A JPH0787222B2 (en) | 1987-03-27 | 1987-03-27 | Thermal conductive substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63239964A true JPS63239964A (en) | 1988-10-05 |
| JPH0787222B2 JPH0787222B2 (en) | 1995-09-20 |
Family
ID=13467658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7168587A Expired - Lifetime JPH0787222B2 (en) | 1987-03-27 | 1987-03-27 | Thermal conductive substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787222B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6559533B1 (en) * | 1999-09-17 | 2003-05-06 | Kabushiki Kaisha Toshiba | High-frequency package and the method for manufacturing the same |
| JP2012001430A (en) * | 2010-06-14 | 2012-01-05 | Ixys Semiconductor Gmbh | Method for manufacturing double-sided metallized ceramic substrate |
-
1987
- 1987-03-27 JP JP7168587A patent/JPH0787222B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6559533B1 (en) * | 1999-09-17 | 2003-05-06 | Kabushiki Kaisha Toshiba | High-frequency package and the method for manufacturing the same |
| JP2012001430A (en) * | 2010-06-14 | 2012-01-05 | Ixys Semiconductor Gmbh | Method for manufacturing double-sided metallized ceramic substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0787222B2 (en) | 1995-09-20 |
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