JPS63239933A - Manufacture of semiconductor base material - Google Patents

Abstract

PURPOSE:To form many types of semiconductor elements on a single substrate at the same time, by growing a single crystal on a nucleus forming surface having a nucleus forming density in the next higher order, growing a single crystal, which is different from said single crystal, on the nucleus forming surface having a large nucleus forming density, forming the single crystal on the single crystal, which is formed at the preceding time. CONSTITUTION:A surface 5, wherein nucleuses are not formed and nucleus forming density is small, is provided. A plurality of nucleus forming surfaces 7-9 are formed. Each nucleus forming surface has a sufficiently small area for growing a crystal only from a single nucleus and has a nucleus forming density larger than that of the surface 5 wherein the nucleuses are not formed. The surfaces 7-9 have different nucleus forming densities. At the stage when the single crystals are grown with the single nucleuses grown on the nucleus forming surfaces as the cores, a single crystal 6 is grown on the nucleus forming surface 7 having the larger nucleus forming density. Thereafter, a single crystal 10, which is different from said single crystal 6, is grown on the nucleus forming surface 8 having the larger nucleus forming density in the next higher order under the conditions different from above described nucleus forming conditions. The single crystal 10 is grown on the single crystal 6, which is formed on the nucleus forming surface 7 having the larger nucleus forming density. Thus the desired continued semiconductor regions 6-11 are formed on the nucleus forming surfaces 7-9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor substrate. More specifically, it relates to a method for manufacturing a single crystal substrate created by utilizing the difference in nucleation density of deposited material depending on the type of deposition surface material, and in the manufacturing process of the present invention, Many types of semiconductor elements are formed at the same time. As for these semiconductor elements.

Examples include electronic devices such as semiconductor integrated circuits, optical integrated circuits, and magnetic circuits, optical devices, magnetic devices, piezoelectric devices, and surface acoustic devices.

(Prior Art and its Problems) Conventionally, single crystal thin films used for semiconductor electronic devices, optical devices, etc. have been formed by epitaxial growth on single crystal substrates. however.

In order to epitaxially grow a single crystal G film on a single crystal substrate, it is necessary to match the lattice constant and thermal expansion coefficient between the single crystal material of the substrate and the epitaxial growth layer.
In order to form a single-crystal layer capable of producing high-quality devices, there has been a problem in that the types of substrate materials are limited to an extremely narrow range.

On the other hand, in recent years there has been much research and development into three-dimensional integrated circuits, in which semiconductor elements are layered in the normal direction of a substrate to achieve higher integration and multi-functionality. Research and development of large-area semiconductor devices such as solar cells arranged in arrays and switching transistors for liquid crystal pixels is becoming more popular year by year.

What these two methods have in common is that they require a technique for forming a semiconductor thin film on an amorphous insulator and forming electronic elements such as transistors thereon. Among these, a technique for forming a high quality single crystal semiconductor on an amorphous insulator is particularly desired.

However, in general, when a thin film is deposited on an amorphous insulator substrate such as Si02, the crystal structure of the salt 81 film becomes amorphous or polycrystalline due to the lack of long-range order in the substrate material, resulting in high It has been extremely difficult to form high quality single crystal semiconductors. Here, an amorphous film is one in which short-range order at the level of the nearest neighbor atoms is preserved, but no longer-range order, and a polycrystalline film is one that has a specific crystal orientation. It is a collection of single crystal grains separated by grain boundaries.

As mentioned above, in order to solve the conventional problems, Japanese Patent Application No. 153273/1983 proposes that the nucleation density be sufficiently higher than that of the material on the composting surface, and only a single nucleus can be formed on the composting surface. A dissimilar material is provided that is fine enough to grow.
A formation method has been proposed in which a crystal is formed by growing a crystal around a single nucleus grown on the dissimilar material, and by using this method, a single crystal can be formed even on an insulating amorphous substrate. It has been shown that disease formation is possible.

FIGS. 3(A) and 3(B) are schematic partial cross-sectional views showing an example of the structure of a single crystal formed by the above-described single crystal forming method.

In FIG. 3(A), a fine foreign material 2 is formed on an insulating substrate 1, and a single crystal is grown around a single nucleus grown on this foreign material 2 to form an island-shaped single crystal 3. It is something to do.

FIG. 3(B) shows that a recess is formed in an insulating substrate 1, a fine foreign material 2 is formed on the bottom of the recess, and a single crystal is grown around a single nucleus grown in this foreign material 2. There is also a method in which an island-shaped single crystal 3 is formed, and a single crystal region is formed in a part of the insulating substrate 1.

The method for forming this single crystal will be explained in more detail in the description of the embodiments of the present invention.

(Object of the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can simultaneously form multiple types of semiconductor elements on a single substrate by using the above-mentioned single crystal formation method. do.

(Means for Solving the Problems) The above-mentioned object of the present invention is to have a non-nucleation surface (SNDS) with a low nucleation density and an area sufficiently small for one crystal to grow from only a single nucleus. The nucleation density (N
Dc) and a plurality of nucleation surfaces (SNDL) with different nucleation densities (HD+, ) are provided, and a single crystal is grown around a single nucleus grown on these nucleation surfaces (SNDL). In the step of growing a single crystal on a nucleation surface (SNDL) with a large nucleation density (NDt) among the plurality of nucleation surfaces (SNDL) under predetermined nucleation conditions,
Next is the nucleation surface (SND) with a large nucleation density (NDc).
L) is grown a single crystal different from the single crystal under conditions different from the nucleation conditions, and this single crystal is nucleated with a nucleation density (NDL) larger than the nucleation plane (SNOL). A method for manufacturing a semiconductor substrate, characterized by forming a desired continuous semiconductor region continuous to each of the nucleation planes (!JNDL) by forming it on a single crystal formed on a plane (Ss o t ). This is achieved by

(Function) In the method for manufacturing a semiconductor substrate of the present invention described above, the non-nucleation surface (SNDS) has a non-nucleation surface (SNDS) with a low nucleation density and an area that is sufficiently small for crystal growth from only a single nucleus. By growing crystals under predetermined nucleation conditions on a substrate provided with a nucleation surface (SNOL) having a nucleation density (NDL) larger than the nucleation density (NDS) of the A single crystal can be grown only on this nucleation surface (SsoL) centered on a single nucleus grown on the nucleation surface (SNDL) with a large shaped r&density (NDL). In this case, the nucleation density (NIIs
) No crystals grow on the small nucleation surface (SNDS).

In the present invention, a plurality of nucleation surfaces (SNDL) that enable such crystal growth are provided, and each nucleation density (NDL) is different from each other. Therefore, by specifying the nucleation conditions, it is possible to initially grow a single crystal only on the nucleation plane (SNDL) with the largest nucleation density (MDL).

Next, by setting nucleation conditions different from the nucleation conditions described above, it is possible to form a single crystal different from the single crystal on the nucleation surface (SNDL), which is the next highest nucleation density (NDL). At the same time, the nucleation surface (S) with the largest nucleation density (MOL) of this single crystal
It can be formed on a single crystal formed in NDL). Hereinafter, by controlling the nucleation conditions, each nucleation surface (SNDL) is sequentially changed from a nucleation surface (SNDL) with a large nucleation density (NDc) to a nucleation surface (SNDL) with a small nucleation density (NDc).
), and at the same time grow this single crystal around each of the nucleation planes (Sho
t) can be formed on the top layer single crystal. In this way, desired continuous semiconductor regions can be formed on each of the plurality of nucleation planes (SMOL), and can be used as a base material for forming various electronic devices.

(Example) In order to explain the present invention in detail, Japanese Patent Application No. 61-153
The crystal growth method shown in No. 273 will be explained.

This crystal growth method is based on a selective deposition method that selectively forms a deposited film on a deposition surface. This is a method of selectively forming a thin film on a substrate by utilizing differences between materials in factors that influence nucleation during the thin film formation process.

FIGS. 4(A) and 4(B) are explanatory diagrams of the selective deposition method.

First, as shown in the figure, a thin film 2 made of a material having the above-mentioned factors different from that of the substrate 1 is formed on a substrate 1 at a desired portion.

If a thin film made of a suitable material is deposited under suitable deposition conditions, a phenomenon can be produced in which the thin film 3 grows only on the thin layer 2 and does not grow on the substrate 1. By utilizing this phenomenon, the thin film 3 formed in a self-aligned manner can be grown, and the conventional phosphorography process using a resist can be omitted.

Materials that can be deposited by such a selective formation method include, for example, 5i02 as the substrate 1, Si, GaAg, 5i3Hs, etc. as the thin film 2, and Si, W, GaAs jnP as the thin film 3 to be deposited.
etc.

Examples of the present invention are shown in the drawings for a method of growing a Si crystal at a desired position on an amorphous insulating substrate such as SiO2 and forming various electronic devices on the surface of this Si single crystal using the above-mentioned principle. The explanation will be based on.

FIG. i1 and FIG. 2 are process diagrams for explaining an embodiment of the present invention, and show a process for simultaneously manufacturing a thyristor, a bipolar transistor, and a resistor as various types of electronic elements on the same insulating substrate.

First, as shown in FIG. 1(A), a thin film [non-nucleation surface (SHDS)] 5 with a low nucleation density (DNs) that enables selective nucleation is formed on the base substrate 4, and then Various types of 5eed [5eed] having a sufficiently large Si nucleation density (DNL) compared to the thin film 5 with a small nucleation density ([1Ns) and a sufficiently small area so that only a single nucleus grows at the desired position. Nucleation surface (981November 7.8.9
form. The nucleation density (DNL) of each material in tjSi diagram (A) is nucleation surface 7>nucleation surface 8>nucleation surface 9
>Non-nucleation surface 5. The size, crystal structure, and composition of the base substrate 4 may be arbitrary, and it may be a substrate on which functional elements are formed using ordinary semiconductor technology. As a material for forming the non-nucleation surface (Ssos) 5, for example, S
i02 and deposited on the substrate 4 by atmospheric pressure CVD. In addition, the material for forming the nucleation surfaces (SNDL) 7, 8, and 9 is 1, for example, by ion implantation at a dose of 1×1011 pieces/ctm for the nucleation surface 7? , in the case of nucleation surface 8, 1×1016 pieces/cm2. For nucleation surface 9, lX10
The nucleation density is controlled as 16/am2. 5ee
The sizes of d7, 8, and 9 are approximately 1 to 4 pm and approximately square. As another material for the nucleation surfaces 7, 8.9, for example, 5i3Na can be used, which can be deposited by low pressure CVD and then formed through a photoetching process. In this case, the suitable size of the nucleation surfaces 7, 8.9 is approximately square with a size of about 1 to 48 Lm and a thickness of about 300 mm.

Next, as shown in FIG. 1(A), epitaxial growth is performed only on the nucleation surface (SNDL) 7 using the usual epitaxial I&L method. At this time, the nucleation conditions are adjusted appropriately. If set, the non-nucleation surface (Ssos
) 5 and the other nucleation surfaces (SNDL) 8 and 9, Si nuclei are not formed, and Si nuclei can be selectively nucleated only on the nucleation surface (SNDL) 7. The conditions for this are
Although it varies depending on the source gas type, 1For example, mol% with H2
5iHzC in comparison! 21.2%, HCl 2.4%,
A doping gas (PH3, 8206, etc.) is mixed with this only in the desired flow 11, and the temperature is 960°C and the pressure is 150To.
Supplied under conditions of rr.

On the wood flow side, as shown in FIG. 1(A), in the initial stage of single crystal growth, an n-type doping gas is used to grow an n-type Si single crystal 6 of an appropriate size. After that, as shown in FIG. 1(B), the doping gas is switched to p-type and n-type S! p-type Si single crystal 1 on single crystal 6
0 is continuously grown epitaxially. At this time, a p-type Si single crystal can also be grown on the nucleation surface (SNDL) 8 by changing conditions such as the gas system, gas flow rate, temperature, and pressure.

The conditions in this case differ depending on the source gas type, temperature, and pressure, as described above, but the source gas type is, for example, 5iH2CI21.2% and HCl20% in a molar percentage ratio with H2, and the doping gas (PH3, 8206, etc.) in the desired amount, temperature 960°C, pressure 150T.
Supplied under conditions of orr.

Furthermore, as shown in FIG. 1(C), the n-type Sl
By switching the doping gas to n-type under the conditions of crystal growth, P-type S on the nucleation surface (SHDL) 7
An n-type Si single crystal 11 of an appropriate size is epitaxially grown continuously on the i single crystal 10, the p-type Si single crystal lO1 on the nucleation surface (Ssot) 8, and the n-type Si single crystal 11 on the nucleation surface (SNDL) 9. Thus, as shown in FIG. 1(C), n-p-
An island-shaped Si single crystal consisting of n layers is created, and the nucleation surface (
An island-shaped Si single crystal consisting of continuously laminated n-p layers is fabricated on the nucleation surface (SNCIL) 8.
) 9, an island-shaped Si single crystal consisting of only an n layer is produced.

Next, each island-shaped Si single crystal formed as described above is flattened to an appropriate height. Typical methods for this flattening include the roughing/boring method and the etch bag method.

The lapping/borising method is a method in which a Si single crystal is mechanically polished from above (lapping) and the surface is further polished to a mirror finish (borising) by chemical treatment and polishing.

In the etch bag method, a resist is flattened to an appropriate thickness so as to cover a Si single crystal, and then RIE (Reactive
resist and S by ve-Ion-Etching)
This is a method in which the i single crystals are etched together.

By such a planarization method, an annular Si single crystal consisting of a planarized n-p layer as shown in FIG. 2(A) can be obtained. Further, as shown in FIGS. 2(B) and 2(C), a semiconductor substrate is prepared by separating the outer region by a conventional etching method. Here, the semiconductor substrate shown in FIG. 2(B) has a nucleation surface (SNDL) 8 in FIG. 1(D).
The semiconductor substrate shown in FIG. 2(C), which corresponds to a Si single crystal consisting of an n-p-n layer formed on the nucleation surface (SNDL) 7 in FIG. 1(G), is formed on the nucleation surface (SNDL) 7 in FIG. n-p-
It corresponds to a Si single crystal consisting of npn layers. Then, a thyristor, a bipolar transistor, and a resistor are formed on the semiconductor base material produced in this way. As this formation method, a normal semiconductor element manufacturing process can be used. That is, as shown in FIG. 2(B), a base electrode ((B) in the figure) is formed in the p-type semiconductor region inside the semiconductor substrate.
), a collector electrode (
By forming an emitter ((E) in the figure) in the other n-type semiconductor region 9 ((C) in the figure), an n-p-n type bipolar transistor is manufactured. Furthermore, as shown in FIG. 2(C), a cathode electrode (Fig. (Middle (K)), a thyristor is manufactured by connecting a gate electrode ((G) in the figure) to one of the inner p-type semiconductor regions and an anode electrode ((A) in the figure) to the other p-type semiconductor region. be able to. Furthermore, a resistor is created in the semiconductor base material formed on the nucleation surface (SNDL) 9 in FIG. 1(D). When forming the above-mentioned element, after flattening the island-shaped Si single crystal as shown in FIG. 1(C), Si02
An insulating pattern 14 is formed, a contact hole is formed by a normal phosphorography process, and the electrode is connected to the contact hole through, for example, an AI main electrode.

Although the above embodiment shows a method for manufacturing three types of electronic devices, according to the present invention, the type and number of devices to be formed on the same substrate can be selected as appropriate. Needless to say, in addition to the above-mentioned thyristors, bipolar transistors, and resistors, for example, nMOS,
It is possible to produce many types of elements such as pMOs and diodes.

(Effects of the Invention) As explained above, according to the method for manufacturing a semiconductor base material of the present invention, a semiconductor region made of a desired single crystal can be formed at a desired position of a single semiconductor base material, It becomes possible to simultaneously manufacture various electronic devices on a single semiconductor substrate.

[Brief explanation of drawings]

1(A) to (D) are process diagrams showing the method for manufacturing a semiconductor substrate of the present invention, FIG. 2(A) is a plan view of the semiconductor substrate in the manufacturing process of the semiconductor substrate of the present invention, and FIG. Figures 2 (B) and (C) are plan views showing specific examples of electronic devices fabricated on the semiconductor substrate, and Figures 3 (A) and (B) are single crystal configurations formed on an insulating substrate. FIGS. 4(A) and 4(B), which are schematic partial cross-sectional views showing an example, are illustrations of the selective deposition method. 1...Substrate 2...5eed 3...Island-shaped single crystal 4...Underlying substrate 5...Thin film [non-nucleation surface (SNDS)]6.11...
・N-type Si single crystal 7, 8, 9---seed [nucleation surface (5801
Month 10...P-type Si single crystal agent Patent attorney Johei Yamashita (C) (D) No. 10 (A)

Claims (1)

[Claims] A non-nucleation surface (S_N_D_S) with a low nucleation density and a nucleation density (N
A plurality of nucleation surfaces (
S_N_D_L) and these nucleation surfaces (S_N_
At the stage of growing a single crystal centered on a single nucleus grown on the nucleation surface (D_L), the nucleation density (ND_L) of the plurality of nucleation planes (S_N_D_L) is
) After growing a single crystal on the nucleation surface (S_N_D_L) with a large nucleation density (ND_L), a nucleation surface (S_N_D_L) with the next largest nucleation density (ND_L) has a nucleation surface different from the single crystal due to conditions different from the nucleation conditions. While growing a single crystal, this single crystal is grown on a nucleation surface (S_N_D_L) having a larger nucleation density (ND_L) than the nucleation surface (S_N_D_L).
A method for manufacturing a semiconductor substrate, characterized in that a desired continuous semiconductor region is formed on each of the nucleation surfaces (S_N_D_L) by forming a desired continuous semiconductor region on each of the nucleation surfaces (S_N_D_L).