JPS63239867A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To obtain a nondestructive reading memory of a sole element with a simple structure at a high speed by forming a source region and a drain region, and at least statically electrically interrupted charge storage region between a channel forming region and a gate electrode. CONSTITUTION:A P-type GaAs layer 103 is etched to a depth having no static continuity with a charge storage layer 112 at source region 107 and drain region 109 at both positions for holding a gate electrode 105. When a source electrode 108 and a drain electrode 110 are electrically continuous, the energy of the layer 112 is reduced lower than the Fermi energy (EF) of the electrode 108, but the electric continuity between the electrode 108 and the region 112 is interrupted by the hill of a potential between a channel forming region 111 and the region 112. Thus, the state that electrons are stored is '1' (or '0') at the region 112, the state that the electrons are not stored is '0' (or '1') to write information, and information can be nondestructively read by the conduction of the different channel forming regions of the two states.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed, low-power semiconductor memory element.

[Conventional technology]

Conventionally, as a semiconductor memory element similar to the present invention, the one shown in FIG. 7 has been known (J, A.

Cooper, J.R., M.R., Melloc.
In FIG. 7, 1 is a semi-insulating GaAs substrate, 2 is a p-type GaAs layer, 3 is an undoped AQ GaAs layer, and 4 is a semi-insulating GaAs substrate.
and 6 are n+ GaAs layers, 5, 7 and 9 are ohmic electrodes, 8 is n0 region, 10 and 12 are p+ region 1
1 and 13 are ohmic electrodes. With the above element, non-destructive readout is possible with one element, as will be explained below. First, a positive voltage relative to the electrode 9 is applied to the ohmic electrode 7 . If a positive voltage is applied to the electrode 5 in this state, electrons flow from the electrode 9 to the electrode 7, and the n.GaAs
Electrons are accumulated directly under the layer 6 as shown by the marks in the figure.

However, unless a positive voltage is applied to the ohmic electrode 5, electrons will not be accumulated directly under the n'GaAs layer 6. In other words, by applying a voltage to the ohmic electrode WA5, the n'GaAs layer This means that information has been written in the electron storage layer directly below 6. The above information can be read out non-destructively in the form of a change in conductivity between electrode 11 and electrode 13. That is, n+GaAs
If there is an electron storage layer directly below layer 6, n'GaAs
Since the electric field from layer 6 is shielded by the electron accumulation layer, p-type GaAs! ! The depletion layer 12 does not reach the semi-insulating substrate 1 as shown by the broken line 14, and the depletion layer 12 does not reach the semi-insulating substrate 1.
and electrode 13 are electrically connected. The above n”GaA
If there is no electron storage layer directly below the s-layer 6, the depletion layer reaches the semi-insulating substrate 1, and the electrodes 11 and 13 are electrically isolated.

[Problem that the invention seeks to solve]

The conventional element described above has the following problems. First, due to the structure of the element, there is a
Two electrodes 9, 5 and 7 must be provided. Therefore, there is a structural limit to bringing the electrodes 11 and 13 closer together, and it is essential to shorten the distance between the two electrodes in order to speed up the device. Not suitable for high speed. Second, in the conventional element described above, holes are used as current carriers between the electrodes 11 and 13. As is well known, G.
The mobility of holes in a A s is one-tenth or less of that of electrons.

- Therefore, the above-mentioned conventional element is structurally unsuitable for increasing speed. Thirdly, the conventional device described above has a complicated device structure, and highly accurate process control is required in order to obtain good uniformity and reproducibility. Therefore, it cannot be applied to large-scale memory LSIs with insufficient processing margin.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor memory element that is a single-element non-destructive read memory that is high-speed and has a simple structure.

[Means for solving problems]

The above object is to provide a semiconductor memory element having at least a source region, a drain region, a gate electrode, and a channel formation region, in which the source region and the drain region are at least statically electrically connected between the channel formation region and the gate electrode. This is achieved by providing a blocked charge storage region.

[Effect]

The present invention provides an n-channel field effect transistor including a single source region, a single drain region, a single channel forming region, and a single gate electrode, in which between the channel forming region and the gate electrode, A potential well that is statically electrically isolated from the source and drain electrodes is provided.The state in which electrons are accumulated in the well is defined as 1 (or 0), and the state in which no electrons are accumulated in the well is defined as O.
The most important feature is that information is written as (or 1), and that information is read non-destructively by the conductivity of the channel forming region which is - depending on the above two states.

The present invention differs from the prior art in the following points.

First, in the present invention, the arrangement of the source electrode, gate electrode, and drain electrode is the same as that of a normal field effect transistor, and there is only a single electrode (gate electrode) between the source electrode and the drain electrode. On the other hand, in the conventional technology, there are three electrodes (5 in Fig. 7) between the source electrode and the drain electrode.
, 7°9). Therefore, there is a structural limit to speeding up by reducing the distance between the source electrode and the drain electrode, but the present invention does not have this limit and can realize a higher speed device. Second, the present invention uses only electrons and does not use holes, whereas the prior art uses both electrons and holes. As is well known, the traveling speed of holes is slower than that of electrons (l/10 or less in the case of GaAs). Therefore, in the prior art, the operating speed of the device is limited by holes, whereas the present invention does not have the above limitations and can realize a high-speed device.・Thirdly, the conventional technology is
Since the device structure is complex, including two gate electrodes, two p+ regions, two p-type ohmic electrodes, one n1 region, and one n-type ohmic electrode, it is an acceptable process to obtain good uniformity. Although there is little margin, the device structure and manufacturing process of the present invention are simpler, which is advantageous in obtaining uniformity and reproducibility.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of a semiconductor memory element according to the present invention, FIG. 2 is an energy band diagram showing the operating principle of the above embodiment, and FIG. 3 is a diagram showing electrical characteristics of the above embodiment. FIG. 4 is an energy band diagram of the second embodiment of the present invention,
FIG. 5 is a sectional view showing the third embodiment of the present invention, and in FIG. 6, (a) is an energy band diagram of the third embodiment,
(b) is an energy band diagram of the fourth embodiment, and (c) is an energy band diagram of the fifth embodiment.

First Embodiment In FIG. 1, 101 is a semi-insulating GaAs substrate;
2 is n-type AQxGal-xAJ (e.g. x = 0.3
．． Impurity concentration I x 10” am-3+ fiAg2
00A), 103 hap-type GaAs layer (for example, film thickness 500
), 104 is A Q y G 81-yAJ! 7 (for example, impurity concentration 10"C1m-' or less v'!=0.4
5. 105 is a gate electrode made of an n1 type GaAs layer (eg, 500 layers thick), 106 is a metal III provided to reduce gate resistance (eg, W Si film), 107. 109 are each, for example, Si
Source and drain n+ formed by ion implantation
The regions 108 and 110 respectively represent a source electrode and a drain electrode made of, for example, AuGe/Ni.

111 is a channel forming region, and 112 is a charge storage region. The p-type GaAs layer 103 is etched to such a depth that the source region 107 and drain region 109 have no static conduction with the charge storage layer 112 at both positions sandwiching the gate electrode 105 .

The operating principle of the above element is illustrated in the energy band diagram of Fig. 2 and Io (drain current) - VG (
This will be explained using a characteristic diagram (gate voltage). FIG. 2(a) is an energy band diagram in a state where no voltage is applied to the gate electrode 105. In this state, the channel forming region 11
What is the energy of 1?

Since the Fermi energy E of the source electrode 108 is larger, an electron layer is not formed in the channel forming region 111. Therefore, the source electrode 108 and the drain electrode 1
There is no electrical continuity with 10.

When a positive gate voltage VG is applied to the gate electrode 105, the energy of the channel formation region 111 changes from the point where VG exceeds the threshold value vT□ to the Fermi energy of the source electrode 108 (EF ), an electronic layer is formed in the channel forming region 111.

Therefore, source electrode 108 and drain electrode 110 are electrically connected. At this time, the energy of the charge storage region 112 also becomes smaller than the Fermi energy of the source electrode 108 (EF in FIG. 2(b)), but due to the potential hill between the channel formation region 111 and the charge storage region 112, Source electrode 108 and charge storage region 11
Since electrical continuity with the charge storage region 11 is cut off, the charge storage region 11
Channel forming region 1 in which no charge is accumulated in 2
The electron density of the electron layer at 11 is the gate voltage V.

Therefore, the drain current IO increases with the gate voltage Va (see FIG. 3(a)).

When the gate voltage VG becomes higher than the first critical voltage Vc, as shown in FIG. empty charge accumulation region 11
Move to 2. As a result, the electron density in the electron layer of the channel forming region 111 decreases significantly, and the drain current I
o decreases drastically as shown in FIG. 3(a). When the gate voltage VG is decreased from the above state, electrons are accumulated in the charge storage region 112 as shown in FIG. 2(d), and a state in which no electron layer is formed in the channel formation region is maintained. Ru. In other words, the source electrode 108 and the drain electrode 11
0 is kept electrically cut off (see Figure 3 (a)
)) At this time, the electrons accumulated in the charge storage region 112 are not in thermal equilibrium with the source electrode 108, but since there is a potential hill between the channel formation region 111 and the charge storage region 112, 10g does not flow out.

When the gate voltage VG becomes smaller than the second critical voltage VC2, the channel formation region 111 as shown in FIG.
The electrons cross the potential hill between the charge storage region 112 and the charge storage region 112 and flow into the channel formation region
Move to 11. The electrons become a transient current and flow out to the drain electrode 110 as shown by the broken line in FIG. 3(a). After the electrons stored in the charge storage region 112 are released, the source electrode 108 and the drain electrode 11
0 becomes electrically cut off again.

Thereafter, when the gate voltage VG is increased to bring the gate voltage to 0 volts, the state returns to the state described at the beginning in the explanation of this operating principle. This embodiment can be used as a non-destructive read memory. In other words, 1 (or O) indicates that there is an electron layer in the charge storage region 112, and 0 (or O) indicates that there is no electron layer in the charge storage region 112.
Alternatively, 1) may be used. Reading can be performed non-destructively using the drain current value ID when the gate voltage is a value v0 between the threshold value VT and the first critical voltage Vcm. When writing 1 (or 0), the gate voltage VG may be set to a value V□ larger than the critical voltage Vcm of −temperature 1. When writing 0 (or 1), gate voltage V
It is sufficient to set a once to a value v2 smaller than the second critical voltage VCz. Here 5. The values of the threshold value Vd, the first critical voltage vc1, and the second critical voltage Vc are respectively n-type A
QxGal-XAS1102, GaAs layer 103, and AQ, Ga0. It is a function of the film thickness and impurity concentration of AJ1104, and by appropriately setting these quantities, the desired V + vc1. It is possible to obtain the value of vc2.

As shown in the Io (drain current) vs. VG (gate voltage) characteristic example in FIG. 3(b), the threshold value VT is set to a negative value,
It is also possible to choose vo to be 0 volts and the absolute values of v and V2 to be equal.

As mentioned above, the device structure and manufacturing process of this example are simpler than those of the conventional example, and unlike the conventional example that uses both electrons and holes, this example is a non-conventional single element that uses only electrons. Since it is a destructive read memory, it is improved in terms of improved operating speed, uniformity, and reproducibility compared to the conventional example.

Second Embodiment FIG. 4 is an energy band diagram for explaining the second embodiment of the present invention. This embodiment is a p-type Ga in the first embodiment.
The As layer 1103 is made of AQ zGal-zAsNI103. '. Here, AQ composition 2 is n-type A Q x Ga
It is zero near the interface with the □-8As layer 102, and
It is zero near the interface with the AQyGal-yAs layer 104.

It is assumed that z changes continuously to take a non-zero value (for example, z = 0.2) at the center of the film. In this embodiment, it is necessary to continuously change the AQ composition, but since a p-type layer that affects the threshold value is not used, the threshold value can be controlled more easily than in the first embodiment. Improvements over the conventional example are the same as in the first embodiment.

Third embodiment FIG. 5 is a sectional view of an element showing a third embodiment of the present invention.

201 is a semi-insulating GaAs substrate, 202 is a GaAs layer (
For example, film thickness 2000), 203 is An xGa, -x
As layer (e.g. x = 0.2, film thickness 200), 204
205 is a GaAs layer (for example, thickness 300), and 205 is an AlyGa1-yAs layer (y = o, 4s, thickness 200).
206 is an n+ type GaAs layer, 207 is a metal film (for example, WSi film), 208 is an n+ type source region, 209 is a source electrode, 210 is an n+ type drain region, and 211 is a drain electrode. . here.

It is assumed that each of the layers 202, 203, 204, and 205 described above is an undoped (impurity concentration of 10"ell-' or less) semiconductor film.

212 is a channel forming region, and 213 is a charge storage region. The energy band of this example is shown in FIG. 6(a). The broken line in the figure indicates when the gate voltage VG is O volts,
The solid line indicates the case where the gate voltage is greater than the threshold value VT. The feature of this embodiment is that the semi-conductor layer used in this embodiment is only an undoped layer or an n+ type layer, so that it is difficult to control the threshold voltage VT, the first critical voltage VC, and the second critical voltage VC2. The accuracy of impurity concentration control required for this purpose is lower than that in the first and second embodiments, and a larger process margin can be secured. Improvements over the conventional example are the same as in the first embodiment.

Fourth Embodiment This embodiment is based on the undoped GaAs layer 204 of the third embodiment.
is replaced with an n+ type GaAs layer 204'.The feature of this embodiment is that the gate electrode 2 is replaced with an n+ type GaAs layer 204' compared to the third embodiment.
Since the capacitance between 06 and the channel forming region 212 is large, the mutual conductance in the state where no electrons are stored in the charge storage region 213, that is, in the state of 0 (or 1), is large compared to the third embodiment. It is. Improvements over the conventional example are the same as in the first embodiment.

Fifth Embodiment In this embodiment, the film thickness of the undoped GaAs layer 204 of the third embodiment is set to zero, and AQxGa□-xAgAs5
A12, G
a1-, which monotonically decreases toward the As5205 side.

Similar to the third embodiment, the features of this embodiment are that a large process margin can be taken, and that the difference between the threshold value V and the second critical voltage VC, IVT-VC21, can be made small. It is. The advantages of the conventional example are the same as those of the first embodiment.

〔Effect of the invention〕

As described above, in the semiconductor memory element according to the present invention, the semiconductor memory element has at least a source region, a drain region, a gate electrode, and a channel formation region. By providing a charge storage region that is electrically isolated at least statically, information can be written depending on the presence or absence of the electronic layer in the charge storage region, and information can be read non-destructively based on the conductivity of the electronic layer in the channel forming region. Because it is a single-element nondestructive readout memory that uses only electrons and has a simple configuration, it is suitable for miniaturization of elements, has the advantage of high operating speed, and a large margin in the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor memory element according to the present invention, FIGS. 2(a) and 2(e) are energy band diagrams showing the operating principle of the above embodiment, and FIG. 3(a) ,
(b) is a diagram showing the electrical characteristics of the above embodiment, and the fourth
The figure is an energy band diagram of the second embodiment of the present invention, FIG. 5 is a sectional view showing the third embodiment of the present invention, FIG. 6 is an energy band diagram, and (a) is the energy band diagram of the third embodiment. Band diagram, (b) is the energy band diagram of the fourth embodiment, (
c) is an energy band diagram of the fifth embodiment, and FIG. 7 is a sectional view showing a conventional semiconductor memory element. 105, 206... Gate electrode 107, 208... Source region 108, 209... Source electrode 109, 210... Drain region 110, 211... Drain electrode 111, 212... Channel forming region 112 , 213
...Charge storage area patent applicant Nippon Telegraph and Telephone Corporation Representative Patent Attorney Junyuki Nakamura Suketsu 1 Su (CI) Ko 2 Jiko 1 Ke 2 ■ (C) (e) ゛Total 3 thresholds 4 k ”::' Pick-up-1109 ÷ Japanese elementary school-1-103'-111102-
・Scold 5 l * 7 (, j n 1 i rei 61., F tsu'1

Claims (1)

[Scope of Claims] 1. In a semiconductor memory element having at least a source region, a drain region, a gate electrode, and a channel forming region, there is a static contact between the channel forming region and the gate electrode. 1. A semiconductor memory element characterized in that a charge storage region is provided with an electrically cut-off charge storage region. 2. The channel forming region and the charge storage region are the first
a first semiconductor layer made of a semiconductor; a second semiconductor layer made of a second semiconductor having a conduction band edge energy smaller than that of the first semiconductor; and a third semiconductor layer made of a third semiconductor having a conduction band edge energy larger than the second semiconductor. A region near the interface between the first semiconductor layer and the second semiconductor layer in the second semiconductor layer, and the second semiconductor layer and the third semiconductor in the second semiconductor layer in a stacked body in which three semiconductor layers are sequentially stacked. This is a region near the layer interface, where the metal film or n
A ^+ type semiconductor film is used as a gate electrode, and n^+ regions formed at both positions sandwiching the gate electrode, including at least the channel forming region, but not including the charge storage region, are formed as a source region and a drain region, respectively. 2. The semiconductor memory element according to claim 1, wherein the ohmic contact formed in contact with the source region is used as a source electrode, and the ohmic contact formed in contact with the drain region is used as a drain electrode. 3. The second semiconductor is a compound semiconductor, and by continuously changing the composition, the forbidden band width is continuously changed within the second semiconductor, and a local maximum value is obtained at the center of the second semiconductor layer. A semiconductor memory element according to claim 2, characterized in that: 4. The first semiconductor, second semiconductor, and third semiconductor are Al_xGa_1_−_xAs (0<x≦1), G
aAs, Al_yGa_1_-_yAs (0<y≦1)
A semiconductor memory element according to claim 2, characterized in that: 5. The first semiconductor, the second semiconductor, and the third semiconductor are Al_xGa_1_−_xAs (0<x≦1), A
l_yGa_1_-_yAs(0<y≦1), Al_z
The semiconductor memory element according to claim 3, characterized in that Ga_1_−_zAs (0<z≦1). 6. The first semiconductor, the second semiconductor, and the third semiconductor are each In_0_. _5_2Al_0_. _4_8As,I
n_0_. _5_3Ga_0_. _4_7As, In_
0__. _5_2Al_0_. The semiconductor memory element according to claim 2, characterized in that it is _4_8As. 7. The gate electrode has Ga between it and the third semiconductor layer.
The semiconductor memory element according to claim 4 or 5, characterized in that an As layer is inserted. 8. The gate electrode has Ind between it and the third semiconductor layer.
＿0＿． _5_3Ga_0_. The semiconductor memory element according to claim 6, wherein a _4_7As layer is inserted. 9. The channel forming region and the charge storage region are the first
a first semiconductor layer made of a semiconductor; and a second semiconductor layer made of a second semiconductor having a conduction band edge energy larger than that of the first semiconductor.
a third semiconductor layer made of a semiconductor layer, a third semiconductor having a conduction band edge energy smaller than that of the second semiconductor, and a fourth semiconductor layer made of a fourth semiconductor having a conduction band edge energy larger than the third semiconductor. and a region near the interface between the first semiconductor layer and the second semiconductor layer in the first semiconductor layer, and a metal formed in a part of the layered body, which is the third semiconductor layer, in a stacked body in which these layers are sequentially stacked. A film or an n^+ type semiconductor film is used as a gate electrode, and n^+ regions formed in regions sandwiching the gate electrode that include at least the channel formation region and do not include the charge storage region are respectively used as source regions. and a drain region, an ohmic contact formed in contact with the source region is used as a source electrode, and an ohmic contact formed in contact with the drain region is used as a drain electrode. memory element. 10. The first semiconductor, second semiconductor, third semiconductor, and fourth semiconductor are GaAs, Al_xGa_1_
−_xAs (0<x≦1), GaAs and Al_yG
The semiconductor memory element according to claim 9, characterized in that a_1_-_yAs (0<x≦1). 11. The first semiconductor, the second semiconductor, the third semiconductor, and the fourth semiconductor are each In_0_. _5_3Ga_0
＿． _4_7As, In_0_. _5_2Al_0_.
_4_8As, In_0_. _5_3Ga_0_. ＿４
_7As and In_0_. _5_2Al_0_. ＿４
The semiconductor memory element according to claim 9, characterized in that the semiconductor memory element is _8As. 12. The gate electrode has a G between it and the fourth semiconductor layer.
11. The semiconductor memory element according to claim 10, wherein an aAs layer is inserted. 13. The gate electrode has I between it and the fourth semiconductor layer.
n_0_. _5_3Ga_0_. _4_7 The semiconductor memory element according to claim 11, wherein an As layer is inserted.