JPS63237287A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent influence of supply voltage fluctuation upon non-selected blocks by providing a changeover means between an electric power supply for opposed electrodes of memory cells in plural blocks and these blocks and turning everything off except the selected blocks. CONSTITUTION:Nch transfer gates 6a and 6b are provided as the changeover means between the VSG electric supply 5 and memory cell array blocks 1a and 1b and on-off control is performed by signals phia and phib. By this constitu tion, since the connection is cut off to all blocks but the selected ones, the fluctuation of the VSG in the limited selected blocks does not influence the non-selected blocks, thus improving the reliability of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory 4f1 device, and particularly to connection of a voltage supply power to a capacitive counter electrode of a memory element.

[Conventional technology]

FIG. 2 is a schematic diagram showing a memory element portion of a DRAM, which is an example of a conventional semiconductor memory device. This conventional example includes a memory cell array having memory cells at each intersection of a plurality of word lines and bit lines, and the 8-memory cell array is divided into two blocks. The memory cell array is provided with a cell plate electrode voltage power source (Vs. power source) for applying a predetermined voltage to the opposing electrode (cell plate) of the memory cell. In the figure, la and lb are memory cell array blocks, 2a,
2b is a memory cell, 3a, 3b are word lines, 4a, 4b
5 is a bit line, and 5 is a V and G power supply provided commonly to both memory cell array blocks.

In this conventional example, since there is one system of V3G electric a5, any one memory cell array pro-ref (for example, la
) is selected and operated, the voltage fluctuation caused by the operation is transmitted to the unselected memory cell array block (for example, lb) via the VSC-power supply 5 wiring, and the
The influence of the fluctuation will extend to unselected memory cell array blocks.

-a, in order to reduce current consumption, only the block to which the selected memory cell belongs is activated during the active cycle, that is, a sensing operation is performed, and the other blocks are kept in an inactive state. This is desirable.

[Problem that the invention seeks to solve]

Since the conventional semiconductor memory device is configured as described above, there is a problem in that the influence of VSC fluctuation during operation always affects all memory cell blocks.

This invention was made to solve the above-mentioned problems, and the VSC in one memory cell array block is
An object of the present invention is to obtain a semiconductor memory device that can prevent voltage fluctuations from affecting other memory cell array blocks.

[Means for solving problems]

The semiconductor memory device according to the present invention has a configuration in which the connection between the VSC power source and each memory cell array block is turned on, and the connection between the two is turned on.
A switching means is provided to turn off all connections other than the connection to the selected memory cell array block.

[Effect]

In this invention, since the switching means turns on the connection of the VSG power supply to the selected memory cell array block and turns off the connection to the unselected blocks, the VSC voltage during operation of the selected memory cell array block It is possible to prevent fluctuations in (1) from affecting unselected blocks via the connection wiring of the G power supply.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In the figure, the same symbols as in Figure 2 indicate the same things,
6a, 6b are N-channel transfer gates which are switching means provided between the VSG power supply 5 and each memory cell array block la, lb, respectively. The on/off state is controlled by the signal φ. Here, the φ and φゎ signals are, for example, RAS and RA, respectively.
The output signal and RAS of the NAND circuit with 8 as input.

This is the output signal of the NAND circuit which inputs RA8.

In a semiconductor memory device having such a configuration, by tossing the φ signal at high level and the φb times signal ° low level, the transfer gate 6a is closed and the transfer gate 6a is closed.
6b is open, and the VSa power is supplied only to the memory cell array block 1a. At this time, the wiring of the viG power supply 5 to the memory cell array block 1b is cut off, so fluctuations in the VSC voltage in the memory cell array block 1a, that is, the selected block, do not affect the non-selected storage elements in the same block. However, it is not transmitted to the non-selected memory cell array block 1b and has no effect.

In the above embodiment, an N'-channel transfer gate is used as the switching means, but it may of course be a P-channel transfer gate.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention,
A switching means is provided between the SG power supply and each block to turn on and off the connections between them, and all connections except for the selected memory cell array block are turned off. . This has the effect of preventing voltage fluctuations from affecting non-selected blocks and improving the reliability of the device.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram showing a conventional semiconductor memory device. In the figure, la and lb are memory cell array blocks,
2a, 2b are memory cells, 3a, 3b are word lines, 4a
, 4b is a bit line, 5 is a VSG power supply, and 6a and 6b are transfer gates. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a semiconductor memory device equipped with a memory cell array divided into a plurality of blocks, a connection is established between the power supply for applying voltage to the opposing electrodes of the memory cells of the plurality of blocks and each of the blocks. A semiconductor memory device characterized by being provided with switching means for turning on and off. (2) The semiconductor memory device according to claim 1, wherein the switching means is a transfer gate.