JPS6323676U - - Google Patents
Info
- Publication number
- JPS6323676U JPS6323676U JP11735586U JP11735586U JPS6323676U JP S6323676 U JPS6323676 U JP S6323676U JP 11735586 U JP11735586 U JP 11735586U JP 11735586 U JP11735586 U JP 11735586U JP S6323676 U JPS6323676 U JP S6323676U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- doppler
- filter
- zero
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000001228 spectrum Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図はこの考案の動作を説明するための図、
第３図は従来のレーダ信号処理装置のブロツク図
、第４図は第３図の動作を説明する図である。
図において、１はパルスドツプラフイルタ、２
は定誤警報確率回路、３は周波数軸論理和回路、
４はゼロドツプラ検出回路、５はゲート回路、６
はクラツタ、７はクラツタ消え残り、８は目標信
号を示す。なお、図中同一符号は同一あるいは相
当部分を示す。
Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a diagram for explaining the operation of this invention,
FIG. 3 is a block diagram of a conventional radar signal processing device, and FIG. 4 is a diagram explaining the operation of FIG. 3. In the figure, 1 is a pulse Doppler filter, 2
is a constant false alarm probability circuit, 3 is a frequency axis OR circuit,
4 is a zero Doppler detection circuit, 5 is a gate circuit, 6
indicates the clutter, 7 indicates the clutter remains, and 8 indicates the target signal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
で構成されたパルスドツプラフイルタと、前記パ
ルスドツプラフイルタ出力から目標を検出する定
誤警報確率回路と、前記定誤警報確率回路の出力
を周波数軸方向に論理和する周波数軸論理和回路
と、上記パルスドツプラフイルタ出力から、ドツ
プラ周波数がゼロ付近のスペクトルを有する信号
を検出するゼロドツプラ検出回路と、前記ゼロド
ツプラ検出回路出力により制御され、上記周波数
軸論理和回路を禁止制御するゲート回路とを備え
たことを特徴とするレーダ信号処理装置。 A pulse Doppler filter composed of a digital filter or a fast Fourier transformer, a constant false alarm probability circuit that detects a target from the output of the pulse Doppler filter, and the output of the constant false alarm probability circuit are logically summed in the frequency axis direction. a frequency axis OR circuit that detects a signal having a spectrum with a Doppler frequency near zero from the output of the pulse Doppler filter; and a zero Doppler detection circuit that is controlled by the output of the zero Doppler detection circuit, A radar signal processing device comprising: a gate circuit that performs prohibition control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11735586U JPS6323676U (en) | 1986-07-30 | 1986-07-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11735586U JPS6323676U (en) | 1986-07-30 | 1986-07-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6323676U true JPS6323676U (en) | 1988-02-16 |
Family
ID=31002789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11735586U Pending JPS6323676U (en) | 1986-07-30 | 1986-07-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6323676U (en) |
-
1986
- 1986-07-30 JP JP11735586U patent/JPS6323676U/ja active Pending
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