JPS63234458A - Drop-out detecting circuit - Google Patents

Abstract

PURPOSE:To surely detect a drop-out with simple circuit constitution by monitoring that the signal level of a digitized read signal is increased or reduced continuously during a prescribed number of samplings. CONSTITUTION:A most significant bit continuity number detecting circuit 34 consists of counter or the like, and a detection output is generated when the most significant bit has the same logic continuously during a prescribed number of samplings. This detection output is supplied as a drop-out detection signal to a drop-out correcting circuit. Data of the most significant bit of a subtraction signal is extracted by a most significant bit extracting circuit 42, and it is monitored by the most significant bit continuity number detecting circuit 43 that the most significant bit has the same logic continuously during a prescribed number of samplings, that is, the signal level is continuously increased (or reduced)) for a time longer than that for the absence of drop-out thereby detecting the drop-out.

Description

TECHNICAL FIELD The present invention relates to a dropout detection circuit, and more particularly to a dropout detection circuit in a recorded information reproducing apparatus that digitizes and processes a high frequency signal read from a recording medium.

BACKGROUND ART Conventionally, in a recorded information reproducing device, for example, a disc player that plays back a video disc on which a video signal has been subjected to FM modulation processing and is recorded, signal processing of the FM video signal read from the disc has been performed in an analog manner. It was common.

However, when considering the integration of circuits into ICs (integrated circuits), it is extremely advantageous to perform signal processing digitally rather than analogously, and it is also easier to achieve multifunctionality in the signal processing process. Since high image quality can also be achieved, the present applicant has already proposed a recorded information reproducing device that digitally processes signals read from a disc (see Japanese Patent Application No. 60-280711).
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By the way, in recorded information reproducing devices such as video disc players, signal loss, or dropout, may occur in the read signal from the recording medium due to scratches or dust on the recording medium, so this dropout is detected. It is necessary to compensate for this.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and provides a dropout detection circuit that can reliably detect dropouts with a simple circuit configuration in a recorded information reproducing device that performs signal processing digitally. The purpose is to

The dropout detection circuit according to the present invention is used in a recorded information reproducing apparatus that digitizes a read signal from a recording medium and processes the signal, by delaying the digitized read signal by a period equivalent to one sample, and comparing the delayed signal with the delayed signal. The configuration is such that a dropout is detected by subtracting the previous signal, extracting the data of the most significant bit from this subtracted signal, and detecting dropout when the logic of the most significant bit is continuously the same a predetermined number of times.

In other words, dropout is detected when the signal level of the digitized read signal continues to increase or decrease for a predetermined number of sampling times.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a recorded information reproducing apparatus including a dropout detection circuit according to the present invention. In the figure, an FM video signal read from a recording medium such as a video disc is supplied to an A/D converter 2 via an analog LPF (low pass filter) 1. L
PFI is for removing aliasing distortion in A/D conversion. The digital FM video signal output from the A/D converter 2 is supplied to a digital BPF (band pass filter) 3 and a dropout detection circuit 4 according to the present invention. The digital BPF 3 extracts only the components necessary for detecting the video signal from the A/D conversion output including the FM audio signal, and supplies the extracted components to the FM detection circuit 5 at the next stage.

As the FM detection circuit 5, for example, one having the configuration proposed by the present applicant in Japanese Patent Application No. 59-262481 can be used.

From the detection output of the FM detection circuit 5, only the baseband component of the video signal is extracted by a video LPF 6. The digitized video signal that has passed through the video LPF 6 is supplied to a dropout correction circuit 7 and a signal separation circuit 8. The dropout correction circuit 7 performs dropout correction in response to the dropout detection signal supplied from the dropout detection circuit 4.

The signal separation circuit 8 separates and extracts the horizontal synchronization signal, color burst signal, etc. contained in the digitized video signal, and supplies the separated signals to the clock generation circuit 9. The clock generation circuit 9 is
Based on the horizontal synchronization signal or color burst signal from the signal separation circuit 8 and the reference horizontal synchronization signal from the reference signal generation circuit 10, 4fsc (fsc is the subcarrier frequency) and 4Nfsc (N is an integer of 2 or more, for example 3 ) generates the clock for the PLL (phase
It has a locked loop) circuit configuration. The 4fsc and 4NfSC clocks generated here are used as clocks for digital signal processing, and the sampling clock of the A/D converter 2 and the clock for signal processing up to the video LPF 6 are set to 4Nfsc,
Downsampling is performed from the output to a 4fsc clock.

The digitized video signal output from the dropout correction circuit 7 is a 4fS signal generated by the clock generation circuit 9 based on the color burst signal extracted from the reproduced video signal.
The data is written into the buffer memory 11 by the C clock. Reading data from this buffer memory 11 is as follows:
This is done using a 4fsc reference clock generated by the reference signal generation circuit 10. In this way, by reading data from the buffer memory 11 using a stable reference clock unrelated to the reproduced video signal, jitter (time axis fluctuation) of the reproduced video signal can be absorbed. The digitized video signal read out from the buffer memory 11 is sent to a D/A (digital/analog) converter 1.
2, it is converted to analog and becomes the playback video output.

FIG. 2 is a block diagram showing one embodiment of the dropout detection circuit 4 according to the present invention. In the figure, the digitized video signal that is the output of the A/D converter 2 is delayed by a period equivalent to one sample in a delay circuit 40 having a delay amount equivalent to one sample period in the A/D converter 2, and is then converted to a subtracter. 41. In the subtracter 41, the delay circuit 40
The digitized video signal before the delay is subtracted from the delayed digitized video signal. This subtraction signal is supplied to the most significant bit extraction circuit 42, which extracts the most significant bit data. The logic (1, 0) of the most significant bit of the subtraction signal corresponds to the positive or negative polarity of the subtraction result. For example, in 2°S concompliment (2's complement), the logic "0#" corresponds to the positive polarity. , logic "12" represents a negative value.

The extracted most significant bit data is supplied to the most significant bit consecutive count detection circuit 43. The most significant bit consecutive number detecting circuit 43 is constituted by a counter or the like, and generates a detection output when the logic of the most significant bit is the same logic for a predetermined number of consecutive times. This detection output is supplied to the dropout correction circuit 7 (FIG. 1) as a dropout detection signal.

In such a configuration, when dropout occurs, as shown in FIG. 3(A), distortion may occur in the signal waveform read from the disk. The repetition of positive and negative amplitudes in a period is not completed when it should be completed, and the signal level continues to increase or decrease. Here, when the subtracter 41 calculates the amplitude difference between the signal after the digitalized video signal is delayed by the delay circuit 40 and the signal before the delay, that is, the amplitude difference between sample points, the topmost signal of the subtracted signal is calculated. For example, in the case of 2° S combination, the logic of the bit is "0" when the amplitude difference is positive, and "1" when it is negative. The positive and negative polarities of this amplitude difference are shown in Figure 3 (B).
It becomes as shown in .

At this time, as shown in the central part of the figure, a series of logic "1"s (or logic "0"s) means that the signal level read from the disk continues to increase (or decrease).

Therefore, the data of the most significant bit of the subtraction signal is extracted by the most significant bit extraction circuit 42, and the logic of this most significant bit is continuously the same a predetermined number of times (for example, four times in the embodiment shown in FIG. 3). That is, dropout can be detected by monitoring by the most significant bit consecutive number detection circuit 43 that the signal level continues to increase (or decrease) for a longer time than when there is no dropout.

In the above embodiment, the most significant bit consecutive number detection circuit 43 is configured to monitor whether the logic of the most significant bit remains the same a predetermined number of times using a counter or the like, but as shown in FIG. , a shift register 430 that sequentially stores the most significant bit data extracted by the most significant bit extraction circuit 43, and, for example, ro 000J and rl 1.
The configuration may include a reference pattern generation circuit 431 that generates a reference pattern of 11J, and a coincidence detection circuit 432 that detects coincidence between the output of the shift register 430 and the output of the reference pattern generation circuit 431.

Further, in the above embodiment, a video disk was used as an example of the recording medium, but a video tape may be used as long as a predetermined signal is modulated with a high frequency signal and recorded. .

As described in detail, the dropout detection circuit according to the present invention monitors whether the signal level of the read signal read from the recording medium and digitized continues to increase or decrease for a predetermined number of sampling times. Since the configuration is configured to detect dropout by this, dropout can be reliably detected with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a recorded information reproducing apparatus having a dropout detection circuit according to the present invention, and FIG.
The figure is a block diagram showing an embodiment of the dropout detection circuit according to the present invention, FIG. 3 is a diagram showing input and output waveforms of the A/D converter in FIG. 1, and FIG. 4 is the most significant bit in FIG. 2. FIG. 2 is a block diagram showing an example of the configuration of a continuous number detection circuit. Explanation of symbols of main parts 4...Dropout detection circuit 5...
FM detection circuit

Claims (1)

[Claims] A dropout detection circuit in a recorded information reproducing device that digitizes and processes a read signal from the recording medium when reproducing a signal modulated with a high frequency signal and recorded on a recording medium, the circuit detecting the digitized read signal. a delay means for delaying the output signal by a period equivalent to one sample; a subtraction means for subtracting the output signal of the delay means from the digitized read signal; and an extraction means for extracting data of the most significant bit from the output signal of the subtraction means. and a detection means for detecting that the logic of the most significant bit extracted by the extraction means is the same continuously a predetermined number of times, and the detection output of the detection means is used as a dropout detection signal. dropout detection circuit.