JPS632336A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS632336A JPS632336A JP14581386A JP14581386A JPS632336A JP S632336 A JPS632336 A JP S632336A JP 14581386 A JP14581386 A JP 14581386A JP 14581386 A JP14581386 A JP 14581386A JP S632336 A JPS632336 A JP S632336A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sealing
- mold
- card module
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000011347 resin Substances 0.000 claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 40
- 238000007789 sealing Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 abstract description 17
- 239000002184 metal Substances 0.000 abstract description 8
- 238000000465 moulding Methods 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法に係わシ、特に内部に
半導体素子を有し外面に外部装置と電気的に接続可能な
電極を有するノーイブリッドＩＣの樹脂封止方法に関す
るものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a semiconductor device having a semiconductor element inside and an electrode electrically connectable to an external device on the outside. The present invention relates to a resin sealing method for hybrid ICs.
第９図はこの種のノ・イブリッドＩＣとして例えばＩＣ
カードモジュールの樹脂封止方法を説明する図である。Figure 9 shows an example of this kind of hybrid IC.
It is a figure explaining the resin sealing method of a card module.
同図（、）はノ・イブリッドＩＣの封止前の外形図でｔ
りυ、同図において、１は基板、２は半導体素子、３は
基板上の配線、４は配線と半導体素子２とを電気的に接
続する金属細線である。The figure (,) is an outline drawing of hybrid IC before sealing.
In the figure, 1 is a substrate, 2 is a semiconductor element, 3 is a wiring on the substrate, and 4 is a thin metal wire that electrically connects the wiring and the semiconductor element 2.
５は半導体素子２の裏面側に形成された外部装置接続用
裏面電極、５は通常ハイブリッドＩＣで用いられている
封止用液状樹脂、６は液状樹脂５が広く流れるのを防ぐ
ダム基板、７は液状樹脂５を滴下するだめの装置である
。5 is a back electrode for external device connection formed on the back side of the semiconductor element 2; 5 is a sealing liquid resin usually used in hybrid ICs; 6 is a dam board that prevents the liquid resin 5 from flowing widely; 7 is a device for dropping liquid resin 5.
第９図（ｂ）は樹脂５で封止した後のノ・イブリッドＩ
Ｃの断面図である。通常のハイブリッドＩＣの場合、封
止はこの状態で終わるか、または再度外装用の樹脂封止
全行なう。しかし、近年ＩＣカードモジュールでは、封
止表面の平坦性が厳しく要求されるため、封止後、第９
図（Ｃ）に示すように封止された樹脂５の表面を研磨し
、平坦な樹脂封止面を形成してＩＣカードモジュール１
０を得ていた。なお、第９図（ｂ） ＋ （ｃ）におい
て、８は外部装置の電極と接触または接続し、半導体素
子２と外部装置との間で電気的な信号のやシ取シを行な
うために設けた裏面電極である。FIG. 9(b) shows the Hybrid I after being sealed with resin 5.
FIG. In the case of a normal hybrid IC, the sealing ends in this state, or the entire exterior resin sealing is performed again. However, in recent years, in IC card modules, flatness of the sealing surface is strictly required.
As shown in Figure (C), the surface of the sealed resin 5 is polished to form a flat resin sealed surface, and the IC card module 1
I was getting 0. In FIGS. 9(b) and 9(c), reference numeral 8 is provided to contact or connect with an electrode of an external device and to exchange electrical signals between the semiconductor element 2 and the external device. This is the back electrode.
このようにして形成されたＩＣカードモジュール１０は
第１０図（１）に平面図、同図（ｂ）に側面図で示した
ようにＩＣカード本体１１内に組み込まれてＩＣカード
が構成され、矢印Ａ方向に外部装置に挿入することによ
り、ＩＣカードモジュール１０の裏面電極８が外部装置
と電気的に接続され、その機能が動作する０
〔発明が解決しようとする問題点〕
従来のＩＣカードモジュールに代表される、裏面に電極
８金持ち、樹脂５により薄く封止されるハイブリッドＩ
Ｃは、封止工程に研磨工程を必要とするため、工程が複
雑となる０
また、研磨工程では、封止樹脂表面は単に平面的なもの
しか得られず、封止樹脂表面に意識的に模様を掘）込ん
だ）、封止樹脂表面および側面を必要に応じて種々の形
状にすることができない。The IC card module 10 thus formed is incorporated into the IC card main body 11 to form an IC card, as shown in FIG. 10 (1) in a plan view and in FIG. 10 (b) in a side view. By inserting the IC card module 10 into an external device in the direction of arrow A, the back electrode 8 of the IC card module 10 is electrically connected to the external device, and its functions operate.0 [Problems to be solved by the invention] Conventional IC card Hybrid I, represented by a module, has 8 electrodes on the back and is thinly sealed with resin 5.
C requires a polishing process in the sealing process, which complicates the process.0 In addition, in the polishing process, the sealing resin surface can only be flat, and the sealing resin surface is intentionally It is not possible to make the surface and side surfaces of the sealing resin into various shapes as required.
さらに従来の方法では、封止工程の機械化および大量生
産化が困難で研磨工程での不良もあり、コストも高くな
る。また、従来の方法で用いていた液状の封止樹脂は、
通常の低圧トランスファー法で用いる樹脂と比べると信
頼性が低いなどの問題があった。Furthermore, with conventional methods, it is difficult to mechanize the sealing process and mass-produce, and there are also defects in the polishing process, resulting in high costs. In addition, the liquid sealing resin used in the conventional method is
There were problems such as lower reliability compared to resins used in normal low-pressure transfer methods.
この発明は、上記のような問題点を解決するためになさ
れたもので、ハイブリッドＩＣの樹脂封止面を荏意な形
状にでき、また、その寸法精度も正確なものが得られ、
かつ−度に大量に生産でき、樹脂の硬化時間も短かいこ
とから、大量生産全可能とし、さらに外形を任意の形状
に形成することができる半導体装置の製造方法を提供す
ることを目的としている。This invention was made to solve the above-mentioned problems, and it is possible to make the resin-sealed surface of a hybrid IC into an arbitrary shape, and to obtain accurate dimensional accuracy.
Moreover, the present invention aims to provide a method for manufacturing a semiconductor device that can be produced in large quantities at a time, and the curing time of the resin is short, so that mass production is possible and furthermore, the external shape can be formed into an arbitrary shape. .
この発明による半導体装置の製造方法は、ノ・イブリッ
ドＩＣ’ｔ−金型成形法によシ樹脂封止するものである
。The method of manufacturing a semiconductor device according to the present invention is to seal the semiconductor device with a resin by a non-hybrid IC't-mold molding method.
この発明における半導体装置の製造方法は、ノ・イブリ
ッドＩＣを金型成形法によって樹脂封止されるので、外
形の形状を任意にかつ正確にできるとともに、樹脂対土
工程が簡易になシ、大量生産に適する。また、信頼性の
高い固形の樹脂を使うことにより、信頼性も向上する。In the method of manufacturing a semiconductor device according to the present invention, since a non-hybrid IC is encapsulated with resin by a molding method, the outer shape can be arbitrarily and accurately, the resin-to-soil process is simple, and large quantities can be manufactured. Suitable for production. Furthermore, reliability is also improved by using a highly reliable solid resin.
以下、図面を用いてこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明による半導体装置の製造方法に用いら
れる封止装置の金製装置部を示す図で、同図（凰）は斜
視図、同図（ｂ）はその要部断面図である。FIG. 1 is a diagram showing a metal device part of a sealing device used in the method for manufacturing a semiconductor device according to the present invention, where the figure (denoted) is a perspective view and FIG. 1B is a sectional view of the main part thereof. .
同図において、金型２０は上金型２１と下金盤２２とか
ら構成されており、下金型２２にはＩＣカードモジュー
ル組立体を挿入する凹状のキャビティ部２２＆が設けら
れている。このキャビティ部２２ｍの形状が封止後のモ
ジュールの形状となる。In the figure, a mold 20 is composed of an upper mold 21 and a lower mold plate 22, and the lower mold 22 is provided with a concave cavity 22& into which an IC card module assembly is inserted. The shape of this cavity portion 22m becomes the shape of the module after sealing.
また、この下金型２２にはキャビティ部２２．へ樹脂を
導入するゲート２２ｂおよびランナー２２ｃが設けられ
ている。The lower mold 22 also has a cavity portion 22. A gate 22b and a runner 22c are provided for introducing resin into the resin.
このように構成された金型２０は、゛まず、下金型２２
を固定し、上金型２１を開放し、下金型２２のキャビテ
ィ部２２ｂ内に、表面に内部配線３を形成した基板１上
に半導体素子２を搭載して金属配線４によシワイヤボン
ドされたＩＣカードモジュール組立体９を挿入する。次
に上金型２１を閉じ、外部から溶はした樹脂をランナー
２２ｂおよびゲー） ２２ｃを介してキャビティ部２１
Ｃ内に加圧注入し、樹脂封止を行なう。しかる後、上金
型２１を開放し、キャビティ部り２ａ内には第２図（轟
）、（ｂ）に示すようにＩＣカードモジュール組立体９
の上面が樹脂１２により封止されたＩＣカードモジュー
ル１３が完成される。The mold 20 configured in this way is constructed by ``first, the lower mold 22
was fixed, the upper mold 21 was opened, and the semiconductor element 2 was mounted in the cavity 22b of the lower mold 22 on the substrate 1 on which the internal wiring 3 was formed on the surface, and was wire-bonded with the metal wiring 4. Insert the IC card module assembly 9. Next, the upper mold 21 is closed, and the melted resin is poured from the outside into the cavity 21 through the runner 22b and the gage 22c.
Inject under pressure into C and seal with resin. After that, the upper mold 21 is opened, and the IC card module assembly 9 is placed in the cavity part 2a as shown in FIG. 2 (Todoroki) and (b).
An IC card module 13 whose upper surface is sealed with resin 12 is completed.
このような封止方法によれば、ＩＣカードモジュール組
立体９の上面を金型成形法により樹脂封止したので、封
止樹脂１２０表面形状が平坦化されかつ外形寸法が高精
度なＩＣカードモジュール１３が容易に製作することが
できる。According to such a sealing method, since the upper surface of the IC card module assembly 9 is sealed with resin by the molding method, the IC card module can have a flat surface shape of the sealing resin 120 and a highly accurate external dimension. 13 can be easily manufactured.
なお、上記実施例では、ＩＣカードモジュール１３に内
蔵された半導体素子２が１個の場合について説明したが
、内蔵される半導体素子２の数は特に限定されない。In the above embodiment, a case has been described in which the IC card module 13 has one built-in semiconductor element 2, but the number of built-in semiconductor elements 2 is not particularly limited.
また、上記実施例では、ＩＣカードモジュール封止面を
広げ、表面を平坦に形成しだが、上金型２１により成形
した封止面の形状は任意である。Further, in the above embodiment, the IC card module sealing surface is widened and the surface is formed flat, but the shape of the sealing surface formed by the upper mold 21 may be arbitrary.
また、上記実施例では、ＩＣカードモジュール組立体９
の表面のみを金型２０で封止し、だが、工Ｃカードモジ
ュール組立体９の表面および側面を封止しても良い。Further, in the above embodiment, the IC card module assembly 9
Although only the surface of the C-card module assembly 9 is sealed with the mold 20, the surface and side surfaces of the C-card module assembly 9 may be sealed.
また、この発明の他の実施例として第３図に示すように
上金型２１の表面に線状に凸部２１ａを設けることによ
シ、第４図に示すように封止樹脂１２の表面に凹溝１２
ｍを形成することが可能とな）、各種の模様を堀込むこ
とができる。また、この発明のさらに他の実施例として
第５図に示すようにＩＣカードモジュール組立体９の上
面および側面を封止樹脂１２によシ封止することによっ
てその側面に前述したカード本体１１に係止できる係止
部１２ｂを設けることができる。また、ＩＣカードモジ
ュール組立体９の側面を封止する場合、基板１の寸法精
度が厳しくなくても、封止後のＩＣカードモジュール１
３の寸法精度は、金型２０によシ、高精度に設定するこ
とができる。Further, as another embodiment of the present invention, as shown in FIG. 3, by providing a linear convex portion 21a on the surface of the upper mold 21, the surface of the sealing resin 12 as shown in FIG. Concave groove 12
m), and various patterns can be carved. In still another embodiment of the present invention, as shown in FIG. 5, the top and side surfaces of the IC card module assembly 9 are sealed with a sealing resin 12, so that the above-described card body 11 can be attached to the side surfaces. A locking portion 12b that can be locked can be provided. In addition, when sealing the side surface of the IC card module assembly 9, even if the dimensional accuracy of the substrate 1 is not strict, the IC card module 1 after sealing
The dimensional accuracy of No. 3 can be set to a high degree of accuracy depending on the mold 20.
また、この発明の他の実施例としては、第６図に示すよ
うにＩＣカードモジュール組立体Ｓ上にダム基板６を接
着するとともにこのダム基板６に樹脂導入用の溝６ａを
設けて下金型２２のキャビティ２２＆内に挿入し、上金
型２１を閉じて樹脂封止を行ない、第７図に示すように
ＩＣカードモジュール組立体９内の半導体素子２上が樹
脂１２によシ封止され、表面が平坦化されたＩＣカード
モジュール１３が完成される。また、半導体素子２が２
個の場合には第８図に示すようなＩＣカードモジュール
１３が形成される。Further, as another embodiment of the present invention, as shown in FIG. 6, a dam board 6 is bonded onto the IC card module assembly S, and a groove 6a for resin introduction is provided in the dam board 6 to form a lower plate. The IC card module assembly 9 is inserted into the cavity 22& of the mold 22, and the upper mold 21 is closed to perform resin sealing, and as shown in FIG. The IC card module 13 whose surface has been flattened is completed. Further, the semiconductor element 2 is
In the case of 1, an IC card module 13 as shown in FIG. 8 is formed.
以上のように、この発明によれば、裏面に外部装置と電
気的接続可能な電極を有するノ・イブリッドＩＣを、金
型を用いて樹脂封止したので、封止面の形状を任意の形
にかつ正確に成形でき、樹脂封止時の作業性が向上し、
大量生産が可能となる。As described above, according to the present invention, a hybrid IC having electrodes on the back surface that can be electrically connected to an external device is sealed with resin using a mold, so that the shape of the sealing surface can be formed into any shape. It can be molded quickly and accurately, improving workability during resin sealing.
Mass production becomes possible.
また、基板の外形寸法精度が低くても、封止後の外形寸
法は金型で制御できるため、高精度な外形寸法を有する
半導体装置が得られる効果がある。Further, even if the external dimension accuracy of the substrate is low, the external dimensions after sealing can be controlled by the mold, so there is an effect that a semiconductor device having highly accurate external dimensions can be obtained.
第１図（ａ） 、 （ｂ）はこの発明による半導体装置
の製造方法の一実施例を説明するための封止装置の金型
装置部を示す斜視図、その要部断面図、第２図（ａ）
ｔ （ｂ）はこの発明による半導体装置の製造方法によ
シ製作された半導体装Ｒを示す図、第３図（＆）。
（ｂ）はこの発明の他の実施例を説明するだめの封止装
置の金型装置部を示す斜視図、その要部断面図、第４図
はこの発明の他の実施例によシ製作された半導体装置を
示す斜視図、第５図はこの発明のさらに他の実施例によ
り製作された半導体装置を示す断面図、第６図（１Ｌ）
ｔ （ｂ）はこの発明の池の実施例を説明するための
封止装置の金型装置部を示す斜視図、第７図、第８図は
この発明の他の実施例により製作された半導体装置を示
す斜視図、第９図（ａ） Ｉ （ｂ） ｆ （ｅ）は従
来の半導体装置の製造方法を説明する斜視図、その断面
−１第１０図（ａ） 、 （ｂ）はＩＣカードモジュー
ルをカード本体に組込んだＩＣカードを示す平面図、そ
の側面図でおる。
１・・・・基板、２φ・・・半導体素子、３・・・・内
部配線、４ψ・・−金属配線、９・・・・ＩＣカードモ
ジュール組立体、１２・・・・樹脂、１２ａ・・・・凹
溝、１２ｂφ・・・係止部、１３・・−−ＩＣカードモ
ジュール。
第２図
（ａ）
（ｂ）
ｉ３：ＩＣ７７−ド七シ蜀−Ｉし
ＰＣ’Ｊ Ｆｌ ぐの
第３図
２１０＝凸町
第４図
第５図
１２ｂ：イ禾Ｊ−者７
第６図
第７図
第８図
第９図
第１０図
ＣＧ）
（ｂ）
只FIGS. 1(a) and 1(b) are a perspective view showing a mold device part of a sealing device for explaining one embodiment of a method for manufacturing a semiconductor device according to the present invention, a sectional view of the main part thereof, and FIG. (a)
t(b) is a diagram showing a semiconductor device R manufactured by the method for manufacturing a semiconductor device according to the present invention, and FIG. 3(&). (b) is a perspective view showing a mold device part of a sealing device for explaining another embodiment of the present invention, and a sectional view of the main part thereof, and FIG. FIG. 5 is a sectional view showing a semiconductor device manufactured according to still another embodiment of the present invention, and FIG. 6 (1L)
t (b) is a perspective view showing a mold device part of a sealing device for explaining an embodiment of the present invention, and FIGS. 7 and 8 show semiconductors manufactured according to other embodiments of this invention. A perspective view showing the device, FIGS. 9(a), 1(b), and (e) are perspective views illustrating the conventional manufacturing method of a semiconductor device, and its cross section-1. FIGS. 10(a) and (b) are ICs. 1 is a plan view and a side view of an IC card in which a card module is incorporated into a card body. DESCRIPTION OF SYMBOLS 1...Substrate, 2φ...Semiconductor element, 3...Internal wiring, 4ψ...-Metal wiring, 9...IC card module assembly, 12...Resin, 12a... ...Concave groove, 12bφ...Locking portion, 13...--IC card module. Figure 2 (a) (b) i3: IC77-Doshichishu-Ishi PC'J Fl Guno Figure 3 210 = Kokomachi Figure 4 Figure 5 12b: Ihe J-person 7 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 CG) (b) Only
Claims (1)
イブリッドＩＣを、一対の金型間に挿入し、該ハイブリ
ッドＩＣの少なくとも表面を樹脂封止することを特徴と
した半導体装置の製造方法。A method of manufacturing a semiconductor device, comprising inserting a hybrid IC having a semiconductor element mounted on a substrate and having external electrodes on the outer surface between a pair of molds, and sealing at least the surface of the hybrid IC with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14581386A JPS632336A (en) | 1986-06-20 | 1986-06-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14581386A JPS632336A (en) | 1986-06-20 | 1986-06-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS632336A true JPS632336A (en) | 1988-01-07 |
Family
ID=15393733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14581386A Pending JPS632336A (en) | 1986-06-20 | 1986-06-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS632336A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1505858A2 (en) * | 2003-07-22 | 2005-02-09 | Matsushita Electric Industrial Co., Ltd. | Circuit module and manufacturing method thereof |
-
1986
- 1986-06-20 JP JP14581386A patent/JPS632336A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1505858A2 (en) * | 2003-07-22 | 2005-02-09 | Matsushita Electric Industrial Co., Ltd. | Circuit module and manufacturing method thereof |
| EP1505858A3 (en) * | 2003-07-22 | 2008-04-23 | Matsushita Electric Industrial Co., Ltd. | Circuit module and manufacturing method thereof |
| US8003438B2 (en) | 2003-07-22 | 2011-08-23 | Panasonic Corporation | Circuit module and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5244840A (en) | Method for manufacturing an encapsulated IC card having a molded frame and a circuit board | |
| KR100280762B1 (en) | Thermally Reinforced Semiconductor Devices Having Exposed Backsides and Methods of Manufacturing the Same | |
| US6358773B1 (en) | Method of making substrate for use in forming image sensor package | |
| US4688152A (en) | Molded pin grid array package GPT | |
| US5184209A (en) | Ic card and manufacturing method therefor | |
| US4812420A (en) | Method of producing a semiconductor device having a light transparent window | |
| EP0390996A2 (en) | IC card module | |
| JPH05343588A (en) | Partial mold-type pcb chip-carrier type package | |
| US5192682A (en) | Manufacturing method for thin semiconductor device assemblies | |
| US5665296A (en) | Molding technique for molding plastic packages | |
| JPS632336A (en) | Manufacture of semiconductor device | |
| JPS6215142B2 (en) | ||
| JPH02204096A (en) | Manufacture of ic card | |
| JPH06132449A (en) | Semiconductor device | |
| JP5605971B2 (en) | Electronic device and manufacturing method thereof | |
| JP4086534B2 (en) | Memory card and molding method | |
| JPS62202539A (en) | Integrated circuit package and manufacture thereof | |
| JPH02241042A (en) | Ic sealing method | |
| JPH04177844A (en) | Production of resin-sealed semiconductor device | |
| KR200189300Y1 (en) | Semiconductor molding die | |
| JPH04373138A (en) | Resin sealed semiconductor device and its manufacture | |
| JPH0990007A (en) | Magnetic sensor and its packaging method | |
| JPH10135257A (en) | Device manufacturing resin sealed semiconductor and die therefor | |
| JPS6145379B2 (en) | ||
| KR940009603B1 (en) | Semiconductor package & fabricating mothod thereof |