JPS63233425A - Display controller for data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a display control device for a data processing device as set forth in claim 1.

BACKGROUND OF THE INVENTION Conventionally, display control devices of this type have a single display refresh memory in which a character code is stored or a map of pixels or graphic dots is stored. I remember it was either. The family of CPUs for personal use, which can be controlled by industrially standardized programs, has a refresh memory with a capacity for a memory map equal to the number of dots that can be displayed on the display. , it was impossible for this system to store character codes and graphic pixels at the same time. In such a display, if different parts of the image are to be displayed on the video unit, in particular if character areas are to be displayed together with the graphic images, the characters in such areas are not initially stored in the refresh memory. It was necessary for the data to be stored in the form of a dot map.

According to already proposed character display control devices, the refresh memory can be divided into different areas, each area having a function for scrolling text.
), that is, they are individually controlled for vertical movement in the horizontal alignment of text. To accomplish this, an auxiliary memory stores a list of strings to be displayed. Therefore, on the one hand, the regions vertically divide the display screen, and on the other hand, the refresh memory is stored in a consistent manner in all regions according to a single character mode.

Display control devices are already known that have multiple pages of refresh memory and display color images by reading these pages in parallel. According to such a display control device, it is possible to store the first page using character codes, while storing other pages using dot maps. Display operations can select complementary zones on the first page and other pages to replace graphic portions with written text. However, even with such a control device, it is not possible to display characters and display different types of graphics at the same time, so it is not considered to be flexible.

(Problems to be Solved by the Invention) An object of the present invention is to provide a display control device in which a refresh memory can simultaneously store and display character codes and dot maps.

This object is achieved by the display control device of the invention as defined by the features of claim 1.

(Field of Application of the Invention) The field of application of the invention can be found, for example, in workstations such as those in banks. In banks, 1
By multiple display operations, the operator can check the customer's transaction amount stored in character code and at the same time check the customer's signature stored in graphic form.

(Example) The following description is made to explain a preferred embodiment of the invention, and together with the accompanying drawings, the invention is not limited to this embodiment.

A. System overview (Figure 1) Please refer to Figure 1. Reference numeral 10 indicates a central control unit (c) of a computer (for example, a computer for personal use).
pu) and data address channel (data
address bus) 11, RAM 12, ROM 13
It is connected to the.

Additionally, the data address bus 11 controls the display of data and images on a series of input/output units (I10 units), such as a keyboard 14, a printer 15, a floppy disk unit 16, and a display controller 17 (e.g. a display unit 18 such as a CRT). do)
It is connected to the.

B. Display control device 17 (Fig. 2) (a) Cathode ray tube control device 19 The display control device 17 is a cathode ray tube control device (C
RTC) 19. This cathode ray tube controller (CR)
TC) 19 is programmed to generate vertical and horizontal sync signals as well as raster address signals to control the display. Is this a cathode ray tube controller? 1t (CRTC) 19 has logic means for controlling various functions required for the display, such as cursor and image movement.8 For example, a cathode ray tube controller is
It consists of an integrated circuit (IC) known as D6345 (manufactured by Hitachi), which divides the image on the screen vertically into four segments, and each segment has an independent scrolling function and two independent cursors. It may also have the function of controlling the

For this purpose, the cathode ray tube controller 19 has a series of registers for controlling various functions. This register includes two registers for horizontal synchronization and vertical synchronization. It also has a register for indicating the position or cell of the character to be displayed as a multiple of the duration of the character or characters in the line. These will be explained in detail later.

(b) Overview of display mode The display control device 17 operates in a predetermined vertical (column)
) It is possible to control the display of characters according to a dot matrix or pixels consisting of X horizontal (ro-) numbers, or it is possible to control the display of a graphic consisting of pixels stored in memory according to a memory bit map.

The following display modes are provided in the standard video unit 18 which may be 640x400 pixels; 1) 80x25 character character mode corresponding to 8x16 pixels; 2>40x25 character character mode corresponding to 16x16 pixels. Modes: 3) High quality monochrome graphic mode consisting of 640 x 400 pixels; 4) Standard monochrome graphic mode consisting of 640 x 200 pixels; 5) High quality color graphic mode consisting of 320 x 400 pixels; 6) Standard color graphic mode consisting of 320 x 200 pixels; It should be clear from this that in character mode the display has the same defined resolution as in graphics mode of 640 x 400 pixels.

An 8x16 dot matrix defines the cells on the screen, so that the screen has a total of 2
000 cells.

(c) Outline of input control The logic means of the cathode ray tube controller 19 is controlled by an input/output register group 21 via a data bus 20. This data bus 20 is connected to the data address bus 11 via an interface 22. The input/output register group controls the display mode, control mode, and
Define operating conditions.

Display control device 17 further includes display refresh memory 23 . This display refresh memory 23 is connected to a cathode ray tube controller (CRTC) 19 via a latch 25 and a multiplexer 26. One address interface 24 is connected to the multiplexer 26 and the selector 44 and performs switching (selection) between the memory and the input/output register group.

°Finally, the logic means of the cathode ray tube controller, 19,
Sends an interrupt request signal to P'UIO and
0 can be notified to prevent unnecessary access to the memory 23 and register group 21. This interrupt request signal is transferred on the data address bus 11 via the interrupt interface 30.

(d) Outline of Display Operation Mode Switching According to the present invention, the display control device 17 can control the display unit 18 to perform the following operation switching. In other words, the display functions in one of the modes 1) to 6) above in accordance with standard conditions (standard mode), and the display operates in window mode (window mod).
This is e) switching between operations according to conditions (modes) as described later. In this window mode, it is possible to.

(e) Overview of refresh memory 23 The refresh memory 23 has a capacity of 32 bytes, and has an arbitration unit (an
To store a 0-character code, it is possible to select whether to store the character code or according to the pixel map of the displayed graphic based on the control of the arbiter unit. Refresh memory 23 is divided according to 2-byte word groups.

The first byte of this word group indicates the character code, and the next byte indicates the character's attributes - e.g., underline, inversion, character and background color, brightness, etc. according to the character being displayed. It indicates the characteristic features of the characters. 40X
One page consisting of 25 characters requires a memory capacity of 2 bytes, and one page consisting of 80x25 characters requires a memory capacity of 4 bytes, so this refresh memory 23
In the former case, a maximum of 16 pages can be accommodated, and in the latter case, a maximum of 8 pages can be accommodated.

Output from refresh memory 23 is latched 46
is maintained. For each single character display, the character code in latch 46 is used to address the ROM 27, which functions as a character generator, while the byte indicating its attributes is used to address the attribute decoder 28. The output of ROM 27 and the output of attribute decoder 28 will define the pixels to be displayed on the video display at each scan line. In the 40×25 character character mode, the character pattern generated by the same character generator (ROM) 27 in a known manner is transmitted to the cathode ray tube controller (
Each output bit is generated repeatedly during a horizontal scan under the control of the CRTC (CRTC) 19.

To store graphic pixels, the refresh memory 23 stores a map in which 1 bit corresponds to each pixel in the case of monochrome display, and 2 bits corresponds to each pixel in the case of color display. Memorize the map. In the latter case, two bits can define four colors for each pixel.

In the case of high quality display, the entire storage area of the refresh memory 23 can store one graphic page.

On the other hand, in the case of standard monochrome graphics mode, the capacity of 16 bytes of refresh memory 23 is sufficient to store one page, and therefore half of the storage area of refresh memory 23 is either unused or stored in another graphic page. used for memory. Braun tube control device (C
RTC) 19 controls the reading of the memory map of refresh memory 23 according to the lines of the raster scan sequence provided for control of display 18.

(To) In the case of monochrome display, the refresh memory 23 is assigned addresses 88000 to BFFFF (Fig. 4), 200
In the line standard graphics mode, the refresh memory 23 is divided into two 16-byte portions, which are connected to each other via a transceiver 47 and to the data bus 20 via a transceiver 48. ing.

Each 16-byte portion of the refresh memory 23 contains one display page; the odd lines (1, 3, 5...) in the first page (page-0) have the address 28000.
~89FFF, even number lines (2, 4, 6...
), when the signal of the 0th page (page=1) stored at addresses BAOOO to BBFFF is selected, the same thing occurs in the remaining half area of the refresh memory starting from address BCOOO. In addition, 320
In color graphics mode of x 200 pixels, each line is stored similarly, but the bits of each byte are paired for color selection, so each
The display of 4 dots is controlled by the byte.

In the high-definition monochrome graphic mode, the entire storage area of the refresh memory 23 provides one page of memory map. This storage is done according to the following table (see Figure 4); original nibble 1 line 1, 5, 9, 13, 1f, 21, 25, 29.
・・・・・・Address B8000-89FFF line
2, 6, 10, 14, 18, 22, 26.30...
...Address B^000-BIIFFF line 3,
7, 11, 15, 19, 23, 27.31...
Address BCOOO-RoDFFF line 4, 8, 12
, 18, 20, 24, 28.32...Address BEOOO-BFFFF (g) In the case of color display For color display, the RO that forms the color table is required.
M29 (FIG. 2) is addressed by the background mixer 49, the serial converter 31 (which converts the signal output from the mixer 50 into the signal to be displayed), and the attribute decoder 28,
Determines the color of the displayed pixel. mixer 49, mixer 5
0 further inputs a signal from the input/output register group via a latch 52 and a multiplexer 51, and also inputs a signal from the refresh memory 23 via another latch 53. In detail, the RO that forms the color table
M29 consists of two color tables (or palettes) that are selectively used as described below. A color table 29 in which the first palette consists of "black,""green,""red," and "yellow," and the second palette consists of "gray,""cyan,""magenta," and "white."
(The signal from ROM29 is the display unit)
This signal is sent to the interface 32 of the (CRT) 18 and achieves display control of the contents stored in the refresh memory 23.

(H) Display 18 The display 18 can be configured as a video display that performs a positive mode, that is, a monochrome display in which characters are displayed in black against a white background. The standard for such a display is to have a function of 640 x 640 pixels, so it is possible to display a graphic mode based on this number of pixels.In the zero character mode, the optical effect of expanding the "black" pixels , character patterns are displayed with different character trajectories on the negative display screen. As a result, a difference occurs between the negative character pattern modified with "inversion" and the display result on the screen.

Moreover, in character mode, conditioning can be done by known control circuits to display 640x480 pixels. In this case, the character matrix is selected to be 8 x 15, while the character arrangement on the display is selected to be 8 x 32 characters. Positive character patterns in the standard mode as well as in the 8x15 matrix mode are generated by a second character generator 34 (ROM 34) as described below.

If a positive image is displayed, refresh R
The output turn signal from the zero character generator 34, of which the AM 23 has a capacity of 36 bytes, is sent to the serial converter 31 via the table 29. Serial converter 31
The display of a negative monochrome image is performed in the same way, by sending out a series of signals from the display 18 to control the display 18.

An OR circuit includes a mixer 50 and two character generators 27 and 34.
Make a binary connection with.

(S) Window mode In window mode, the cathode ray tube controller (C
The RTC) 19 conditions the means included in the selector 44 to address individual storage cells in the refresh memory 23 in order to display both according to the character code and according to the graphics mode. . This allows you to define any graphics window with multiple (integer) cells, or a number of columns or rows of cells representing a character matrix. can. In this case, the multiplexer 45
Add an offset to address 3. This offset value is calculated from cputo and refresh memory 2
3 (FIG. 5) assigned to addresses A3000-AFFFF of 0. In normal graphics mode, refresh memory 23 is divided into eight zones that constitute eight scan lines of cells. Address A3000-A
The first zone between 87FF and CRT controller F19
directly addressed by.

On the other hand, the second to eighth zones are successively addressed by a fixed offset number of '800J in hexadecimal.

Accordingly, the scan lines of the screen are stored in the refresh memory 23 according to a sequence as shown below as Table n. This sequence is refresh memory 2
3 is for the first 16 bytes and the remaining 1
A similar sequence is repeated for the 6th byte.

Cart α1 Line 1, 9.17, 25.33...Address A3000-A87F F Line 2, 10.18,
28.34...Address A3800-A8FFF
Line 3, 11, 19, 2f, 35...Address A9000-A9f FF line 4, 12, 20, 2
8.36...Address A9800-A9F F
F line 5, 13, 21, 29.37...Address AAOOO-AA7FF line 6.14, 22, 3
0.38----7 Tre XAA80G-AAFFF line 7, 15, 23, 31.39...Address ABOOO-AB7FF line 8, 16, 24, 32
．． 40... Addresses AB800-ABFFF Similarly, in the high definition graphics mode, the total area of refresh memory 23 is divided into 16 zones, which zones constitute 16 scan lines of storage cells.

The storage sequence of the refresh memory 23 is shown in the table ■
It is indicated by.

ta≦Processing I Line 1.17, 33, 49.65・・・・・・・・・
・Address A3000-A87FF line 2.18,
34,50.66・・・・・・Address A380
0-A8F F F Line 3, 19, 35, 51.
67・・・・・・Address A9000-A97F
'F line 4, 20, 38, 52.68...
...Address A9800-A9F F F line 5
, 21.37, 53.69... Address AAOOO-AA7FF line 6, 22, 38, 54
．． F0・・・・・・Address AA80Q-AAF
F F line f, 23.39, 55.71...
...Address ABOOO-A87FF line 8
, 24.40, 56.72... Address AB800-ABFFF line 9, 25, 41, 57
．． 73・・・・・・Address ACOOO-AC7
FF line 10, 26, 42. Ra8,74...
...Address AC30O-ACF F F line 1
1, 27, 43, 59.75...Address ADOOO-AD7FF line 12.28, 44, 6
0.76・・・・・・Address AD800-ADF
FF line 13, 29, 45, 61°77...
...Address AEOOO-AE7FF line 14,
30.48, 62.78...Address AE
800-AEFFF line 15, 31, 47, 63.
79・・・・・・Address AFOQO-AP7FF
Line 16, 32.48, 84.80...
Address A F2O3-A FFF F Auxiliary RAM 33 The display controller 17 (FIG. 1) further includes an auxiliary read/write memory (RAM) 33 (FIG. 2) that is addressed via the interface 24. Furthermore, it has an arbitration multiplexer C11i (stop unit) 45. This auxiliary RAM 33 is connected to the multiplexer 26 via a latch 54 and further connected to the data bus 20 via a transceiver 55. The display controller 19 can be responsive to each character code stored in the refresh memory 23 and can be responsive to each graphics storage cell stored in the memory 23. Each graphic storage cell includes an auxiliary RAM 33.
The auxiliary RAM 33 has a capacity of 4 bytes, and the content of this 1 byte of information is a window descriptor code that defines the mode of each cell to be displayed. , AOOOO-A7FFF (FIG. 6) is assigned, so that the information corresponding to two pages on the screen can be included. This auxiliary RAM 33 appropriately edits the window descriptor (co++pile) in each byte.
This window descriptor has a close relationship with the data stored in the refresh memory 23.

These two memories 23 and 33 can be accessed by the CPU 10 at any time, either sequentially or individually, without waiting for a response period. This sequentiality is as the description element is stored at each time during storage into the cell. On the other hand, in the individual case, the contents of a cell having a certain memory content or the window descriptor itself can be individually written independently from other parts, while taking into account the close relationship with respect to alphanumeric mode and graphic mode. It is possible to change.

To be more specific, the display mode is defined by three bits of the lowest three digits, 0, 1.2. These 3 bits are Do, Di, D
Let's express it as 2. The three bits of the window descriptor byte are decoded according to the table (3) shown below.

0 0 0 640x400 graphics 1 0 0 320x400 graphics palette 10 1 1 320x400 graphics palette 20 1 0 64
0x200 graphics 1 1 0 32
0x200 graphic palette 11 1 1
320x200 graphic information 0 0 1 80x25 characters 1 0
Bits D3-D7 of the 140x25 character window descriptor code byte are used to define color in graphics mode and to define various attributes of the character in character mode.

This will become clear from the description below.

Mixers 49 and 50 The graphic signal output from the refresh memory 23 (FIG. 2), the pattern signal from the character generator (ROM) 27 and 34, and the signal from the attribute decoder 28 are sent to the background mixer 49 and the serial The input/output register group 21 (FIG. 3) is loaded via the mixer 50 that loads the converter 31.
The various units of the display controller 17 are controlled by a group of input/output registers 21. This input/output register group consists of registers 36 to 42 (Figure 3).
, the output bits from these become signals indicating various parameters required by the display.

Specifically, register 36 functions as a read-only unit and constitutes a first status register.

Its bit 0 provides a signal of DISPN=1 during the repeated scanning period in the vertical and horizontal directions. Further, bit 3 provides a signal of VSYN=0 during the repeated scanning period in the vertical direction. Also, bit 4 gives a MONO=O signal for a color CRT, and a MONO=O signal for a monochrome CRT.
Give a signal of NO=1.

Register 37 functions as a read-only unit;
Configure a second status register. Its bit 0 is I
A signal of NT I = 1 is given to permit access to the other input/output register group 21, and a signal of INTI=O is given to permit reading of the register 37 by CPU10. Further, bit 1 gives a signal of ■NTM=1 to permit access to the refresh memory 23. Bit 2 can also provide a WIND signal to select a display condition or mode. To explain this in detail, when a signal of WIND=O is supplied, the operation is in the standard mode, and when a signal of WIND=1 is supplied, the operation is in the window mode.

Also, bit 3 is MO for positive display.
It provides a NI=0 signal and a MONI=1 signal for a normal 640x400 display. This MONI signal therefore also controls the selection of the two character generators 27 and 34.

Register 38 constitutes a color set register. These bits 0, 1, and 2 are BLAT signals, GLA
A T signal and a RALT signal are respectively supplied. These signals define the three primary colors. Further, bit 5 selects color palette 1 when the C0=O signal is supplied, and selects color palette 2 when the C0=1 signal is supplied. Bit 3 provides the ILAT signal that defines the gold color tone.

Bit 4 provides the ALTB signal that defines the color tone of each color of displayed data in color graphics mode.

Registers 39, 41, and 42 constitute a first mode register, a second mode register, and a third mode register, respectively.

Bit O of the first mode register 39 defines a character mode of 80x25 characters. Supply HRES=1 signal, 4
Provides an HRES=0 signal that defines a character mode of 0X25. Also, bit 1 is □GRAPR=1 signal in graphic mode, GR in character mode.
Provides an APP=0 signal.

Bit 3 enables display
The VIDE=1 signal is input to the VIDE=1 signal, and the VI
Provides DE=0 signal. Bit 4 provides a BWO=1 signal during monochrome graphics mode and a BWO=O signal during color graphics mode. Bit 5 provides the BLIB signal only during character mode. BL
A signal of EB=1 enables blinking of characters with an attribute of intensity of background=1.

Bit O of the second mode register 41 is 640×400
High-quality monochrome graphics mode, as well as 320×
O when in 400 pixel high quality color graphic mode
Provides LIM=1 signal. When in character mode, this second
The mode register 41 of the cathode ray tube controller (CRT)
C) Allow 19 to address refresh memory 23. Dot 3 of this register 41 provides a PAGE=0 signal for selecting one half of the refresh memory 23 and a PAGE=1 signal for selecting the other half of the refresh memory 23 in the standard graphics mode. Bit 6 provides a UNDE=1 signal that enables the explanation of the attribute to be underlined. For example, all characters defined in blue by the attribute byte are displayed in white with an underline. Bit 7 provides the ABWF=1 signal to enable the second status register 37.

The last register 42 constitutes the third mode register.

Its bit O provides the poso signal, which is used only for positive video display. POS0
When =1, the negative display is enabled and the character generator 27 is activated. Bit 5 is the MODO=O signal indicating a 640x400 format display;
It provides a MODO=1 signal indicating an 480 format display.

In window mode, the first status register 36;
the output signals of the second status register 37, the third mode register 42, and the VIDE signal of the first mode register 39;
Both ABWF signals of the second mode register 41 maintain their functionality without any changes. However, the functions performed by the other signals are controlled by bits D3-D7 of the window descriptor code.

Specifically, in character mode, D3. of this window descriptor code. The D4 bit is the BLIB signal of the first mode register 39 and the UND signal of the second mode register 41.
Each performs the same function as a signal. In graphics mode, bits D3-D7 of the window descriptor code are connected to the BLAT signal of color set register 38, GL
They each perform the same functions as the AT signal, ILAT signal, and ALTB signal.

Practical Example of C0 Operation Mode The operation mode of the display control device 17 is as follows; Assume that the display is of the negative monochrome type. Associated signals are stored in registers 36-42. When operating in standard mode, bit 2 of second status register 37 is set to provide a WIND=O signal.

This signal conditions cathode ray tube controller (CRTC) 19 to control the effect CRTCl 9 has on refresh memory 23 in dependence on the parameter signals provided from registers 36-42, as described above.

When operating in windowed mode, bit 2 of second status register 37 is now set to provide a WIND=1 signal. This signal conditions the cathode ray tube controller (CRTC) 19 so that the CRTC 19 acts on the refresh memory 23 and the auxiliary memory 33;
Color set register 38 and second mode register 41
0-6 outputs are deenergized.

It is further assumed here that a page with a monochrome display as shown in FIG. 6 is stored. This display screen is 8
An elongated portion 60 consisting of three character lines in 0X25 character mode, a portion 61 formed by a graphic image consisting of 30X15 cells according to 64o x 400 graphics mode, and 10X1 in 40X25 character mode.
It consists of a section 62 consisting of 5 characters, a section 63 formed by a graphic image consisting of 30.times.15 cells according to the 640.times.200 graphics mode, and an elongated section 64 consisting of 7 lines of characters in the 80.times.25 character mode.

A3000-A37F F of refresh memory 23
24.0 words are stored in the area. Each word is formed by one byte of a character code and one byte indicating its attribute. Therefore, 240 bytes are stored in the auxiliary memory 33, and each of these bytes is 80×2
Indicates 5-character mode. Therefore, these bytes all have bits DO=1, D1=O1, D2=0.

For the fourth row of storage cells, the 30x16 word is the fifth
The memory map is stored in the refresh memory 23 according to the layout shown in the figure. In detail, the cathode ray tube controller 19 only needs to define the address of the first line of each storage cell in the zone A 8000-A 8700, and the subsequent addresses within the same cell will follow this defined address. Hexadecimal constant 800 in address
It is automatically determined by adding .

The first line of words in the graphics storage cell is associated with a 30-byte window description element in auxiliary memory 33. These window descriptors are DO=O, D1=
It has a bit of O2D2=0. These storage cells are followed by 10 for a string in 40X25 character mode.
Word is memorized. Each of these words dominates two adjacent cells on the screen. In the same manner as in the above case, the auxiliary memory 33 stores DO=1, D1=O1D.
2=1 bit. Since 20 bytes are stored with the window descriptor, it will be clear that every character of the form 16x16 requires two window description elements.Finally, in the cell in the fourth row, Therefore, according to the layout of FIG. 5, even when 30×8 words are stored in the refresh memory 23 with a memory map in 600×200 mode, the cathode ray tube controller fi (CRTC) 19 stores zones A 8000-A 8700. Define only the first line of each storage cell in . Within the same storage cell, subsequent lines are automatically addressed by adding the hexadecimal constant 800 to the address. Again, the first line of a word of graphics cells is associated with a 30-byte window descriptor in auxiliary memory 33. The fourth row of cells therefore requires a total of 80 window descriptors.

The other 14 lines in the part where the windows 61, 62, 63 appear are stored in a similar manner.6 According to the 80x25 character mode, the last 7 lines of characters are stored in zones A3000-A8 of the refresh memory 23.
560 words are stored in 7FF.

Meanwhile, a 560-byte window descriptor is stored in the auxiliary memory 33 in association with this.

Therefore, 2000 window descriptors are required for this one screen page.

Auxiliary memory 33 records a significant number of window descriptors, regardless of the mode in which the individual windows are recorded.

(Summary of Operations) To display, the cathode ray tube controller f19 sequentially addresses the words of the first zone of the refresh memory 23. If each word is associated with a window descriptor indicating a character mode, the first byte of the word is output as the address of the character generator 27, and the second byte is the address of the string of storage cells. During the scanning period, it is input to the attribute decoder 28.

If a word in the first zone of the refresh memory 23 is associated with a window descriptor indicating one of the graphics modes, during the scanning period of the line of storage cells the cathode ray tube controller 19 controls the graphics mode. Words are addressed according to the refresh memory 23 read sequence determined by the mode. the output from the character generator 27 or 34 in character mode, as well as the output from the attribute decoder 28;
Further, the output of the refresh memory 23 in the graphic mode is input to the mixer 50.

Mixer 50 mixes graphic and character signals. The output from mixer 50 reaches color table 29 via serial converter 31.

The output of color table 29 controls the video screen via display interface 32.

(Other Embodiments) Various improvements and modifications may be made to the control device without departing from the scope of the present invention. For example, the refresh memory 23 may be configured with memory groups of various storage capacity levels. It is possible to do so.

This memory group may be used to define each pixel by grouping interrelated bits at various storage capacity levels to form an image with improved color selection.

The display control device 17 may be used to control different display units, for example, a positive display and a negative display.

The positive display may be operated only in the standard mode, so that the character generator 34 is not connected to the refresh memory 23.

[Brief explanation of the drawing]

FIG. 1 shows a partial diagram of a computer for personal use. Also shown is the display control device of the present invention. FIG. 2 is an example of a block diagram of a display control device according to an embodiment of the present invention. FIG. 3 is a block diagram of an input/output register group of the display control device of FIG. 2. FIG. 4 is a schematic diagram of a refresh memory for graphics data in standard mode. FIG. 5 is a schematic diagram of a refresh memory for graphics data in windowed mode. FIG. 6 shows an example of display operation, and also shows the storage of a corresponding window descriptor in association with this example. (Brief explanation of symbols) 17...Display control device 19...
- Braun tube controller (CRTC) 20... Data bus 21... Input/output register group 22... Data interface 23...
...Refresh memory 24...Address interface 25.4
6, 52, 53.54...Latch 26.45.51
......Multiplexer 27.34...Character generator (for negative, positive) 28...Attribute decoder 29...Color table 31... Serial converter 32...Display interface 33.
...Auxiliary memory (4 people)

Claims (1)

[Claims] 1) A refresh memory (23) for storing the code of displayed characters or the dot map of graphics to be displayed, and a predetermined length x width for each character code. a character generator (27, 34) for generating character dots according to a matrix of
17) In a display control device for a processing device, the control unit divides the refresh memory (23) in window mode to display a series of independent windows and to display character codes or dots in each window. means (33) comprising logic means (HF-50) operative to selectively record maps and further conditioning said control unit (17) to control the display according to the recording mode in each window; A display control device for a data processing device, characterized in that the display control device is provided with: 2) A patent characterized in that a second refresh memory (23) for storing character codes or dot maps in standard mode and means (37) for selecting window mode and standard mode are provided. A display control device according to claim 1. 3) each window stored according to the dot map has a plurality of columns and rows consisting of a set of matrices;
3. A display control device according to claim 1, wherein each window contains an integer number of graphics cells of the same dimensions as the matrix. 4) The conditioning means may include window descriptor codes (D0-D) for each character cell and each graphic cell.
7) A display control device according to claim 3, characterized in that it has an auxiliary memory (33) for storing. 5) The window descriptor code (D0-D7) has a function of selecting a character definition and a graphic image definition from a group of definitions given by the control unit. 5. The display control device according to item 4. 6) In the graphics mode, the logic means (HF
-50) automatically addresses successive lines of dots of cells in a given refresh memory portion conditioned by a window descriptor. display control device. 7) A display control device according to claim 6, characterized in that the memory portion is automatically determined by adding a constant to the address of the first line of cells. 8) Claim 4, characterized in that it has a series of registers (21) for setting display parameters, one register (37) of which has the function of controlling the selection means. The display control device according to any one of items 1 to 7. 9) a character generator (27, 34) addressable by a character code stored in said memory (23) during a series of line scans of the display; in window mode said memory portion 9. The display control device according to claim 8, wherein the display control device is automatically addressed from the address of the first line. 10) means (37) for controlling the display of characters in positive mode, wherein said character generator (27, 34) has an area (34) for character generation in positive mode;
) and if windowed mode is selected,
10. Display control device according to claim 1, characterized in that it comprises means (42) for disabling said area of the character generator.