JPS63233390A - Radar jamming instrument - Google Patents

Radar jamming instrument

Info

Publication number
JPS63233390A
JPS63233390A JP6625087A JP6625087A JPS63233390A JP S63233390 A JPS63233390 A JP S63233390A JP 6625087 A JP6625087 A JP 6625087A JP 6625087 A JP6625087 A JP 6625087A JP S63233390 A JPS63233390 A JP S63233390A
Authority
JP
Japan
Prior art keywords
signal
delay
circuit
radar
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6625087A
Other languages
Japanese (ja)
Inventor
Toshiki Ono
俊樹 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6625087A priority Critical patent/JPS63233390A/en
Publication of JPS63233390A publication Critical patent/JPS63233390A/en
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To apply a frequency-modulation to a jamming signal only in a condition wherein the time delay of the jamming signal is larger than the range gate of a radar by adding a circuit for judging the execution or the stopping of the frequency modulation in accordance with the time delay of the jamming signal. CONSTITUTION:A delay time control circuit 3 obtains a delay time to be given to an input pulse signal and feeds signals to a delay circuit 2 and a frequency modulation execution judging circuit 7. The delay circuit 2 feeds a delay signal with the time delay to a path changeover switch 6 in response to the pulse signal inputted from a received signal input terminal 1. On the other hand, the judging circuit 7 outputs a signal (a) to the switch 6 when the delay time to be given to the input signal is larger than the range gate of a radar and otherwise outputs a signal (b). The switch 6 feeds the delay signal to an amplitude modulating circuit 4 in case of the signal (a) or to a jamming signal output terminal 5 in case of the signal (b). The modulation circuit 4 applies a prescribed amplitude modulation to the delay signal in case of the signal (a) and outputs the modulated delay signal to the output terminal 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、レーダ等の電波発射源に対して妨害電波を
送信するレーダ妨害装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radar jamming device that transmits jamming waves to a radio wave emission source such as a radar.

〔従来の技術〕[Conventional technology]

第2図は従来のレーダ妨害装置を示す構成図であり、図
において、Illは受信信号入力端子、(21は入力し
た受信信号に対して所足の時間遅延を施す遅延回路、(
31はこの遅延回路(2)へ遅延時間を指示する4延時
間制御回路、141は遅延回路(!1が出力した遅延信
号に対して眼幅変調を行う振幅変調回路、;11)は妨
害信号出力端子である。
FIG. 2 is a configuration diagram showing a conventional radar jamming device. In the figure, Ill is a received signal input terminal, (21 is a delay circuit that applies a sufficient time delay to the input received signal, (
31 is a delay time control circuit 4 that instructs the delay time to this delay circuit (2), 141 is a delay circuit (an amplitude modulation circuit that performs interpupillary width modulation on the delayed signal outputted by !1, ; 11) is an interference signal It is an output terminal.

次に動作について説明する。Next, the operation will be explained.

今、第3図に示すパルス信号列が受信信号入力端子田に
入力する場合を考える。遅延時間制御回路(31は該当
時刻における入カバルス信号に与えるべき遅延時間(d
t )  を求めて、遅延回路121へ送出する。第4
図に遅延時間の時611変化例を示す。遅延回路(21
は、受信信号入力端子Ill f!:経て入力したパル
ス信号に対してdtの時間遅延を持つ遅延信号を振幅変
調回路(41へ送出する。
Now, consider the case where the pulse signal train shown in FIG. 3 is input to the received signal input terminal. The delay time control circuit (31 is the delay time (d) to be given to the incoming signal at the relevant time
t) and sends it to the delay circuit 121. Fourth
The figure shows an example of time 611 change in delay time. Delay circuit (21
is the received signal input terminal Ill f! : A delayed signal having a time delay of dt with respect to the input pulse signal is sent to the amplitude modulation circuit (41).

振幅変調回路(41は遅延信号に対して振幅変調を行っ
た後、妨害信号出力端子+51へ送出する。
The amplitude modulation circuit (41 performs amplitude modulation on the delayed signal and then sends it to the interference signal output terminal +51).

上記動作をパルス信号入力の度に行うことKより、妨害
の対象であるレーダ側へはレーダ・エコー信号と妨害信
号の両方が入力することになる。第5図にレーダ側入力
信号例を示す。第5図において+alは、妨害信号の時
間遅延がレーダの距離ゲートより小さい場合?示してお
り。
Since the above operation is performed every time a pulse signal is input, both the radar echo signal and the interference signal are input to the radar, which is the object of interference. FIG. 5 shows an example of the radar side input signal. In Figure 5, +al is when the time delay of the jamming signal is smaller than the radar range gate? It shows.

第4図のAの範囲に対応するものである。l!Iの状態
においてに、レーダのホ離ゲート内にレーダ・エコー信
号と妨害信号の両方が入っており、通常のレーダは距離
ゲート内の耕幅が大きな信号に追尾するのが一般的であ
る為、レーダを妨害信号K jA尾させるには常に妨害
信号の振幅全レーダ・エコー信号の振幅より大きくして
おく必要がある。レーダが妨害信号に追尾した後。
This corresponds to the range A in FIG. l! In state I, both the radar echo signal and the interference signal are present within the distance gate of the radar, and a normal radar generally tracks the signal with a large range within the distance gate. , in order to cause the radar to follow the jamming signal K jA, the amplitude of the jamming signal must always be greater than the amplitude of the total radar echo signal. After the radar tracks the jamming signal.

第4図のBの矢印の如く、遅延時間を途々に大きくして
いくことにより、第5図のIb+のようにレーダの距離
ゲートはレーダ・エコー信号の後方に移動していくこと
になる。第5図VCおいて(0)ハ妨害信号の時間遅延
がレーダの距離ゲートより大きい場合を示しており、第
4図のCの範囲に対応するものである。l(1は状態に
おいて汀、レーダの距離ゲート内には妨害信号のみが存
在するため、妨害信号VC振幅変調を施すことによりレ
ーダに妨害効果を与えることが可能となる。
By gradually increasing the delay time as shown by the arrow B in Figure 4, the radar distance gate will move to the rear of the radar echo signal as shown in Ib+ in Figure 5. . In VC of FIG. 5, (0) C indicates a case where the time delay of the interference signal is larger than the distance gate of the radar, and corresponds to the range C of FIG. 4. Since only the interference signal exists within the range gate of the radar, it is possible to give a interference effect to the radar by applying amplitude modulation to the interference signal VC.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のレーダ妨害装置は妨害信号の時間遅延がレーダの
距離ゲートより小さい場合においても妨害信号に振幅変
fAを行ってしまう為、レーダの距離ゲートをレーダ・
エコー信号から引き離すことが困難であり、妨害効果ケ
与えるに至らないという問題点があった。
Conventional radar jamming devices change the amplitude fA of the jamming signal even when the time delay of the jamming signal is smaller than the radar distance gate.
There was a problem in that it was difficult to separate it from the echo signal, and it did not produce any interference effect.

この発明は上記のような問題点を解消するためになされ
たもので、妨害信号の時間遅延がレーダの希薄ゲートよ
り大きい状態でのみ妨害信号に対する振幅変調を行うよ
うなレーダ妨害装at得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and aims to provide a radar jamming device that performs amplitude modulation on a jamming signal only when the time delay of the jamming signal is larger than the sparsity gate of the radar. purpose.

〔問題点t−解決するための手段〕[Problem t-Means for solving]

この発明に係るレーダ妨害装置は、従来のレーダ妨害装
置に対して、妨害信号の時間遅延に応じて振幅変調の実
行・停止を判定する回路?付加したものでああ。
The radar jamming device according to the present invention differs from the conventional radar jamming device in that it has a circuit that determines whether to perform or stop amplitude modulation according to the time delay of the jamming signal. That's what I added.

〔作用〕[Effect]

この発明における振幅変調実施判定回路は、受信信号に
与え72:時間遅延を遅延時間制御回路から入力し1時
間遅延がレーダの距離ゲートより大きい場合にのみ遅延
信号が振幅変調回路に入力するように制御する。
The amplitude modulation execution determination circuit in the present invention inputs a time delay 72 to the received signal from the delay time control circuit, and inputs the delayed signal to the amplitude modulation circuit only when the one-hour delay is larger than the distance gate of the radar. Control.

〔発明の実施例〕[Embodiments of the invention]

以下・この発明の一実施例2図について説明する。第1
図において、…は受信信号入力端子、(21けこの受信
信号入力端子11)から入力した受信信号に対し所定の
時間遅延を持つ遅延信号を出力でる遅延回路、(,3;
ばこの遅延回路121の遅延時間をili++御する遅
延時間′MI御回路、(61は上記遅延回路(21が出
力した遅延信号の伝送経路を切換える経路切換スイッチ
、儀71け遅延時間に心じて経路切換スイッチ(61へ
切換信号を送出する振幅変調実施判定回路、・41は経
路切換スイッチを経て入力した遅延信号に対して振幅変
調を権す振幅変調回路、+61は妨害信号を出力する妨
害信号出力端子である。
Hereinafter, FIG. 2 will be described as an embodiment of the present invention. 1st
In the figure, ... is a received signal input terminal, and a delay circuit (,3;
A delay time 'MI control circuit for controlling the delay time of the tobacco delay circuit 121 (61 is a path changeover switch for switching the transmission path of the delayed signal outputted by the delay circuit (21); Route changeover switch (amplitude modulation execution determination circuit that sends a switching signal to 61; 41 is an amplitude modulation circuit that performs amplitude modulation on the delayed signal input via the route changeover switch; +61 is an interference signal that outputs an interference signal) It is an output terminal.

次に動作について説明する。Next, the operation will be explained.

今、第3図に示すパルス信号列が受信信号入力端子II
+に入力する場合を考える。遅延時間制−回路131は
該当時刻における入力パルス信号に与えるべき遅延時間
(6t>を求めて、遅延回路12)および振幅変調実施
判定回路(7)へ送出する。
Now, the pulse signal train shown in FIG. 3 is connected to the received signal input terminal II.
Consider the case of inputting to +. The delay time system circuit 131 determines the delay time (6t>) to be given to the input pulse signal at the relevant time and sends it to the delay circuit 12 and the amplitude modulation implementation determination circuit (7).

第4図に遅延時間の時刻変化例を示す。FIG. 4 shows an example of how the delay time changes over time.

遅延回路121は、受信信号入力端子+11 ’i経て
入力したパルス信号に対してatの時間遅延を持つ遅延
信号を経路切換スイッチ(81へ送出する。一方、振幅
変調実施判定回路(7)は、atがレーダの距離ゲート
より大きい(第4図のAの範囲)場合VCは経路切換ス
イッチ16)へ1a1信号を送出し、そうでない場合に
はlb°信号を送出する。
The delay circuit 121 sends a delayed signal having a time delay of at to the pulse signal inputted through the received signal input terminal +11'i to the path changeover switch (81).On the other hand, the amplitude modulation implementation determination circuit (7) If at is larger than the distance gate of the radar (range A in FIG. 4), the VC sends a 1a1 signal to the path changeover switch 16), otherwise it sends an lb° signal.

経路切換スイッチ(61は、1a1信号の場合には遅延
信号を振幅変調回路141へ送出し、+ 1.、 l信
号の場合には遅延信号を妨害信号出力端子151へ送出
する。振幅変調回路141は遅延信号に対して所定の振
幅変調を施した後、妨害信号出力端子・5)へ送出する
The path changeover switch (61 sends out the delayed signal to the amplitude modulation circuit 141 in the case of the 1a1 signal, and sends out the delayed signal to the interference signal output terminal 151 in the case of the +1., l signal.Amplitude modulation circuit 141 After subjecting the delayed signal to a predetermined amplitude modulation, it is sent to the interference signal output terminal 5).

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば受信信号に対する妨害
信号の時間遅延がレーダの距離ゲートより大きい場合に
のみ妨害信号に振幅変t4に施fように構成したので、
レーダの距離ゲート内で妨害信号の振幅変調を行うこと
がなくなりレーダが妨害信号に追尾する(レーダに妨害
がかかる)6(g率が高くなるとAう効果がある。
As described above, according to the present invention, the amplitude change t4 is applied to the jamming signal only when the time delay of the jamming signal with respect to the received signal is larger than the distance gate of the radar.
Amplitude modulation of the interference signal is no longer performed within the range gate of the radar, and the radar tracks the interference signal (interference occurs on the radar).6 (The higher the g rate, the more effective it is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるレーダ妨害装置の構
成図、−2図は従来のレーダ妨害装置の構成図、名3図
は入力パルス信号列、第4図は遅延時間の時刻変化例、
1第5図はレーダ側入力信号状況例である。 1′AVCおいて、山は受信信号入力端子、(21は遅
延回路、131け遅延時間制御回路、141は振幅変調
回路、(6)は妨害信号出力端子、(8)は経路切換ス
イッチ、(7)は眼幅変調実施判定回路である。 なお、図中、同一符号は同一、又は泪当部分を示す。
Fig. 1 is a block diagram of a radar jamming device according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional radar jamming device, Fig. 3 is an input pulse signal train, and Fig. 4 is an example of time variation of delay time. ,
1. FIG. 5 is an example of the input signal situation on the radar side. In 1'AVC, the peaks are the received signal input terminals, (21 is the delay circuit, 131-digit delay time control circuit, 141 is the amplitude modulation circuit, (6) is the interference signal output terminal, (8) is the path changeover switch, ( 7) is an interpupillary distance modulation execution determination circuit. In the drawings, the same reference numerals indicate the same or the contact portions.

Claims (1)

【特許請求の範囲】[Claims] 受信信号に対して適当な時間遅延の後に振幅変調を施し
た妨害信号を送信するものにおいて、妨害信号の時間遅
延に応じて振幅変調の実行・停止を制御する回路を設け
たことを特徴とするレーダ妨害装置。
A device that transmits a disturbance signal subjected to amplitude modulation after an appropriate time delay with respect to a received signal, characterized by being provided with a circuit that controls execution/stop of amplitude modulation according to the time delay of the disturbance signal. Radar jammer.
JP6625087A 1987-03-20 1987-03-20 Radar jamming instrument Pending JPS63233390A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6625087A JPS63233390A (en) 1987-03-20 1987-03-20 Radar jamming instrument

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6625087A JPS63233390A (en) 1987-03-20 1987-03-20 Radar jamming instrument

Publications (1)

Publication Number Publication Date
JPS63233390A true JPS63233390A (en) 1988-09-29

Family

ID=13310429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6625087A Pending JPS63233390A (en) 1987-03-20 1987-03-20 Radar jamming instrument

Country Status (1)

Country Link
JP (1) JPS63233390A (en)

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