JPS63232520A - Load driving circuit - Google Patents

Abstract

PURPOSE:To improve the effect of the charge and the discharge of a load capacity by a PNP transistor by making the amplitude of a signal impressed on the base of the PNP transistor for active pull-down larger than the amplitude of the signal impressed on the base of an NPN emitter follower transistor. CONSTITUTION:The transistors 11 and 12, a constant-current source 13 and resistances 14-17 constitutes a current switch and the resistance 17, the transistors 18 and 19 and the resistance 22 constitutes a level shift circuit. By making the amplitude of the signal inputted in the base of the PNP transistor 21 for the active pull-down larger than the amplitude of the signal inputted in the base of the NPN emitter follower transistor 20, the velocity that the current of the transistor decreases is accelerated when the output VOUT rises and the veloiity that the current increases is accelerated when the output VOUT breaks. Thus, the effect of the charge and discharge of the load capacity 23 by the PNP transistor can be raised and a switching velocity can be made higher.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to high-speed logic circuits, and particularly to a load drive circuit suitable for driving a load.

[Conventional technology]

In conventional high-speed logic circuits, for example, an emitter-coupled logic circuit (ECL) as shown in FIG. 9 is used, and in particular, an emitter follower circuit composed of a transistor 20 and a resistor 93 is used for driving a load. This circuit is described as a conventional example in, for example, Japanese Utility Model Application No. 56-92909 filed by the present inventors. Furthermore, as an improvement over this, an ECL circuit with an active pull-down circuit as shown in Fig. 10 in which the resistor 93 of the emitter follower shown in Fig. 9 is replaced with a transistor is described in JP-A-61-269523. .

In the circuit of FIG. 10, when the output Vout rises, the output 24 of the level shift circuit 101 rises, and the current of the transistor 21 decreases. Therefore, the current of the transistor 20 is effectively used to charge the load capacitance 23,
Speed up charging time. Switching times are therefore reduced. On the other hand, when the output VOUT falls, the output 24 of the level shift circuit 101 falls, and the transistor 21
The current increases. Therefore, this increased current is used to discharge the load capacitance 23, speeding up the discharge time.

Therefore, the switching time is also reduced at the time of falling.

[Problem that the invention seeks to solve]

The conventional technique shown in FIG. 10 can exhibit the above-mentioned effect when the load capacitance 23 is relatively large, but when the load capacitance 23 is relatively small, the transistor 21 and the level shift circuit 101 become a load. Therefore, the circuit is slower than the circuit shown in FIG. The reason for this is as follows.

Since there is a time delay in the level shift circuit 101, the former is faster in principle between the base input signal of the transistor 20 and the base input signal of the transistor 21.

Furthermore, the NPN transistor 20 normally has better performance and faster response than the PNP transistor 21.

Further, when the load capacitances 23 are small, most of the current of the transistor 20 flows to the transistor 21 even in a transient state. Therefore, when the output Vou rises, the rate at which the current in the transistor 20 increases is faster than the rate at which the current in the transistor 21 decreases, and as a result, the transistor 21 cannot exhibit the above-mentioned effect. On the other hand, when the output V0IJT falls, it is the opposite of the above case, and the transistor 20
The speed at which the current in transistor 21 decreases is faster than the speed at which the current in transistor 21 increases, so as with the rise,
Therefore, the discharge effect of the transistor 21 cannot be sufficiently exerted.

The present invention solves the above problems and provides an emitter follower circuit with an active pull-down circuit.
It is an object of the present invention to provide a circuit configuration for enhancing the charging/discharging effect of load capacitance by an NP transistor.

[Means for solving problems]

The above objective is to reduce the amplitude of the signal input to the base of the NPN emitter follower transistor.

This is achieved by increasing the amplitude of the signal input to the base of the PNP transistor for active pull-down, and making the PNP transistor more powerfully drive the load.

[Effect]

By increasing the signal amplitude of the base input of the PNPh transistor, when the output VOIJT rises, the speed at which the current of the above transistor decreases becomes faster, and when the output VOUT falls, the current increases. increase the speed at which Therefore, it is possible to compensate for the delay in the level shift circuit that creates the base input of the PNP transistor, and the fact that the performance of the PNP transistor is inferior to that of the NPN transistor, and to powerfully charge and discharge the load capacitance using the PNP transistor. can.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Transistor 11. ．． 12. Constant current source 13, resistors 14, 15
, 16 and 17 constitute a current switch. When the input voltage Vrs is lower than the reference voltage VBa, VOUT becomes a logical low level (referred to as an L level), and when it is higher, it becomes a logical high level (referred to as an H level). transistor 20
is for an emitter follower, and has the same function as the transistor 20 in FIGS. 9 and 10 of the conventional example. resistance 17,
Transistors 18, 19. The resistor 22 constitutes a level shift circuit. The PNP transistor 21 is for active pull-down.

First, we will explain how the DC potential and current are determined. It is assumed that the base-emitter voltages of transistors 18, 19, 20, and 21 are approximately the same and are expressed as VBE. Also, the base current is ignored. Let the current of the constant current source 13 be Ics, and the values of the resistor 16.17 be Rct and Rc2, respectively. The H level and L level of the output voltage VOIJT are set to VO, respectively.
If UT (H)eVout (L), then VQLIT DI) = -Va11! VOUT (L)=-Ics' Rat-ViB. Therefore, the amplitude of VOUT (A) = I
cs・Ra1. Similarly, the amplitude VLA of the base input of the transistor 20 is Ic5-Rcz. Also, P
The amplitude v2^ of the base power 24 of the NP transistor 21 is.

Vz^=VaH-VIZL Here, V2H and V2L are the H level and L level of the base input signal of the transistor 21, respectively.

Vzo= -2VIE Vzt, =-IcsIl(Rct+Rcz) -2VB
E! Therefore, Vz^=Ica' (Rci+Rcz).

In other words, ■1^ and Vz^ have a difference in amplitude by IQB''RC2, and the latter is larger. ゛Also, regarding the current, ILS is the current flowing through transistors 18 and 19, and ILS is the current flowing through transistors 20 and 21. Iap, and when the output voltage Voυ↑ is H level (H
), and distinguishing by (L) at L level, I M5 (H) = I EF (H) = (I V DTI
-2VBFri/RLIt, 5(L)=(1・Vdingding1 -2Vag-Ic5- (Rct+Rcz))/R
c.

Here, RL is the value of the resistor 22.

IEP (L) is transistor 18, 19 No Vag
It is determined by the difference between VBH and VBH of transistors 20 and 21.

If the former is VaEt and the latter is VaEt, then 2 Va
I! t:2 Vagx+ I as llRaw here.

Considering that, becomes.

In other words, to summarize the current, when the output is H level, ILS and IEP are the same, and when the output is L level, Ip
p can flow several times I+, s, which is a resistance of 17
(Rcz).

Next, the switching operation will be explained.

Attention is paid to the base input Vt of the NPN transistor 20 and the base input voltage 24 (Vz) of the PNP transistor 21. When the output VOUT falls, Vz changes from Ov to -Ics-R
cz, but on the other hand, Vz falls from -2VBE to -
2Vaa - I as (Rcz+ Rat). There is a difference in amplitude of C3-RC2.

Therefore, level shifting transistors 18 and 19
By increasing the value of Ics·Raw according to the delay time in , it is possible to make the falling speed of Vz the same or faster than the falling speed of Vz. On the contrary, I as
When there is no difference in the amplitude of -Rat, it is inevitable that the falling speed of 2 is slower than that of Vz due to the delay in the level shift transistors 18 and 19.

If the falling speed of vz is fast, the current of the NPN transistor 20 stops flowing (cutoff) and P
The current in NP transistor 21 increases and therefore N
Since the transistor 20 (PN) is not cut off, the load capacitance 23 can be strongly and quickly discharged by both the transistors 20 and 21, and the switching time for the fall of VOUT can be reduced. v
When the falling speed of z is slow, the NPN transistor 20
After reaching a state close to cut-off, the current of the PNP transistor 21 increases, and eventually the transistor 21
Since the load capacitor 23 is discharged only by this, the switching time for the fall of VOUT becomes long.

On the other hand, when the output V OUT rises, the rise speed of Vz is fast, so the current of the NPN transistor 20 decreases faster than the current of the NPN transistor 20 increases, so the current of the NPN transistor 20 decreases more efficiently. It is often used to charge the load capacitor 23, and can reduce the switching time for the rise of VOUT.

In FIG. 2, the NPN transistor 19 in FIG. 1 is replaced with a PNP transistor 25. In FIG. 3, the NPN transistor 19 in FIG. 1 is replaced with a diode 31.

Both perform the same operation as the circuit shown in FIG.

In Figure 4, the resistor 22 in Figure 1 is replaced with a constant current source circuit consisting of a transistor 41 and a resistor 42, and compared with the circuit in Figure 1, IL3 (H) and LLS (L) are the same. The operation is the same, except that

Although not shown, the resistor 22 in FIGS. 2 and 3
It is clear that the main current source circuit can also be constructed as shown in FIG.

In Fig. 5, the transistor 19 in Fig. 1 is replaced with a resistor 51, and when I VTT l is sufficiently large, Is almost changes when Voυ is at the H level and when it is at the L level. Therefore, the voltage drop due to the resistor 51 is almost constant, and it functions almost the same as a diode, etc.
It is clear from this figure that the resistor 52 can also be constructed with a constant current source circuit as shown in FIG.

FIG. 6 shows the collector of transistor 19 and the emitters 2. in the circuit of FIG. During the evening, a capacitance [61 is added, transistors 18, 19, resistors 17, 22
This is effective in reducing the delay of the level shift circuit composed of. It is clear that this capacitor 61 can be added in the same way in all the circuit configurations described so far, and the same effect can be obtained.

Furthermore, the same effect as described above can be obtained even if the capacitor 61 is added between the base of the PNP transistor 21 and the base of the transistor 18 or between the base of the transistor 21 and the base of the transistor 20. Furthermore, it is clear that these methods of addition may be applied to all the circuit configurations described above.

In the above circuit configuration, all input transistors are 11
Although I have only considered this, it is possible to create a multi-input gate by connecting the collector and emitter of several other NPN transistors to the collector and emitter of transistor 11, respectively.In addition, in a circuit configuration of 5 or more, all V
Although only OR output is considered as OUT, it is clear that NOR output can also be obtained with a completely similar circuit configuration.

FIG. 7 shows another embodiment of the present invention. The current switch in FIG. 1 is replaced by an inverter circuit composed of a transistor 71, resistors 14, 15, 72, and a capacitor 73 in this figure. When +Vxs is at H level, current flows through transistor 71 and L level is applied to the bases of transistors 2o and 18. Vr
The opposite is true when N is at L level. Capacitor 73 is provided to speed up the response of the inverter.

Therefore, the operation of the emitter follower circuit composed of transistors 18, 19, 20° 21 and resistor 22 is as follows.
This is exactly the same as the case shown in the figure, and the same effects of the present invention can be expected.

Also, except that this circuit uses only NOR logic and cannot take OR logic, the configuration of . It is quite obvious that variations of the diagram are possible.

FIG. 8 shows still another embodiment of the present invention. The configuration of this figure based on FIG. 1 is also possible for all the above-mentioned variants. In this embodiment, the emitters of transistors 18 and 18' and the emitters of transistors 20 and 20' are connected, respectively, to realize a connected OR logic. One set of transistors 19, 21 and resistor 22 is sufficient. As a result, logically Vout = Vxs + V
r+v' (7) output is obtained, and the above-mentioned effect can be obtained as a switching characteristic.

〔Effect of the invention〕

As described above, according to the present invention, in an emitter follower circuit with an active pull-down circuit, it is possible to enhance the charge/discharge effect of the load capacitance by the PNP transistor for active pull-down, and increase the switching speed.

[Brief explanation of drawings]

1 to 6 are circuit diagrams of one embodiment of the present invention, FIG. 7 is a circuit diagram of another embodiment, FIG. 8 is a circuit diagram of still another embodiment, and FIGS. 9 and 10. The figure is a conventional circuit diagram. V I N , V r N '...Input voltage, V
OUT...Output voltage, 21...PNP for pull-down
Transistor, 17... Resistor for amplitude expansion, 23...
・Load capacity, 101...Rebehato l [! 1'@21! ] 3rd place 1st trial 3rd concave 4th concave 51st! 6th concave■EIl-V'mouth.

Claims (1)

[Claims] 1. An NPN emitter follower transistor that receives an input signal from its base and obtains an output signal from its emitter;
PN whose emitter is connected to the emitter of the transistor
An emitter follower circuit with an active pull-down circuit consisting of a P-type transistor, characterized in that the amplitude of the signal applied to the base of the PNP-type transistor is larger than the amplitude of the signal applied to the base of the NPN-type transistor. load drive circuit. 2. In a logic circuit in which the voltage drop due to the current flowing through a load resistor determines the signal amplitude, the first signal and the second signal are obtained by different values of the load resistor, and the first signal with the smaller amplitude is used as the above signal. 2. The load drive circuit according to claim 1, wherein the load drive circuit is configured to apply the signal to the base of the NPN transistor, and apply a second signal having a large amplitude to the base of the PNP transistor via a level shift circuit.