JPS63232515A - Identification circuit for ternary level signal - Google Patents

Abstract

PURPOSE:To attain the compatibility of the simple constitution of a circuit and the accurate identification of pulses by utilizing an output from a comparator so as to control a threshold. CONSTITUTION:At first, a constant-voltage VB is adjusted in +VTH which is higher than the zero level of inputted ternary level signal. When the ternary level signal S is inputted in an input 11 and crosses with the threshold VTH, the non-inversion output 13 of the comparator 2 outputs the one of binary level signals at the first transition of the input signals S. Meanwhile, since an inversion output 14 outputs the zero level, the voltage is composed with Vb to alter the threshold to -VTH, which is supplied to an input 12. When the input ternary signal S rises, the non-inversion output 13 of the comparator 2 outputs the zero of the binary level signal and the voltage equal to one level occurs in the inversion output 14, then the threshold voltage alters to +VTH. Thus, a ternary/binary conversion circuit having little distortion of pulse width can be obtained in the extremely simple constitution of the circuit.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD OF THE INVENTION The present invention relates to a ternary level signal identification circuit. More specifically, the input ternary level signal is identified and the two
This invention relates to a new configuration of a circuit that outputs a value level signal. BACKGROUND OF THE INVENTION FIGS. 3(a) to 3(d) are diagrams for explaining the ternary level signal identifying operation of a conventional ternary level signal identifying circuit. That is, the signal waveform shown in FIG. 3(a) is a three-level signal input to the circuit, and when there is no signal, it maintains the half-value level of the signal amplitude (midpoint 20), and when there is a signal, it maintains a two-level signal. This is a signal S indicating an amplitude corresponding to the level (+1.-1). The signal waveform shown in Fig. 3 et al.) is the threshold VT) shown in the figure.
This is the output signal waveform A when this signal S is binarized by ``.In addition, the signal waveform shown in FIG. 3(C) is the output signal waveform A when this signal S is binarized by This is the output signal waveform B when Can be done. Converting such a ternary level signal to a binary level signal is performed by the fourth
This can be easily realized by a circuit as shown in the figure. That is, as shown in FIG. 4, by inputting a predetermined threshold value VTH'' or VTll- to one input of the comparator 1 and inputting the input signal S to the other input, the input signal S is set to the threshold value. A binary signal whose state changes every time it crosses a level is output. Such a conventional three-value level signal identification circuit has a simple configuration, and since the threshold value is deviated from the half-value level,
When there is no signal, the signal level and threshold will not cross,
It can be said that this circuit configuration does not cause identification errors. However, as can be easily seen by comparing the signal waveforms shown in FIGS. 3(b) and 3(c), there is a problem in that the pulse width of the output A or B is distorted compared to the original signal S.
゛Therefore, in order to correct this pulse width distortion, as shown in FIG. lb, and further, these comparators 1
A circuit has been proposed that can obtain an output signal C whose pulse width distortion has been corrected as shown in FIG. 3 (6) by inputting output signals A and B of a and lb to an SR flip-flop. . However, this circuit has a complicated structure and is significantly disadvantageous in terms of manufacturing cost and operating speed. The problem to be solved by the invention is that conventional three-level level discrimination circuits with a simple structure cannot avoid pulse width distortion of the output signal, while a circuit with a pulse width distortion correction function , the structure was complicated and expensive. Therefore, the present invention solves the problems of these conventional techniques, and
The object of the present invention is to provide a novel circuit that has both a simple circuit configuration and accurate pulse identification. Means for solving the problem, that is, according to the present invention, a ternary level signal that maintains 0 level when there is no signal and reaches a predetermined (+1.-1) level when there is a signal is changed to the (+1.-1) level. Corresponding <1. O
) It is a circuit that identifies a binary level signal that takes a level, and initially maintains a predetermined voltage different from the θ level of the input ternary signal, and when the input ternary signal rises, the input ternary level signal The voltage level changes from a high voltage level to a low voltage level with respect to the 0 level of the input ternary level signal, and when the input ternary level signal falls, the voltage level changes from a low voltage level to a high voltage level with respect to the 0 level of the input ternary level signal. a threshold value generation circuit that generates a threshold value, and a comparator that compares a threshold discharge force ternary level signal generated by the threshold value generation circuit;
A ternary level signal discrimination circuit is provided. Effect When a predetermined threshold value is set to identify a ternary level signal, in order to perform the identification without pulse width distortion, the threshold value may be set to the half value level of the signal amplitude. however,
In this case, the signal level and the threshold value become the same value when there is no signal, resulting in an identification error. Therefore, it is desirable to operate so that the threshold value avoids the signal half-value level, and furthermore, it is necessary to operate in a manner that does not cause pulse width distortion as described above. The present invention was completed as a result of various studies on circuits that realize the above-described operation while taking care not to complicate the circuit configuration. In the ternary signal identification circuit according to the present invention, the threshold values for comparison with the input ternary level signal are a level higher than the amplitude center level of the input ternary signal and a level higher than the amplitude center level of the input ternary signal. Varies between low levels. That is, when the human input signal rises, the input signal value is compared with the threshold value which is higher than the amplitude center level of the input ternary signal.
] is identified, and when the input signal falls, it is compared with a threshold value at a level lower than the amplitude center level of the input ternary signal to identify [-1] of the input signal. This kind of operation is based on the same idea as the conventional technology mentioned above (shown in Figure 5).
However, in the prior art, this has been done using two comparators that refer to different threshold values. The ternary level signal discrimination device according to the present invention uses one comparator and controls the threshold value using the output of the comparator. That is, when identifying an input ternary level signal, for example, if the rising edge of the signal is first identified, the next operation to be identified is the falling edge of the signal. Therefore, it is possible to control the threshold value using a certain algorithm according to the binary signal output by the comparator. Although this kind of control will be specifically described later, it can be realized by an extremely simple circuit by using the inverted output (or a signal obtained by inverting the output) of the comparator. EXAMPLES The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one example of the present invention and does not limit the technical scope of the present invention in any way. . FIGS. 1(a) and 1(b) show configurations of different embodiments of a three-level signal discrimination circuit constructed according to the present invention. First, the circuit shown in FIG. 1(a) will be explained. This circuit mainly consists of a comparator 2 having a pair of input terminals 11.12 and a pair of output terminals 13.14. . An input 11 receives a ternary signal to be identified by this circuit, and the other input 12 receives a threshold value to be described later. Further, a binary signal generated by the operation of this circuit is output from the output 13, and an output 14, which is an inverted output of the output 13, is fed back to the human power 12 via a resistor R2. Figures 2 (a) and (c) are signal waveform diagrams for explaining the above-mentioned operation, and the output binary level signal obtained by comparing the human input signal waveform and threshold voltage fluctuations. The waveforms are respectively represented. The threshold value in this circuit is generated by dividing a predetermined constant voltage Ve supplied from the outside and an inverted output voltage supplied from the output 14 using resistors R2 and R2. The constant voltage Ve is adjusted to a value different from the amplitude center level of the input ternary level signal, that is, the 00 level of the ternary level signal. In this example, we will use Fig. 2 (
As shown in a), initially +V Ding H higher than 0 level
has been adjusted. When a ternary level signal is input and crosses the threshold VTII, the non-inverting output 13 of the comparator 2 raises an identification pulse with a delay of Δt1 from the true rising edge of the input signal, and the binary level signal [1] Output. Meanwhile, at the same time, the inverted output 14 of the comparator 20 is

Since the [0] level is output, this voltage is combined with Ve, and the threshold value changes to -V'rH. Next, when the input ternary signal falls and crosses this threshold value -VTR, the non-inverting output 13 of the comparator 2 causes the identification pulse to fall with a delay of Δt2 from the true falling edge of the input signal, and the binary level signal is of

Output [0]. At the same time, a voltage corresponding to the [1] level is generated at the inverted output, and the threshold voltage changes to +VTR. Therefore, if the delay Δt at the rise and the delay Δt2 at the fall are equal, no pulse width distortion occurs. Now, the inverted output voltage of comparator 2 is V. and set the threshold voltage to V
The THN threshold input terminal □ has a constant voltage ■ via the resistor R1. and ■ via resistor R2. It is assumed that the following is applied. At this time, these relationships can be expressed by the following formula. Here, specifically, when the output voltage of comparator 2 is "1" -
0,8■, when it is “0” it is -1,8■, and the value of the resistance is R
I=IKΩ, R2=50Ω, and Vtn=26
6 in mV. ! :, t6° input ternary level signal S is G
ND (=OV) is the no-signal level, and C+ with an amplitude of 30 mV (peak-to-peak) or more around this level
1. -1], the input signal voltage S is the threshold value V
When it becomes higher than TH, Vo is "L" = -1.8V
According to equation (1), vTH=10 mV, and it can be seen that the threshold value changes below the signal half-value level [0■]. Also, if the input signal S becomes lower than the threshold value VTR, ■. is "H" = -0.8V, and ■7□ζ+1
The voltage becomes 0 mV, and changes symmetrically around the GND voltage of 0. Incidentally, as is clear from these explanations, the comparator 2,
The ternary level signal input terminal 11 may be in phase with the binary level signal output terminal 13 and at the same time be in opposite phase with the output 13 connected to the threshold terminal 12. Therefore, as shown in Fig. 1 et al., the entire structure may be connected in reverse phase. That is, in the circuit of FIG. 1(b), the input ternary level signal is sent to the inverted input 11a, and the output binary level signal is sent to the inverted output 13.
a, respectively, and a threshold generation circuit is formed between the non-inverting input 12a and the non-inverting output 14a. Effects of the Invention As detailed above, according to the present invention, a ternary/binary conversion circuit with less pulse width distortion can be realized with an extremely simple circuit configuration. In addition, in a circuit with such a configuration, the threshold value for waveform shaping is not affected by the signal amplitude (power) of the input signal, and furthermore, if the denity ratio of the human input signal is 50%, burst There is no fluctuation in the DC component of the signal even when the signal is manually operated. Therefore, the circuit operation can be used as an AC coupled receiver whose circuit operation is not easily affected by DC voltage fluctuations such as temperature fluctuations. By utilizing these characteristics, it can be advantageously used as an optical receiver even in the field of optical communications where the dynamic range of signals varies greatly.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(a) are diagrams showing a specific configuration example of a ternary level signal identification circuit according to the present invention, and FIG.
a) and (b) are signal waveform diagrams illustrating the operation of the circuit shown in FIG. 1(a), and FIG. 3 is a signal waveform diagram illustrating the operation of the conventional three-level signal identification circuit. FIG. 4 is a diagram illustrating the configuration of a conventional ternary level signal identification circuit, and FIG. 5 is a diagram illustrating another configuration of the conventional ternary level signal identification circuit. [Main reference numbers] 1, la, lb, 2 --- comparator, 2... flip-flop, 11, lla... ternary level signal input, 12.1
2a...threshold input,

Claims (3)

[Claims] (1) A ternary level signal that maintains 0 level when there is no signal and takes a predetermined (+1, -1) level when there is a signal, as described above (
This circuit identifies the signal as a binary level signal that takes the (1, 0) level corresponding to the +1, -1) level, and initially maintains a predetermined voltage different from the 0 level of the input ternary signal. When a signal rises, the voltage level changes from a high voltage level to a low voltage level with respect to the 0 level of the input ternary level signal, and when the input ternary signal falls, the voltage level changes from a high voltage level to a low voltage level with respect to the 0 level of the input ternary level signal. A threshold generation circuit that generates a threshold that changes from a low voltage level to a high voltage level with respect to the voltage level, and a comparator that compares the threshold generated by the threshold generation circuit and an input ternary level signal. Features a 3-value level signal identification circuit. (2) The threshold generation circuit divides the inverted output of the comparator and a predetermined voltage different from the 0 level of the input ternary level signal, thereby generating voltages at levels higher and lower than the amplitude center level. 2. The ternary level signal identification circuit according to claim 1, wherein the ternary level signal identification circuit is a voltage dividing circuit that generates . (3) The threshold generated by the threshold generation circuit is
3. The three-value level signal discrimination circuit according to claim 1, wherein the three-value level signal discriminating circuit changes symmetrically with the zero level of the value level signal as an amplitude center level.