JPS63232514A - Binary/ternary level signal conversion circuit - Google Patents

Abstract

PURPOSE:To obtain an output signal waveform having small distortion of pulse width without receiving the effect of the variation of DC voltage caused by the variation of temperature, etc., by using a high pass filter(HPF) so as to AC-combinine a circuit. CONSTITUTION:The titled circuit is constituted of the HPF 1 connected to an input, a signal state detection circuit 2 connected in parallel with the HPF 1 and HPF 3 as an impulse signal generation circuit and buffers 4 and 5 are respectively provided on the output sides of the HPFs 1 and 3 in order that two signal paths do not form feedback. An inputted binary burst signal is AC- combined by the HPF 1 and added with the impulse signal generated in the impulse generation circuit 3 from the gate signal obtained from the signal state detection circuit 2 so as to be converted into a trinary level signal corresponding to the binary level signal. Thus, the circuit does not essentially receive the effect of the variation of temperature of the signal level and the variation of DC voltage caused by the variation of power source voltages, etc., because it is constituted as the circuit of the AC-combination type.

Description

[Detailed description of the invention]

FIELD OF THE INVENTION The present invention relates to a binary/ternary level signal conversion circuit. More specifically, the present invention converts an input signal into a signal when there is no signal.

The present invention relates to a novel configuration of a circuit that converts into three predetermined levels: a [0] level, and predetermined [+1] and [-1] levels. 2. Description of the Related Art The binary/three-value conversion circuit referred to here converts a burst-like binary level signal consisting of [1, 0), and in a no-signal state, the signal amplitude is at an intermediate level.

To [0] level, 2 at signal time
Each level of value ll:1.0:] is a predetermined value (+1
．． -1) into a signal consisting of three different levels. FIGS. 5(a) to 5(C) are diagrams showing the operation of a conventional binary/ternary conversion circuit. FIG. 5(a) shows the signal waveform of an input signal, and FIGS. FIG. 5C shows the signal waveform of the generated ternary level signal. That is, in the conventional binary/three-value conversion circuit, the input binary signal as shown in FIG. 5(a) becomes old gh or Low only when the signal shown in FIG. generate a gate signal, use this gate signal to DC voltage shift the input signal by half the signal amplitude,
A ternary level output signal as shown in FIG. 5(C) was obtained. Problems to be Solved by the Invention In the conventional circuit operating system as described above, the input binary level signal is converted into a three level signal by DC voltage shifting. The signal level is easily affected by temperature fluctuations, etc. However, when attempting to correct such level fluctuations using a so-called temperature compensation circuit, the circuit configuration becomes complicated, which is extremely disadvantageous in terms of operating speed, manufacturing cost, etc. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a novel binary output signal waveform that is not affected by DC voltage fluctuations due to temperature fluctuations, etc., in other words, provides an output signal waveform with small pulse width distortion. An object of the present invention is to provide a three-value conversion circuit. Means for solving the problem, that is, according to the present invention, a binary level burst input signal is set to an intermediate value level (0) when there is no signal, and (1, 0) when a signal is input, respectively (+1°-1 ) convert to 2
A value/three-value level signal conversion circuit, comprising: a first high-pass filter to which an input signal is input; and a signal state detection circuit that maintains one of predetermined 200 million levels depending on the presence or absence of the input signal; a second high-pass filter to which the output of the signal state detection circuit is input, and by superimposing the outputs of the first and second high-pass filters, a signal corresponding to the input binary level signal is obtained A binary/ternary level signal conversion circuit is provided that outputs a value level signal. Operation The binary/triple level signal conversion circuit according to the present invention solves the above problems by configuring the circuit by AC coupling instead of operation by DC voltage shift, which is easily affected by level fluctuations due to temperature characteristics, etc. Its main feature is that it solves the following problems. That is, in this circuit, the input binary burst signal is passed through a high pass filter (hereinafter referred to as HP F).
By passing the AC coupled input signal through a filter (denoted as filter), the impulse signal is taken out from the impulse generation circuit by the gate signal obtained from the signal state detection circuit, and the impulse signal is mixed with the AC coupled input signal. Performs 3-level waveform shaping. EXAMPLE The configuration of the circuit according to the present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one example of the present invention, and the technical scope of the present invention is not limited in any way. It's not something you do. FIG. 1 is a diagram showing an embodiment of a binary/ternary level signal conversion circuit constructed according to the present invention. As shown in the figure, this circuit has a HP
FI, a signal state detection circuit 2 connected in parallel with this HPF1, and an HPF 3 as an impulse signal generation circuit.
It is mainly composed of. Furthermore, in order to prevent the two signal paths described above from forming a feedback, a buffer 4.5 is provided at the output 1 of each HPFI, 3.
were established respectively. Therefore, in this circuit, the input binary burst signal is AC-coupled by the HPF, and is added to the impulse large signal generated by the impulse generation circuit from the gate signal obtained from the signal state detection circuit. Ru. FIGS. 2(a) to 2(e) are diagrams for explaining the operation of the circuit shown in FIG. 1, and each shows the waveform of an input signal processed by each element. The signal waveform shown in FIG. 2(a) is a binary level burst signal input to this circuit. Furthermore, here,
The duty ratio of this signal is assumed to be 50%. When this input binary signal is AC-coupled by HPF 1, the signal level reaches a steady value at a response speed determined by the time constant of HPFI, as shown in FIG. 2 (5). In addition, in this example, the duty ratio was set to 50%, so
The steady-state value is the reference voltage level equal to half the signal amplitude. On the other hand, the signal state detection circuit 2 is a general gate signal generation circuit, and as shown in FIG. Occur. This gate signal is input to HPF3, as shown in Fig. 3(d).
As shown in the figure, it functions as an impulse generation circuit that generates impulse signals when the voltage rises and falls. The input signal generated in this way converges to a steady level,
When mixed with the impulse signal, the sag at the beginning and end of the signal waveform shown in Figure 2 (b) is canceled, and a signal equivalent to the ternary bell signal corresponding to the input binary bell signal is output. be done. Note that the signals shown in FIGS. 2(a) and 2(d) are both signals after AC coupling, and are not affected by DC voltage fluctuations in the preceding stage circuit. The operation of the binary/ternary level signal conversion circuit of this embodiment as described above will be described in detail below. For clarity of explanation, here the input signal is expressed as raised-cosi
Treated as ne wave. FIG. 4 is a diagram illustrating the operation of the binary/ternary level signal conversion circuit shown in FIG. 1. Assuming that the input signal is s (t), this signal is expressed by the following formula (
It can be expressed as in 1). When this is Laplace-transformed, the equation can be expressed as follows: S (s) = L C3 (t)] On the other hand, HPFl is a CR type circuit as shown in Fig. 3, and this circuit Let H(s) be the transfer function of
The Laplace transform Y(s) of can be expressed as follows. Y (s) = S (s) ・H(s) (4) Comparing this equation (4) with equation (2), the first term on the right side shows that H(s) has a step with an amplitude of 2. Equivalent to giving a function input. That is, by deleting this term, the influence of the DC component of the output signal can be canceled. Therefore, the impulse generation circuit, which is also an HPF, is
Focusing on the operation as a PF circuit, it can be expressed as follows. Therefore, by substituting this into equation (4), Y'(s)=L
Cy (t)) = Y (s) −C(s) ・G(s)・5(s)・
-(6) However, G(s) represents a transfer function for detecting a signal state from s(t) and extracting a gate signal. It can be expressed as. That is, a gate circuit that generates a gate signal as shown in FIG. 2 (C) in response to a burst signal or an equivalent gate signal is input from an external source, and the time constants of H(s) and C(S) are If the values of T are set equal, the operation of the binary/triple level signal conversion circuit as described above can be realized. Effects of the Invention As detailed above, the binary/triangle constructed according to the present invention
The value level signal conversion circuit is capable of converting a binary level burst signal into a ternary level signal, and although it has an extremely simple circuit configuration, it is configured as an AC coupling type circuit, so the signal The circuit is essentially unaffected by DC voltage fluctuations due to level temperature fluctuations or power supply voltage fluctuations. Therefore, in the conventional field of communication technology, it can not only be used advantageously as a circuit for transmitting ternary burst signals with high signal quality and suppressing pulse width distortion to the utmost, but also It can also be used as an extremely advantageous communication means in the field of optical communications where signal amplitudes vary greatly. This is because in a binary level burst signal, the DC voltage level of the entire signal varies between when there is no signal and when there is a signal.
This is because the ternary burst signal does not cause fluctuations in the DC component of the signal level both when there is no signal and when there is a signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a binary/ternary level signal conversion circuit constructed according to the present invention. FIG. 3 is a waveform diagram for explaining the operation of the illustrated circuit, showing the output waveforms of each element constituting the circuit, and FIG. FIG. 4 is a block diagram for explaining the operating principle of the binary/triple level signal conversion circuit according to the present invention; FIG. 5(a) 5 to (C) are waveform diagrams for explaining the operation of a conventional binary/triple level signal conversion circuit.
Figure (a) shows the signal waveform of the input signal, Figure 5 (5) shows the gate signal waveform, which will be described later, and Figure 5 (C) shows the signal waveform of the generated ternary level signal. . (Main reference numbers) 1...H, P, F (high pass filter), 2...Signal condition detection circuit, 3...H, P, F (impulse generation circuit), 4.5...
・Buffer circuit

Claims (3)

[Claims] (1) A binary/ternary level signal that converts a binary level burst input signal to an intermediate level (0) when there is no signal, and converts (1, 0) to (+1, -1) respectively when a signal is input. The conversion circuit includes a first high-pass filter to which an input signal is input, a signal state detection circuit that maintains one of predetermined binary levels depending on the presence or absence of the input signal, and the signal state detection circuit. a second high-pass filter to which the output is input;
A binary/ternary level signal conversion circuit, characterized in that it outputs a ternary level signal corresponding to the input binary level signal by superimposing the output of the second high-pass filter. (2) The binary/triple level signal conversion circuit according to claim 1, wherein the time constants of the first high-pass filter and the second high-pass filter are equal to each other. . (3) The first and second high-pass filters are CR
3. The binary/ternary level signal conversion circuit according to claim 1, wherein the circuit is a type high-pass filter circuit.