JPS63232336A - Etching of double-layer wiring film - Google Patents
Etching of double-layer wiring filmInfo
- Publication number
- JPS63232336A JPS63232336A JP6393187A JP6393187A JPS63232336A JP S63232336 A JPS63232336 A JP S63232336A JP 6393187 A JP6393187 A JP 6393187A JP 6393187 A JP6393187 A JP 6393187A JP S63232336 A JPS63232336 A JP S63232336A
- Authority
- JP
- Japan
- Prior art keywords
- chamber
- etching
- film
- wafer
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 27
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 11
- 239000000956 alloy Substances 0.000 abstract description 11
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052801 chlorine Inorganic materials 0.000 abstract description 7
- 239000000460 chlorine Substances 0.000 abstract description 7
- 238000005260 corrosion Methods 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 abstract description 5
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052731 fluorine Inorganic materials 0.000 abstract description 4
- 239000011737 fluorine Substances 0.000 abstract description 4
- 229910052717 sulfur Inorganic materials 0.000 abstract description 4
- 239000011593 sulfur Substances 0.000 abstract description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 13
- 230000007423 decrease Effects 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000295 emission spectrum Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は二層配線膜のエツチング方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of etching a two-layer wiring film.
従来は、特開昭６０−３３３６７号に記載のように二層
配線膜のエツチングを行う場合、上部のアルミニウム合
金膜のエツチングに続けて同一チャンバ内で下層金属層
（ＴｉＷ膜層）をエツチングしていた。Conventionally, when etching a two-layer wiring film as described in JP-A No. 60-33367, the lower metal layer (TiW film layer) was etched in the same chamber after etching the upper aluminum alloy film. was.
上記従来技術はＡｌ合金膜とその下層膜を同一チャンバ
で処理するようになっているため、異なるガスの混在に
対する配慮がされておらず、チャンバ内の汚染およびエ
ツチング性能への問題があった・
本発明の目的は、上記の問題を解決し、エツチング速度
の低下がなく、１１１食のない二層配線膜のエツチング
を行うことのできる二層配線膜のエツチング方法を提供
することにある。In the above conventional technology, the Al alloy film and its underlying film are processed in the same chamber, so there is no consideration given to the mixing of different gases, leading to problems with contamination within the chamber and etching performance. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for etching a two-layer wiring film, which solves the above-mentioned problems and allows etching of a two-layer wiring film without a decrease in etching speed and without 111 etchings.
上記目的は、ＡｆＬ合金膜と異種の金属ＩＩＩとから成
る半導体の配線材料のエツチング方法において、配線材
料の処理工程ごとに処理室を換えることにより、達成さ
れる。The above object is achieved by changing the processing chamber for each wiring material processing step in a method for etching a semiconductor wiring material consisting of an AfL alloy film and a different metal III.
処理されるウニへはチャンバに配設されてＡ１合金膜の
部分のエツチングが行われ、次にウェハは真空中に保持
されたまま、別のチャンバに配設され、下層膜（ＴｉＷ
膜）部分のエツチングが行われる。その後、ウェハは退
避室を経て大気中に排出される。なお、ＴｉＷのモッチ
ングが実行されている間、最初のチャンバでは次のウェ
ハにＡｌ合金膜のエツチングが実行されている。これに
より、１１合金膜エツチングに用いるガス（塩素系）と
ＴｉＷ膜エツチングに用いるガス（フッ素系、硫黄、系
）とが同一チャンバ内で混在することがないので、ウェ
ハ処理枚数を重ねるにつれ、ガスの混在によるエツチン
グ性能への影響、特に人文合金膜エツチングの速度の低
下が防止でき、又、Ｔ ｉ Ｗ膜を処理するチャンバに
塩素系ガスが混入しないのでウェハを大気中に搬出した
後の腐食を防ぐことができる。The wafer to be processed is placed in a chamber where the A1 alloy film is etched, and then the wafer is placed in another chamber while being held in vacuum to remove the underlying film (TiW).
Etching of the membrane) portion is performed. Thereafter, the wafer is discharged into the atmosphere through the evacuation chamber. It should be noted that while the TiW mocking is being performed, the Al alloy film is being etched on the next wafer in the first chamber. This prevents the gas used for etching the No. 11 alloy film (chlorine-based) and the gas used for etching the TiW film (fluorine-based, sulfur-based) from coexisting in the same chamber. It is possible to prevent the influence on etching performance due to the mixture of wafers, especially the decrease in the etching speed of humanities alloy films, and since chlorine-based gas does not enter the chamber that processes the TiW film, there is no corrosion after the wafer is carried out into the atmosphere. can be prevented.
以下、本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
ロードロック室１、チャンバ２、ロードロック室３、チ
ャンバ４、ロードロック室５を順次連結して成り、それ
ぞれは真空引きされていて、ロードロック室１．５は大
気開放が可能となっている。It consists of a load-lock chamber 1, a chamber 2, a load-lock chamber 3, a chamber 4, and a load-lock chamber 5 connected in sequence, each of which is evacuated, and the load-lock chamber 1.5 can be opened to the atmosphere. .
処理室であるチャンバ２．４には図示しない別々のガス
供給手段がつながれ、図示しない別々の排気装置により
所定圧力に減圧排気されている。また、チャンバ２．４
には処理ガスをプラズマ化させる放電手段、この場合は
、高周波電力が印加される平行平板型電極が設けられ、
さらに処理の終点を判定する終点判定手段が設けられて
いる。ロードロック室１，３．５にはそれぞれ大気中と
チャンバ２との間、チャンバ２と４との間およびチャン
バ４と大気中との間でウェハを搬送するアームまたはベ
ルト等の搬送手段が設けである。A separate gas supply means (not shown) is connected to the chamber 2.4, which is a processing chamber, and the gas is evacuated to a predetermined pressure by a separate exhaust device (not shown). Also, chamber 2.4
is provided with a discharge means for turning the processing gas into plasma, in this case a parallel plate type electrode to which high frequency power is applied,
Furthermore, end point determining means is provided for determining the end point of the process. Load lock chambers 1 and 3.5 are each provided with transport means such as an arm or a belt for transporting wafers between the atmosphere and chamber 2, between chambers 2 and 4, and between chamber 4 and the atmosphere. It is.
上記構成の装置により、ウェハ６はロードロック室１を
経てチャンバ２の電極上に配置され、Ａｌ合金膜部分の
みエツチングされる。ＡｆＬ合金膜部分のエツチングの
終了は終点判定手段により発光スペクトルをモニタする
ことにより判断される。With the apparatus configured as described above, the wafer 6 is placed on the electrode in the chamber 2 through the load lock chamber 1, and only the Al alloy film portion is etched. The completion of etching of the AfL alloy film portion is determined by monitoring the emission spectrum by the end point determining means.
次にウェハは搬送手段によりロードロック室３を経由し
て真空状態に保持されたままチャンバ４の電極上に配置
され、ＴｉＷ膜のエツチングを行う。Next, the wafer is placed on the electrode of the chamber 4 while being held in a vacuum state via the load lock chamber 3 by a transport means, and the TiW film is etched.
このエツチングの終了も終点判定手段により発光スペク
トルをモニタすることにより判断される。The end of this etching is also determined by monitoring the emission spectrum by the end point determining means.
エツチングを終了したつ゛エバ６はロードロック室５を
経由して、大気中に搬出される。After the etching has been completed, the evaporator 6 is carried out into the atmosphere via the load lock chamber 5.
チャンバ２でＡ４ｕ合金膜がエツチングされている間、
チャンバ４では他のウェハのＴｉＷ膜がエツチングされ
、また、チャンバ４でＴｉＷ膜のエツチングが行われて
いる間、チャンバ２では新しいウェハのＡ１合金膜がエ
ツチング処理されている。このように、チャンバ２では
塩素系のガスを用いてＡ１合金膜のエツチングだけを行
い、チャンバ４ではフッ素系、硫黄系のガスによりＴＩ
Ｗ１１！（７）エツチングだけを行う。While the A4u alloy film is being etched in chamber 2,
In chamber 4, the TiW film of another wafer is being etched, and while the TiW film is being etched in chamber 4, the A1 alloy film of a new wafer is being etched in chamber 2. In this way, in chamber 2, only the A1 alloy film is etched using chlorine-based gas, and in chamber 4, TI is etched using fluorine-based and sulfur-based gas.
W11! (7) Perform only etching.
以上、本−実施例によれば、従来のように塩素系めガス
とフッ素系または硫黄系のガスとが混在することがない
ので、ウェハの処理枚数を重ねるにつれて、ガスの混在
によるエツチング性能への影響、特にＡ１合金膜のエツ
チング速度の低下が防止できるとともに、ＴＩＷ膜をエ
ツチング処理するチャンバ内に塩素系ガスが混入しない
のでウェハを大気中に搬出した後の腐食を防ぐことがで
きる。As described above, according to this embodiment, chlorine-based gas and fluorine-based or sulfur-based gas do not coexist as in the past, so as the number of wafers processed increases, the etching performance due to the mixture of gases decreases. In addition, it is possible to prevent the effects of etching, especially a decrease in the etching rate of the A1 alloy film, and since no chlorine-based gas is mixed into the chamber in which the TIW film is etched, corrosion after the wafer is carried out into the atmosphere can be prevented.
本発明によれば、Ａｌ合金膜と異種の合金膜とを別々の
チャンバで処理するので、各々に使用するガスの混在に
よるエツチング速度の低下およびエツチング後の腐食を
防止することができるという効果がある。According to the present invention, since the Al alloy film and the different types of alloy films are processed in separate chambers, it is possible to prevent a decrease in the etching rate due to the mixture of gases used for each, and to prevent post-etching corrosion. be.
第１図は本発明の二層配線膜のエツチング方法を実施す
るための装置の一実施例を示す構成図である。FIG. 1 is a block diagram showing an embodiment of an apparatus for carrying out the method of etching a two-layer wiring film of the present invention.
Claims (1)
材料のエッチング方法において、配線材料の処理工程ご
とに処理室を換えることを特徴とする二層配線膜のエッ
チング方法。1. A method for etching a semiconductor wiring material consisting of an Al alloy film and a different metal film, which is characterized in that the processing chamber is changed every time the wiring material is processed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6393187A JPS63232336A (en) | 1987-03-20 | 1987-03-20 | Etching of double-layer wiring film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6393187A JPS63232336A (en) | 1987-03-20 | 1987-03-20 | Etching of double-layer wiring film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63232336A true JPS63232336A (en) | 1988-09-28 |
Family
ID=13243588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6393187A Pending JPS63232336A (en) | 1987-03-20 | 1987-03-20 | Etching of double-layer wiring film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63232336A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0456135A (en) * | 1990-06-21 | 1992-02-24 | Nec Corp | Manufacture of semiconductor device having metal layer of laminated structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6258636A (en) * | 1985-09-09 | 1987-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Dry etching process and device thereof |
-
1987
- 1987-03-20 JP JP6393187A patent/JPS63232336A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6258636A (en) * | 1985-09-09 | 1987-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Dry etching process and device thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0456135A (en) * | 1990-06-21 | 1992-02-24 | Nec Corp | Manufacture of semiconductor device having metal layer of laminated structure |
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