JPS63231648A - Cache memory erasing system - Google Patents

Abstract

PURPOSE:To eliminate a need of a selector which gives the address of a V bit part, to shorten the delay time of the cache mishit/hit discriminating pass by using the address array unuse time due to cache miss to erase all entries. CONSTITUTION:When a following cache access request (address=A) is accepted at a timing t1, the request address A is set to a logical address register 10 and an entry designating part (a) of an address array 32 of the request address A is set to an entry address register (EAR) 11 through a selector 20. When the entry having the entry number (a) is checked at a timing t2 to discriminate cache mishit, value '0' of a counter 12 is loaded to the EAR 11 and contents of the counter 12 are counted up by one. At a timing t3, the entry having entry number 0 of the unuse-side V bit is cleared and contents '1' of the counter 12 are set to the EAR 11 and contents of the counter 12 are counted up by one furthermore. At a timing t12, the entry having entry number 9 is cleared.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a cache memory erasing method.

[Conventional technology]

Referring to FIG. 3, this type of cache memory erasing method conventionally has an address correspondence between the data array 34 that stores a copy of the data in the main memory in a predetermined unit C (called a block) and the data in the main memory. An address array 33 consisting of entries managed in block units, an all-clear counter 12 that holds the number of erased entries, and an address array 3
A selector that switches between the register 11 and the all-clear counter 12 based on a register 11 that holds an entry address for identifying the entry No. 3, and a used V-bit display flag 70 that indicates the system of validity display bits (hereinafter abbreviated as V-pit) in use. It has selector A and selector B, and executes all entry deletion as follows.

That is, when flag 70 is off, V bit A 31st
is at register 11! /selector A2 so that the V bit B system 32 is addressed by the all clear counter 12.
1 and selector B22, the selector 23 selects the v-bit A system 31 and uses it. When the flag 70 is on, the switching is reversed and the v-bit B system 31 is used.

When the cache memory control unit 80 accepts the all entry deletion request, it inverts the value of the flag 70 and
The request processing is completed by switching the bit system, but after the V bit system that was used becomes unused, it is addressed by the all clear counter 12, and the all clear counter is counted in order from the 0th entry. Delete all entries while uploading.

While the unused V-bit system is being cleared, the used v-bit system can process subsequent cache access requests, and all entries are deleted after the unused V-bit system is cleared. In response to acceptance of the request, the value of the flag 70 is inverted again and the same operation is performed.

Therefore, the processing time for erasing all entries can be executed in a short time from the perspective of the request source, but for this purpose, two or more systems of V bits are provided, and each system is provided with a selector for selecting the address of the V bit section. There was a need.

[Problem that the invention seeks to solve]

In the conventional cache memory erasing method described above, in order to erase all entries by switching the v bit,
Each of them had an independent selector for giving the address of the v-bit part storing two systems of ``hits''.

Therefore, the delay time of the path for determining a hit or miss in the cache memory, that is, the path from the entry address register 11 to the connection line 611 in FIG. 3 becomes large. Furthermore, since it is necessary to give addresses independent of other cache memories to the two systems of the hit section, an independent RAM (random read/write memory) chip must be used for the V bit section, but currently RAM and LS
The degree of integration of I is increasing year by year, and as the RAM capacity increases, the number of bits in the V bit section is, for example, 2 bits for V pit and parity, so it is conceivable that the RAM cannot be used effectively.

erasing all entries of a cache memory having a means, an address array means consisting of a plurality of entries for associating the data array means with the main memory, and two systems of validity indicating bits corresponding to the entries of the address array means; In the method, in response to acceptance of an all entry deletion request, the validity indication bits in use are made unused, and after switching to use the validity indication bits in use, the validity indication bits are made unused. Cache memory erasing method 1-2h characterized in that the validity indicating bit is erased using the processing time of a plurality of subsequent cache misses [Embodiment] Next, the present invention will be described with reference to the drawings. This will be explained in detail. Referring to FIG. 1, one embodiment of the present invention includes a real address register 10 that holds a requested address associated with a cache access request, an address array 33 in the requested address,
It has an entry address register 11 that holds a part indicating the entry of. Normally, the real address register 10 and the entry address register 11 set the requested address at the timing when a cache access request is accepted by the cache memory control unit 80. The selector 1 is a circuit that switches the input of the entry address register 11 (hereinafter abbreviated as EAR).The selector 1 is a circuit that switches the input of the entry address register 11 (hereinafter abbreviated as EAR). Either the entry instruction part of the real address register 10 or the requested address for returning is selected. V bit is V bit A system 3
1 and V bit B are stored in the 32nd position, and constitute a cache memory together with an address array 33 that stores a part of the real address register and a data array 34 that stores a copy of the data in the main memory. In the selector 23, either the ■ bit of the V bit A system 31 or the V bit of the V bit B system 32 is selected according to the convenient V bit display flag 70. The selected V bit is connected to the AND gate 61 by a connection 231. is input.

On the other hand, the contents of the address array 32 and the requested address are checked by the comparison circuit 40, and if they match, the connection 401
111 is output to the AND gate 611/(: is input. The AND gate 61 performs a logical product, and the output is called a cash hit signal 611, which is a signal indicating that the desired data is present in the data array 33. Yes, the data output from the teltar array 33 is valid.When the hit signal 611 is 10' in response to a cache access request, it is called a cache miss. is read from the main memory and registered in the data array 33 via connection 801.

Next, the operation of erasing all entries will be explained in detail. When the request to erase all entries is accepted via the cache access request line 800, the request is cleared.

V bit display flag 7 used in the memory control unit 80
The value of 0 is inverted and the using side V bit is switched, but
Unlike the conventional method, clearing of the V bit on the side that is no longer used does not start execution immediately, but waits. When the cache access request that follows the all-entry deletion request is accepted and results in a cache miss, as described above, the time spent performing the middle cache miss processing is used to update the unused side of V. Bit clearing is performed.

It usually takes about 10 hours to erase a ctf-enabled entry in the same cache miss processing time. Since the number of entries in the address array 33 is 256 in this embodiment, the IIoI cache miss processing is not completed, and the subsequent cache miss processing is repeatedly utilized to complete clearing of all entries. The all-clearing flag (included in the cache-memory control unit 80, but not shown) that indicates that unused V bits are being cleared turns on when an all entry erase request is accepted, and unused V bits clearing is completed. Then it turns off.

If the all-clear flag is on and a subsequent all-entry erase request is accepted, it waits for the subsequent all-entry erase clean-up to be executed, and also waits for the address conversion request to be executed after the I-, JLC. The button is designed to cause IJ deletion to be executed preferentially, and to start executing subsequent IJ deletion requests in the above-mentioned procedure at the time of completion. Therefore, if the next all entry erase request is issued while all entry erasure is incomplete, instruction execution will be delayed by the wait time for the subsequent cache access 4 7 address conversion request, but all cache entries will be The frequency with which erasures occur is so low that performance degradation is rarely a problem.

Next, when the all-clearing flag is off and the used bit display flag 70 is 101, the operation when an all-entry erasing request is accepted will be described in detail with reference to FIGS. 1 and 2.

Referring to FIGS. 1 and 2, according to instructions from the cache memory control unit 80, the used Mbit display flag 70 is updated from 101 to 111, and the all clear flag is switched from an OFF state to an ON state. V bit is selector 2
3, the V-bit A system 31 selected is switched to the B-system 32 (beep), and the clearing process for the unused V-bit A system 31 is postponed.

Here, we will explain the clearing process when a cache miss occurs in a subsequent cache access request.

Timing t in Figure 2! When a subsequent cache access request (address=A) is accepted, the requested address A is set in the logical address register 10, and the entry designation section a of the address array 32 for the requested address A is
is set to EARII via the selector 20. At timing t2, entry number 8 is checked and if there is a cache miss, the value of counter 12 is 10 in EARll.
1 is loaded, and the counter 12 is counted up by wlw. At timing t3, the entry number 0 of the unused V bit is cleared, the content 111 of the counter 12 of BARII is set, and the counter 12 is further counted up by K "1". After that, the execution is repeated in the same device, and when the cache miss processing ends - (at timing t12 before mink"13, entry number 9
Clearing is executed, and EA and Rlt hold the requested address A in order to record the cache miss processing entry in the address array 33GCf. real address register 1
Fetch address a from 0. The all-clear counter 12 does not increment by 1 and retains its contents (10) until the next cache miss. Timing h! Then, an entry is registered in the address array 33 and an instruction is given to accept the next cache access request (request address=B).

In this way, the V bit clearing process is interrupted when the cache miss process is completed, and the V bit clearing is performed successively starting from entry number 10 while waiting for the next cache miss. Repeat this to clear all entries.

As described above, in the present invention, all entries are erased using the time when the address array 33 was unused while processing a conventional cache miss.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for a selector that provides the address of the V bit part by using a method of erasing all entries by using the unused time of the address array due to a cache miss, and eliminates the need for a selector that provides the address of the V bit part. It is possible to shorten the delay time of
This has the advantage that an address array can be efficiently constructed using AM.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the embodiment, and FIG. 3 is a diagram for clarifying the conventional system. In Figures 1 to 3, 10, 11, 50...
...Register, 12...Counter, 20, 21
, 22.23...Switching circuit, 31.32.33
．． 34...Memory, 40...Comparison circuit, 61...--And gate, 62... Agent Patent attorney Susumu Uchihara-,'-1・1 11th end address 1 diagram

Claims (1)

[Claims] Data array means for storing a copy of data in main memory; address array means comprising a plurality of entries for associating the data array means with the main memory; In an all entry erasing method for a cache memory having two systems of validity indicating bits, in response to acceptance of an all entry erasing request, the validity indicating bits in use are made unused, and the unused validity indicating bits are cleared. A cache memory erasing method characterized in that after switching to use the display bit, erasing the unused validity display bit is performed using the processing time of multiple cache misses that occur thereafter. .