JPS63231620A - Data merging system - Google Patents

Abstract

PURPOSE:To increase the processing speed by executing the merging operation, where a storage area where plural data strings each of which includes p-number of records are arranged in the address order and a storage area where plural data strings each of which includes q-number of records are arranged in the address order are coupled, with one instruction from a processor. CONSTITUTION:With respect to the merging operation, records are read out from storage areas 5A and 5B one by one from their start addresses in accordance with the indication of a merge control circuit 3 by a data merging circuit 9. The data merging circuit 9 compares keywords and successively writes records in storage areas 6C and 6D in accordance with the keyword order designated by a data merging instruction 8. As the result, data strings 7 each of which includes (p+q)-number of records and which are arranged in the keyword order are completed in storage areas 6C and 6D. The output of the data merging circuit 9 is switched each time when merging of one data string is completed, and merged data strings are alternately stored in storage areas 6C and 6D.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a data sorting and merging method. Regarding a data merging device used to perform a so-called merging operation that combines multiple sorted data columns into one sorted data column, it is particularly applicable to merging a large number of sorted data columns. If this is the case, it relates to a system that can be executed with one instruction without repeatedly issuing →-ji instructions.

[Industrial application field]

Editing data with the same attributes into record format, arranging a large number of records in the order defined by the keywords, a so-called "sort" operation, and combining many sorted data columns into one column using similar keywords. The so-called "merge" operation of sequential rearrangement is currently widely used, especially in business data processing. When there is a large number of records, it is necessary to divide the records into a certain number of records and repeat the merge operation for each division, but there is a need for a means to simplify this process and improve the efficiency of the software.

[Conventional technology]

Operations for sorting and merging large amounts of data are often used, especially in the processing of office data, and are usually performed by software. In addition, various methods have been proposed in which the circuit is made into hardware for the purpose of executing this at high speed.

The contents of the sorting and merging operations are well known, and many methods have been introduced in literature, so detailed explanations thereof will be omitted.

FIG. 4 shows an outline of the conventional merge method processing, and its problems will be explained. In the figure, data columns ■～■ are
A data column in which a large number of records all with the same attribute are sorted by the same keyword, and record A is in the data column ■.
The nine records of OI-Ap are arranged in the order of their keywords, and the q records of records BOI to Bq are arranged in the data string ■. All the columns from ■ to ■ are structured like this. Dividing and sorting a large amount of data into multiple groups consisting of p and q records like this is easier to process if the data is organized into a size that can be accommodated in a unit of storage area, such as one page. This is convenient, and also because sorting an extremely large amount of data at one time takes more processing time than dividing it into relatively short groups and sorting. Also, usually the size of each data string is p
, q are equal, but in this case, p, q
so that they are not equal.

A sorted data string is a data string obtained by dividing a large amount of data arranged in random order of keywords into an appropriate number of records and rearranging them in order of keywords, so the record arrangement within each data string from ■ to ■ is based on keywords. However, there is no size relationship of keywords between each data string.

In such a case, the merge operation extracts two data columns and merges them, and as shown in the figure, the number of data columns is halved and the length of each data column is doubled in the first merge. In Figure 0, a data string (2) with a length of p and a data string (2) with a length of q are merged to generate a data string (2) with a length of -p+q. Similarly, the data strings of ■ and [phase] are merged as a zero-order second merge that @ generates when ■ and ■ are merged, and the data string of ■ and [phase] are merged, and the length is 2 (p + q).
data strings are generated. After that, merging is repeated in the same manner, and finally one data string arranged in keyword order is completed and the merging operation is completed.

When performing a merge of many data columns in this way,
Merge operations may be executed by a program or by hardware, such as the Vibrine method, but in either case, merge instructions or similar program routines are usually executed many times. be.

The number of times a command is issued is the same as in a tournament-type game, and if the total number of data strings is n, the number of times a command is issued is n-1. For example, if there are 100 data strings, the command will be issued 99 times.

In particular, when merging large amounts of data, a hardware-based high-speed merging device is required, and as the merging circuit speeds up, time loss due to the large number of instructions issued becomes a problem, so this can be reduced and processed. A demand has arisen for further increases in speed.

[Problem to be Solved by the Invention 3] As explained above, even if the processing speed of the merging device is improved, the increase in the frequency of instruction access on the processing device side hinders the improvement in performance. It is possible to realize a means to reduce this as much as possible.

[Means for solving problems]

In order to achieve the above object, the present invention uses a data merging method whose principle is shown in FIG.

A storage area 5 in which a plurality (r) of data strings 4A including nine sorted records are arranged in consecutive address order.
A and a storage area 5B in which a plurality (s) of data strings 4B including nine records are arranged in the order of consecutive addresses are to be merged.

The merge control circuit 3 receives a data merge command 8 from the processing device 2.
control the execution of merge instructions.

The data merge instruction 8 includes the start addresses of the storage areas 5A and 5B, the numbers p and q of records included in the data strings 4A and 4B, and 1! The total numbers m and n of records included in areas 5^ and 5B are specified together with the merge command.

The merge operation is performed in the data merge circuit 9 in accordance with instructions from the merge control circuit 3 in the storage area 5A.

5B, keywords are compared in the data merge circuit 9, and records are sequentially written into the storage areas 6C and 60 in the order of the keywords specified by the data merge command 8.

As a result, records p+q are stored in storage areas 6C and 6D.
The data strings 7 arranged in the order of keywords are completed one after another, and each time the merging of one data string is completed, the output of the data merging circuit 9 is switched, and the merged data strings are stored alternately in the storage areas 6C and 6D. Accumulated.

[Effect]

The processor performs a merge operation that combines a storage area configured by arranging a plurality of data strings containing p records in address order and a storage area formed by arranging a plurality of data strings including q records in address order. Execute with one instruction.

〔Example〕

Examples of the data merging method according to the present invention are shown in FIGS. 2 and 3.
This will be explained using figures. Since the contents of the data merging operation are well known, this section will explain the operation of the data merging device according to the present invention and the format of the data merging command, which is the gist of the present invention.

FIG. 2 shows the main configuration of a data merging device according to the present invention. In this figure, thin lines indicate address designations, medium thick lines indicate control information, and thick lines indicate paths for data to be merged. Storage area 5A.

5B is a set of data columns to be merged,
The first storage area 5A contains one data string containing p sorted records, indicated by SAI to SAr, and the second storage area 5B contains sorted q records, indicated by SBI to SBs.
Three data strings containing records are stored. Here, the data string located at the end of the storage areas 5A and 5B has p
, it may not necessarily contain q records; it may be irregular. Further, as mentioned before, normally p=q, but for the purpose of general explanation it will be expressed as pf-q.

4A and 4B are examples of record arrays inside the data string, and in this figure, data string SA3. This shows the inside of SC2. Inside the sorted data string S^3, p records RA31 to RA3p are arranged in the order of keywords in the direction of increasing addresses. SC2 is similarly configured.

Each of these data strings SAI to SAr has the same characteristics as the data strings shown by ■ to ■ in FIG. 4 as a conventional example. Therefore, although records are arranged in the order of keywords within each of SAI to SAs, there is no order relationship of keywords between each data string. For example, SAd
It cannot be guaranteed that the keyword of the record within is greater than the keyword of the record within S^3.

In addition, each data string SAI to SAr is arranged at consecutive addresses, but this is because there is no empty space between the storage areas of the sort results during the sort operation that is executed in the previous stage by a separate program or mechanism. Arrange it like this. This is necessary from the viewpoint of effective use of the storage area, and two columns of storage areas 5A and 5B are generated by such a procedure at the stage of the sorting operation, which will not be explained here.

The data merging operation is started when the processing device 2 issues a data merging command 8 to the control circuit 30.

The merge control circuit 3 in FIG. 1 corresponds to all the circuits marked with numbers 30 in FIG. 2.

Next, FIG. 3 shows the format of the data merge command 8 issued by the processing device 2, which is the gist of the present invention. The instruction word of the processing unit 2 normally uses one word in the storage device consisting of about 16 or 32 bits, but we will not specifically define the details of the instruction code here. A configuration example will be explained.

This instruction takes the form of indirect specification by register specification, and the first field of the instruction word is an instruction code, in which a data merging instruction is placed like a commonly known computer instruction. The second and third fields are specified by registers, R1 and R2.
Specify a general-purpose register. Similar to known methods, the program writes in advance the specified contents necessary for the data merging operation in the general-purpose register. In the second field, two registers are designated as R1 as shown in the figure, and here are the start addresses of the third and fourth storage areas 6C and 60 where the merged data is stored, and separately the control circuit 30.
Storage area 6C written as the merge execution result by
, 6D is filled in. This is used to confirm that the instruction has definitely completed execution by comparing it with the specification of the total number of data described below.

In the third field, three registers are specified as R2 as shown in the figure. Register 0 contains information necessary for merging, including the position of the keyword within each record, the length of the keyword, and the total length of the record. The register 1.2 includes first and second storage areas 5A,
5B start address, total number of accumulated records m,
n, number of records composing data strings 4A and 4B p, q
is entered.

In FIG. 2, when a data merge instruction 8 as shown in FIG. The information is read out and distributed to each part within the device as follows.

a. Start address of storage area 5A (R5A) → RSA
(SA address register), 35Ab, storage area 5
Start address of B (R2O) → RSB (SB address register), Start address of 35BC4 storage area 6C (R5O) → R5O (So address register),
36Cd, start address of storage area 6D (RSI) -
RSI (SL address register), 36De, number of records p (RCA) - RCA (A record counter),
34A f, number of records q (RCB) → RCB (B record counter), 34B g, p + q obtained from the above record numbers p and q →
I? CC (C record counter), 37h, storage area 5
The total numbers m and n of records constituting A and 5B are held in the control circuit and used to determine the end of the merge operation.

i, the position and length of the keyword are sent to the key comparison circuit 10 and used to extract the keyword from the record.

The data merging operation starts upon completion of the above numerical settings. First, RSA 35A.

Read the first record of the storage areas 5A and 5B specified by the RSB 35B, that is, the first record of each data string of SAI and SBI, input the keyword to the key comparison circuit 10 in the data merging circuit 9, and compare the size. Make a comparison. The record determined to be smaller as a result of the comparison passes through the switching circuit 11 and is stored at the address designated by the R5O36C in the third storage area 6C for storing merge results. At the time of startup, the switching circuit 11 is connected to the control circuit 30.
Set it to the 6C side.

When the determination of the roux code is completed as described above, the records from the storage area 5A in the figure, for example, the side that outputs the records accumulated in the storage area 6C, are stored in the storage HMi 6.
A record counter RCA that is stored at the first record address of C, in this case RSA 35A plus the record length and at the same time indicates the number of records that make up the data string.
34A is -1. Also, in the third storage area 6C, an address register R indicating the position of the next record to be stored.
The record length is also added to SO36C, and the record counter RCC37, which indicates the number of records stored at the same time, is set to -1.
At the same time, the value of the total number m of data held in the control circuit 30 is subtracted by 1 and the process moves to the next comparison.

The record determined to be larger in the previous comparison remains in the key comparison circuit 10 as it is, and the record accumulated in the third storage area 6C is output to the storage areas 5A and 5B.
Since either address register RS^35A or RSB35B has already been updated to indicate the start address of the next record, the next record is read using the updated address register and input to the key comparison circuit 10. The comparison, register, and counter are updated in the same manner as above. In this way, records are read one after another from the storage areas 5A and 5B, compared, and sequentially stored in the storage area 6C. FIG. 2 shows a scene where data strings SA3 and SR3 are merged and the resulting data string is stored in 803. As shown in the third data string 7, the resulting data string is such that the records are sorted in keyword order, for example RA31.
-RB31-----Aligned with RA3p. As a result of this operation, address register R3A 35^, RS
B 35B is added according to the number of records sent from the first and second storage areas 5A and 5B to the third storage area 6C, and at the same time record counters RCA 34A and RCB are added.
34B is subtracted. The total number of records m and n held in the control circuit 30 is also subtracted.

As you continue merging, eventually the record counter RCA
34A and RCB 34B will now indicate 0. This indicates that the record string on the side counted by the counter has been output to the end, and from now on, the record string on the opposite side will be stored unconditionally in the third storage area 6C until the end. good.

When both the record counters RCA 34A and RCB 34B reach O, the data string S^1. It is determined that the merge of SB 1 is completed, and the result is stored in the third storage area 6.
It is stored in the data string 501 of C as a data string including p+q records, and the next data string SA2. SR2
Move on to merging. At this time, the control circuit 30 switches the switching circuit 1 from the 6C side to the 60 side.
The accumulated light of the data string of the merge result is switched from the third storage area 6C to the fourth storage area 6D.

Data string SA in the same order as above 2. SB 2 is merged and stored in the fourth storage area 6D as a data string Sll. At this time, is the address register I? S136
D is used and R3O36C is paused.

The data merge command is executed by repeating the above operations, and as a result, the third and fourth storage areas 6C, 6
Data strings Sol to SOK, each merged into D,
Sll-S1K is accumulated. Here, data string S01
It is clear from the above explanation that data string SAI and SBI are merged, and data string Sll is obtained by merging data strings SA2 and SB2.

The total number of records m and n, which are separately held in the control circuit 30, are subtracted every time the code comparison is completed as explained above. It is determined that the merging is completed when m = n = Q. I can do it. Moreover, this merge operation can be executed with one instruction.

Furthermore, the resulting third and fourth storage areas 6C and 6
D can be merged by one data merging instruction shown in FIG. 3 using the same procedure as explained above.

By repeating the above steps, for example, the data string becomes 12
When there are 8 instructions, the conventional method required 127 instructions, but it can be completed with only 7 instructions.

In the above explanation, four sets of storage areas are used.
This may use four separate areas within one storage device, and as a faster and more effective data merging device, a pipeline method using four vibe line registers is an extremely effective method. becomes. Also, the total number of records is specified as m and n, but all data columns are p and q.
m if there is a guarantee that it contains records of
The value of n is not limited to the total number of records, but also the number of data columns,
A method of specifying r and s in FIG. 2 can also be easily conceived within the scope of application of the present invention.

〔Effect of the invention〕

By implementing the present invention, when merging many data strings consisting of the same number of records, one stage of merging operations for all data strings can be performed in one stage.
The data merging processing capability can be significantly improved by significantly reducing the number of times data merging commands are issued.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the data merging method according to the present invention, Fig. 2 is an embodiment of the data merging method according to the present invention, Fig. 3 is an embodiment of the data merging instruction according to the present invention, and Fig. 4 is data according to the conventional example. An example of the merge method is shown below. 1 to 4, 1 is a data merging device, 2 is a processing device, 3 is a merge control circuit, 4A, 4B are first and second data strings, 5A, 5B, 6C, and 6D are first to fourth data strings. , 7 is the third data string, 8 is the data merge command, 9 is the data merge circuit, 10 is the key comparison circuit, 11 is the switching circuit, 30 is the control circuit, 34A, 34B, 37 is the record counter, 35A ,
35B, 36C, and 36D indicate address registers.

Claims (1)

[Scope of Claims] A first storage area (5A) for storing a plurality of first data strings (4A) each consisting of p records, each sorted and arranged in the order of consecutive addresses;
A second storage area (5B) that stores a plurality of second data strings (4B) consisting of q records arranged in consecutive address order, and the first and second storage areas (5A) (5B).
) from the beginning by merging one data string, and the third data string (7) consisting of (p+q) records, which is the result of the above merging, is transferred to the third and fourth storage areas (6C) (6D). A data merging device (1) consisting of a data merging circuit (9) that allocates and accumulates data in a data merging circuit (9), and a merging control circuit (3) that receives a data merging command (8) from a processing device (2) and controls the above merging operation. ), the data merge command (8) issued by the processing device (2) to the merge control circuit (3) includes a detailed command regarding the merge operation, and the first and second storage areas (5A). The start address of (5B) and the number p of records that make up the data string (4A) (4B)
, q, the total number of records m and n constituting the first and second storage areas (5A) (5B), and the starting addresses of the third and fourth storage areas (6C) (6D) are indicated. According to instructions from the merge control circuit (3), the data merge circuit (9) merges the first and second storage areas (5A) (5B).
Execute a merge operation for one data string from the beginning of , and store the third data string (7), which is the merge result, alternately from the beginning of the third and fourth storage areas (6C) (6D), A data merging method characterized in that a plurality of data strings stored in the first and second storage areas (5A) and (5B) are merged by one instruction.