JPS63229943A - Packet multiplexer - Google Patents

Abstract

PURPOSE:To send data at a high speed while using less hardware by providing a buffer memory in the inside of a packet multiplex section, sending the data processed as a packet sequentially and assigning a prescribed time slot in a time-division multiplex section. CONSTITUTION:Data processed as a packet sent from each packet terminal 3 is inputted to one of plural packet multiplex sections 1 and stored tentatively in a buffer memory provided in the inside of each packet multiplex section 1. Each packet multiplex section 1 outputs a packet arriving first sequentially. A prescribed time slot is assigned to the output of each packet multiplex section 1 by a time-division multiplex section 2 and the output of the assigned time slot is sent from a transmission line 4.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving Problems Outline of Operation Example Configuration (Fig. 2) Basic Operation ( (Fig. 2) Details of configuration and operation (Fig. 2) Control procedure of the time slot adjustment circuit 2o (Fig. 3A,
(Figure 3B, Figure 3c,) Effect 0 in the packet multiplexer of Figure 2! iJ 呆 [Overview] This is a packet multiplexing device that multiplexes packetized data. By further time-division multiplexing the data from multiple packet multiplexing devices, it can achieve large capacity and high speed with a small hardware configuration. It enables data transmission.

[Industrial application field]

The present invention relates to a packet multiplexing device.

It has become possible to use high-speed lines such as optical communication, and it is desired to provide a device that can efficiently multiplex a large number of packets.

[Conventional technology]

A conventional general packet multiplexing device accommodates multiple low-speed packet terminals that send out packetized data.
Packets are multiplexed onto a high-speed line suitable for the traffic volume of all packet terminals.

FIG. 4 is a diagram showing the configuration of a conventional packet multiplexing device and its surroundings. In this figure, 1-1 is a packet multiplexing device, 10 is a packet multiplexing control circuit, 11 is a buffer memory, 12 is a transmission path, 13 is a selector, 3 is a packet terminal device, and 5 is a packet switch.

Each of the packet terminals 3 packetizes data and sends it out. These packetized data are temporarily stored in a buffer memory (FIFO memory) 11 provided corresponding to each packet terminal. The packet multiplexing control circuit 10 monitors whether a packet has arrived at each buffer memory 11, and when detecting the arrival of a packet, controls the buffer memory 11 to extract the packet from the memory 11 in the order in which the packets arrived. At the same time as the read packet is read out at high speed, the selector 13 is controlled so that the read packet is transferred to the transmission line 12.
It will be sent more frequently.

[Problem that the invention seeks to solve]

When introducing optical fibers capable of high-speed transmission into subscriber lines and accommodating high-speed packet terminals, the circuits and components that make up the packet multiplexing equipment are required to operate at high speed, as shown in Figure 4. Conventional packet multiplexers have the disadvantage that the number of terminals (number of lines) that can be accommodated is limited (for example, 8 lines) due to limitations caused by the operating speed of the devices used, such as the constituent circuits and parts. be. Therefore, when accommodating a large number of high-speed packet terminals (high-speed lines) using a conventional packet multiplexing device, the conventional packet multiplexing device needs to have a multi-stage configuration, as shown in Figure 5, for example. There is a problem in that the amount of wear increases, leading to an increase in cost.

In view of the above-mentioned problems, the present invention provides high-speed (
The purpose of this invention is to provide a low-cost packet multiplexing device that can accommodate a large number of packet terminals using a line (for example, 150 Mbps) and has a small hardware configuration.

[Means for solving problems]

FIG. 1 is a diagram showing the configuration of a packet multiplexing device and its surroundings according to the present invention. In this figure, 100 is a packet multiplexer according to the present invention, 1 is a packet multiplexer similar to a conventional packet multiplexer, 3 is a packet terminal, 4 is a transmission line, and 2 is a time division multiplexer provided according to the present invention. Department.

The packet multiplexer 1 temporarily stores the packetized data transmitted from each of the plurality of packet terminals 3 in an internal buffer memory (not shown), and processes the packets that arrived first from the packet multiplexer 1 . The data is transmitted sequentially within the time slot range assigned to the data. Time division multiplexing section 2
is time-division multiplexed by allocating a predetermined time slot to each of the outputs of the packet multiplexing unit 1 and transmitting the data to the transmission line 4.
Output to.

[For production]

Packetized data transmitted from each packet terminal 3 is input to one of the plurality of packet multiplexers 1, and further stored once in a buffer memory provided inside each packet multiplexer 1. Each packet multiplexer 1 outputs the packets in order from the packet that arrived first. Incidentally, a predetermined time slot is assigned to the output of each packet multiplexer 1 by the time division multiplexer 2, and the output of this assigned time slot is sent out from the transmission line 4.

〔Example〕

[Outline of Configuration] (FIG. 2) FIG. 2 is a diagram showing the configuration of an embodiment of the packet multiplexing device of the present invention. In this figure, #1. ... Denoted by #n are n packet multiplexing sub-modules, 2-1 is a time slot control unit, 2-4 is a gate switch unit, and each packet multiplexing sub-module further includes a packet multiplexing unit. 1. Remaining byte number/transfer byte number detection unit 2-2
and a time slot setting section 2-3.

Of the above configurations, the packet multiplexer 1 corresponds to the packet multiplexer 1 in FIG. 1, and includes a time slot controller 2-1, a remaining byte number/transfer byte number detector 2-2,
The configuration consisting of the time slot setting section 2-3 and the gate switch section 2-4 corresponds to the time division multiplexing section 2 in FIG.

n packet multiplexing sub-modules #1. . . . #n accommodates a plurality of high-speed packet terminals 3, and packets sent out from these plurality of packet terminals 3 are input to the packet multiplexing unit 1 and packet-multiplexed. The remaining byte number/transfer byte number detection unit 2-2 detects the sum of the number of packet bytes (remaining byte number) stored in the packet multiplexing unit 1 in each of the packet multiplexing sub-modules.
, and the number of bytes transferred from the packet multiplexer 1. In order to ensure that the output from each packet multiplexing sub-module is output within a predetermined allocated time slot, the time slot setting section 2-3 configures the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 to set the time slot setting unit 2-3 in the time division multiplexing frame of the allocated time slot. This is the part that sets the start timing (transfer start position) and width (permissible number of bytes). The gate switch section 2-4 has each packet multiplexing sub-module #1゜.
. . . during the time slot assigned to #n, each submodule #1 . . . . This is the part that connects the signal line 12 from #n to the transmission line 4. Time slot control unit 2-
1 is each packet multiplexing sub-module #1.1 detected by the remaining byte number and transfer byte number detection unit 2-2.
. . . Adjust and determine time slot allocation to each packet multiplexing sub-module in the next frame of time division multiplexing based on the number of remaining bytes and the number of transferred bytes in #n.

[Basic Operation] (FIG. 2) With the above basic configuration, the operation of the packet multiplexing device shown in FIG. 2 is as follows. Each packet multiplexing sub-module #l, ... #n accommodates a number of high-speed packet terminals that can be processed even by a conventional packet multiplexing device (1 in Fig. 4). The packet multiplexing unit 1 performs packet multiplexing in the same way as in the conventional case. At this time, the number of bytes transferred from within the packet multiplexing section 1 in one frame of time division multiplexing immediately before that point (transfer byte number) and the number of bytes remaining in the packet multiplexing section 1 (remaining byte number) are calculated. It is detected by the remaining byte number/transfer byte number detection unit 2-2. The time slot control unit 2-1 controls each of the packet multiplexing submodules #
1. ...Based on the number of remaining bytes and the number of transferred bytes in #n, calculate and determine the time slot to be assigned to each packet multiplexing submodule in the next frame of time division multiplexing, and The value is set in the time slot setting section 2- in each packet multiplexing sub-module.
3 and the gate switch section 2-4. Based on the setting value of the time slot setting section 2-3, the packet multiplexing section 1 in each packet multiplexing sub-module outputs only during the set time slot. Further, the gate switch section 2-4 also connects the signal line 12 from each sub-module to the transmission line 4 at the same timing as the output from each sub-module. In this way, the packetized data from each packet terminal 3 is subjected to normal packet multiplexing, and then time division multiplexed and outputted from the transmission line 4.

[Details of Configuration and Operation] (FIG. 2) In the following, a more detailed configuration of each part constituting the packet multiplexing device of FIG. 2 will be described.

The packet multiplexing section 1 includes a packet multiplexing control circuit 10, a buffer memory 11, and a selector 13.

The basic functions of each of these are the same as those shown in FIG. The selector 13 is controlled to output only in the determined time slot, and each buffer memory 11 sends the remaining byte number to the remaining byte number/transfer byte number detection unit 2-2, and the selector 1
3 sends the number of transferred bytes to the remaining byte number/transfer byte number detection unit 2-2.

By the way, the packet multiplexing control circuit IO also performs abnormality detection and other tasks in the packetized data sent from the packet terminal 3, and in order to be compatible with various protocols, usually It is composed of a microprocessor rather than hardware logic, and the above control is performed by software.

The remaining byte number/transfer byte number detector 2 - 2 includes a remaining byte number counter 23 , a transfer byte number counter 24 , and a sender 25 . The remaining byte number counter 23 inputs the number of remaining bytes in each buffer memory 11 of the packet multiplexing section 1 for each frame of time division multiplexing, calculates the sum of these, and sends the sum to the sender 25. The transfer byte number counter 24 receives information about the number of transfer bytes from the selector 13 of the packet multiplexer 1, counts this information, and sends it to the sender 25. The sender 25 includes a driver for sending the number of remaining bytes and the number of transferred bytes to the time slot controller 2-1.

The time slot control unit 2-1 is composed of a time slot adjustment diagram 8r20, a time slot management memory 21, and registers 22-1 and 22-2 provided in pairs corresponding to each packet multiplexing submodule. .

The time slot management memory 21 stores each submodule #1. ...The start time (transfer start position) and width (permissible number of bytes) in one frame of time division multiplexing of the time slot assigned to #n are stored, and these initial values can be input from the outside at the time of setup. Set. A pair of registers 22-1.

22-2, the number of remaining bytes and the number of transferred bytes are alternately input from the remaining byte number/transfer byte number detecting section 2-2 for each time-division multiplexed frame, and a pair of registers 22-2 are input to the register 22-2.
When input to either 2-1 or 22-2,
The other one is used for reading, so that writing and reading can be performed simultaneously. The time slot adjustment circuit 2o includes the register 22-1 or 22-1.
-2, while making adjustments between each packet multiplexing sub-module based on the number of remaining bytes and the number of transferred bytes input to the time slot management memory 2.
Set the timeslot start time and width values within 1.

The time slot adjustment circuit 20 is implemented by a microprocessor or hardware logic. An example of the details of the control procedure will be shown later.

The time slot setting section 2-3 consists of a pair of transfer start position registers 26-1, 26-2 and a pair of allowable byte number registers 27-1, 27-2. The outputs of the time slot control section 2-1 are set in these registers, and as described above, the packet multiplexing control circuit 10 of the packet multiplexing section 1 sets the outputs of the selector 13 based on the values of these registers. control. Further, the reason why each of these registers is configured as a pair is due to the same reason as the registers 22-1 and 22-2 of the time slot control section 2-1.

The gate switch unit 2-4 includes gate opening/closing control information memories 2B-1 and 28-2, a gate control circuit 29, and a gate switch 30. Gate opening/closing control information memory 2
Are 8-1 and 28-2 based on the time slot system? H12
-1 for each packet multiplexing submodule #1. . . . #n is stored, and the gate control circuit 29 controls the opening and closing of each gate switch 30 according to the width of these stored time slots. The reason why the gate opening/closing control information memories 28-1 and 28-2 are configured as a pair is also because the registers 22-1 and 22-2
This is the same as in the case of

In addition, all the operations of the above-mentioned parts are performed for each frame of time division multiplexing, and time slot allocation means assigning a basic frame of a predetermined value (for example, 4m5ec) to each packet multiplexing submodule #1. ．． . . . How to distribute it to #n.

[Procedure for controlling the time slot adjustment circuit 20] (3rd A
3B, 3C, and 3C) Next, an example of the control procedure of the time slot adjustment circuit 2'0 of FIG. 2 will be described with reference to FIGS. 3A, 3B, and 3C.

After starting in step 300, in step 301, the packet multiplexing sub-module #1 of FIG.
For each of n, the number of bytes of data remaining in all buffer memories of the packet multiplexing section 1 during one frame of the immediately previous time division multiplexing is checked.

If the remaining number of bytes is 0, the process proceeds to step 302, where the amount of data transferred from the packet multiplexing submodule and the allowable number of bytes allocated to the packet multiplexing submodule in one frame of the previous time division multiplexing are determined. and compares this ratio with a predetermined parameter α (eg, 50)%. When the data transfer amount is less than 50%, in step 303, an indication is written in a part of the time slot management memory 21 that the packet multiplexing submodule is subject to time slot width (allowable number of bytes) reduction. Display (for example, set Pi=1). Then, in step 304, the content of the register that stores the number of empty bytes (number of bytes that can be reduced) in all submodules is set to β (a separately predetermined value, for example, 30 ) Add %. Next, proceed to step 309 and
All submodules #1. . . . For #n, it is checked whether reading of the number of remaining bytes and the number of transferred bytes has been completed, and if there is a submodule that has not been completed, the operations from step 301 are performed for that submodule.

By the way, in step 302 above, if the number of transferred bytes is equal to or greater than α% of the allowable byte number, it is determined that the allocation of the allowable byte number should not be reduced, and step 3
06, in the time slot management memory 21,
The time slot width (permissible number of bytes) of the packet multiplexing sub-module is displayed as it is (Pi = 0), and the process advances to step 309.

Now, when the number of remaining bytes is not 0 in step 301, the process proceeds to step 305, where the ratio of the remaining number of bytes to the allocated allowable number of bytes is calculated, and this is calculated as γ (
It is compared with a separately given number, for example 20%. Here, if the remaining number of bytes is less than 1%, step 306
Proceed to. If the ratio is 1% or more in step 305, the process proceeds to step 307, and a message is displayed in the time slot management memory 21 that the packet multiplexing submodule is subject to increase in the time slot width (allowable number of bytes). For example, let Pi=2), and further, step 30
Proceed to step 8 to determine the number of remaining bytes T in all submodules.
The number of remaining bytes in the submodule is added to the contents of the register that stores . Then, the process advances to step 309. All the above operations are performed in submodule #1.・
. . . When the processing for #n is completed, the process proceeds to the next step 310. Up to this point, each packet multiplexing sub-module #1.
...This is a procedure for classifying #n as being subject to time slot width reduction, maintaining the status quo, or increasing, depending on the number of remaining bytes and the number of transferred bytes in one frame of the previous time division multiplex. be.

Next, in step 310, T=0, that is, a submodule whose remaining byte count is 1% or more of the allocated allowable byte count among all submodules during one frame of the previous time division multiplexing. When T, which is the sum of all the remaining byte counts in the time slot As there is no need to reconfigure the width, step 3
21 to the transfer start position register 26-1 or 26-2 and the allowable byte number register 27-1 or 27-2 in FIG. 2, and also to the gate opening/closing control information memory 28, -1 or 28-2 in step 322. , set the same value as that corresponding to the time slot allocated in one frame of the immediately previous time division multiplex. In this case, time slot allocation for the next frame of time division multiplexing is now completed.

In step 310, TK is O, and in step 311, I=O1, that is, the number of transferred bytes is less than α% of the allocated allowable number of bytes in all submodules during one frame of the previous time division multiplexing. When the sum of β% of the allowed number of bytes in the submodules that were It is determined that there are no empty bytes for resetting the slot width, and the process advances to step 321.

T gear 0° in both step 310 and 311■
When KiO is selected, the target for which the time slot width should be increased is
Since there are empty bytes, there is room to readjust the time slot width, and the process proceeds to the next step 312. Step 312
In step 313, when ■ and T are compared and I) T, that is, the sum of the number of empty bytes is equal to or greater than the sum of the number of bytes to be increased, in step 313, the time slot width is increased. Add the remaining number of bytes of each submodule (Pi-2) stored in the register 22-1 or 22-2 to the allowable number of bytes in the time slot management memory 21. , this is done for all submodules with Pi=2 (step 314). Next, the process proceeds to step 315, where the number of allowable bytes in the time slot management memory 21 is reduced by βx-% for each of the submodules (those with Pi=1) targeted for time slot width reduction. Pi-
1 for all submodules (step 316).

The process then proceeds to step 321, where these adjusted values are set in the registers 26-1.27-1.28-1° or 26-2.27-2.28-2.

When I<T in step 312, that is, when the sum of the number of bytes to be increased is greater than the sum of the number of empty bytes, in step 317, the time slot width is increased by the submodule (Pi = 2). -% of the remaining number of bytes of the submodule stored in the register 22-1 or 22-2 is added to the allowable number of bytes in the time slot management memory 21 for each of the submodules, and this is calculated as Pi=2. This is done for all sub-modules (step 318). Next, proceeding to step 319, each of the submodules (those with Pi=1) that are subject to the time slot width reduction,
The allowable number of bytes in the time slot management memory 21 is set to β%.
reduce This is done for all submodules with Pi=1 (step 316). Then, step 32
1 and stores these adjusted values in the register 26-1.
1.27-1゜28-1 or 26-2.27-2.2
Set to 8-2.

[Effects of the discrete multiplexer shown in FIG. 2] As is clear from the above explanation, the packet multiplexer having the configuration shown in FIG. A packet multiplexing device that enables high-capacity, high-speed data transmission is realized. Furthermore, by performing time division multiplexing, an increase in traffic (increase in the number of packets) from a specific terminal does not affect other packet terminals. Furthermore, according to the configuration shown in FIG. 2, the assignment of time slots for time division multiplexing is variable, so it is flexible with respect to traffic fluctuations.

〔Effect of the invention〕

According to the present invention, compared to conventional packet multiplexing devices, the amount of hardware is small, that is, low cost, high speed, and large capacity, and moreover, an increase in traffic from a specific terminal (increase in the number of packets) can cause other devices to A packet multiplexing device is realized in which packet terminals are not affected.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the packet multiplexing device of the present invention, FIG. 2 is a configuration diagram of an embodiment of the packet multiplexing device of the present invention, and FIG. 3A, FIG. 3B, and FIG. 3C are the diagrams shown in FIG. FIG. 4 is a diagram showing the configuration of the conventional packet multiplexer 1 and its surroundings; FIG. 5 is a diagram showing an example of the control procedure of the time slot adjustment circuit 20 of FIG. It is a figure showing an example of composition for. (Explanation of symbols) 1...Packet multiplexing unit, 1-1, 1-2,...1-3...Packet multiplexing device, 2...Time division multiplexing unit, 2-1...Time Slot control unit, 2-2... Remaining byte number/transfer byte number detection unit, 2-
3...Time slot setting unit, 2-4...Gate switch unit, 3...Packet terminal device, 4...Transmission path, 10...Packet multiplex control circuit, 11...Buffer memory, DESCRIPTION OF SYMBOLS 12... Signal line, 13... Selector, 20... Time slot adjustment circuit, 21... Time slot management memory, 22-1, 2
2-2...Register, 23...Remaining byte number counter, 24...Transfer byte number counter, 25...Sender, 26-1, 26-2...Transfer start position register, 2
7-1, 27-2... Allowable byte number register, 28
-1, 28-2...Gate opening/closing control information memory, 2
9... Gate control circuit, 30... Gate switch.

Claims (1)

[Claims] 1. Packetized data sent from each of the plurality of terminals (3) is temporarily stored in a buffer memory, and sent out from the first transmission line (12) in order from the packet that arrived first. In a packet multiplexing device comprising a plurality of packet multiplexing units (1), a predetermined time slot is assigned to each of the outputs of the plurality of packet multiplexing units (1), and the output of each of the packet multiplexing units (1) is a time division multiplexer (2) that outputs from the second transmission line (4) within the assigned time slot;
) A packet multiplexing device comprising: 2. Detecting the sum of the amount of data stored in the buffer memory (11) in each of the packet multiplexing units (1) and the amount of data sent out from each of the packet multiplexing units (1),
The packet multiplexing apparatus according to claim 1, further comprising a time slot control section (2-1) for adjusting the width of the time slot allocated to each packet multiplexing section (1).